Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	728249920	0	0	627
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	728249920	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	728249920	728090017	0	0
tb.dut.CheckAccuCntDw	0	0	627	627	0	0
tb.dut.CheckEscCntDw	0	0	627	627	0	0
tb.dut.CheckNAlerts	0	0	627	627	0	0
tb.dut.CheckNClasses	0	0	627	627	0	0
tb.dut.CheckNEscSev	0	0	627	627	0	0
tb.dut.CrashdumpKnownO_A	0	0	728249920	728090017	0	0
tb.dut.EdnKnownO_A	0	0	728249920	728090017	0	0
tb.dut.EscPKnownO_A	0	0	728249920	728090017	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	728249920	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	728249920	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	728249920	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	728249920	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	728249920	70	0	0
tb.dut.IrqAKnownO_A	0	0	728249920	728090017	0	0
tb.dut.IrqBKnownO_A	0	0	728249920	728090017	0	0
tb.dut.IrqCKnownO_A	0	0	728249920	728090017	0	0
tb.dut.IrqDKnownO_A	0	0	728249920	728090017	0	0
tb.dut.TlAReadyKnownO_A	0	0	728249920	728090017	0	0
tb.dut.TlDValidKnownO_A	0	0	728249920	728090017	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	755487171	3213741	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	755487171	17102	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	755487171	18255	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	755487171	16738	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	755487171	17842	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	755487171	18480	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	755487171	18253	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	755487171	16627	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	755487171	16772	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	755487171	18080	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	755487171	17219	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	755487171	16921	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	755487171	19137	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	755487171	16869	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	755487171	19209	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	755487171	19407	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	755487171	17322	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	755487171	16838	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	755487171	17258	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	755487171	17670	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	755487171	19385	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	755487171	17266	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	755487171	17123	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	755487171	17968	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	755487171	16773	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	755487171	18380	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	755487171	18133	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	755487171	17884	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	755487171	17117	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	755487171	17211	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	755487171	18288	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	755487171	17031	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	755487171	17168	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	755487171	18302	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	755487171	17193	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	755487171	18098	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	755487171	18016	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	755487171	17168	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	755487171	17369	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	755487171	17086	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	755487171	16956	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	755487171	19493	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	755487171	17046	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	755487171	18264	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	755487171	18098	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	755487171	18153	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	755487171	17347	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	755487171	17845	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	755487171	18407	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	755487171	18497	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	755487171	17143	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	755487171	16397	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	755487171	17473	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	755487171	17740	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	755487171	16987	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	755487171	18204	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	755487171	17197	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	755487171	19042	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	755487171	19004	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	755487171	17069	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	755487171	18177	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	755487171	17620	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	755487171	17032	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	755487171	18100	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	755487171	16730	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	755487171	17102	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	755487171	17950	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	755487171	17163	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	755487171	17957	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	755487171	17027	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	755487171	33821	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	755487171	18107	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	755487171	18174	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	755487171	16818	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	755487171	18235	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	755487171	16890	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	755487171	18753	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	755487171	19446	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	755487171	17140	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	728249920	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	728249920	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	728249920	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	728249920	3870	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	728249920	252052	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	728249920	354037805	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	728249920	273	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	728249920	862	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	728249920	51	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	728249920	413	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	728039355	259167858	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	728249920	939	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	728249920	916	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	728249920	898	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	728249920	882	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	728249920	1419	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	728249920	152288	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	728249920	1318	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	728249920	48	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	728249920	1243	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	728249920	1033	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	728037453	727967243	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	627	627	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	728249920	728090017	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	728249920	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	728249920	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	728249920	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	728249920	2772	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	728249920	186061	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	728249920	395100702	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	728249920	248	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	728249920	511	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	728249920	21	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	728249920	235	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	728039355	312008601	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	728249920	589	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	728249920	576	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	728249920	560	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	728249920	544	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	728249920	892	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	728249920	108838	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	728249920	805	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	728249920	63	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	728249920	1206	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	728249920	996	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	728037453	727967243	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	627	627	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	728249920	728090017	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	728249920	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	728249920	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	728249920	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	728249920	2042	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	728249920	163147	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	728249920	424428360	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	728249920	319	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	728249920	505	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	728249920	17	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	728249920	210	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	728039355	326803574	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	728249920	573	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	728249920	562	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	728249920	557	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	728249920	546	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	728249920	1069	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	728249920	114138	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	728249920	992	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	728249920	59	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	728249920	1299	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	728249920	1089	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	728037453	727967243	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	627	627	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	728249920	728090017	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	728249920	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	728249920	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	728249920	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	728249920	5148	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	728249920	191633	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	728249920	403073473	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	728249920	197	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	728249920	508	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	728249920	23	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	728249920	213	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	728039355	314333748	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	728249920	579	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	728249920	568	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	728249920	558	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	728249920	549	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	728249920	1262	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	728249920	155940	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	728249920	1184	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	728249920	55	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	728249920	1220	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	728249920	1010	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	728037453	727967243	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	627	627	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	728249920	728090017	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	755487171	136624777	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	755487171	754805274	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	755487171	754805274	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	755487171	207520633	0	0
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tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	832	832	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	832	832	0	0

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