Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.61	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	2	42	95.45

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	2	42	95.45	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	165	1			T19	1		T6	1		T15	1
index[0x1]	178	1			T6	3		T20	1		T7	1
index[0x2]	166	1			T1	1		T6	2		T22	3
index[0x3]	176	1			T1	1		T29	1		T42	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	181	1			T19	1		T6	2		T15	1
lens_less_than_1000[1]	148	1			T1	2		T6	3		T7	1
lens_less_than_1000[2]	108	1			T6	1		T20	1		T26	1
lens_less_than_1000[3]	74	1			T29	2		T42	1		T22	1
lens_less_than_1000[4]	54	1			T13	1		T70	1		T266	1
lens_less_than_1000[5]	34	1			T22	1		T64	1		T80	1
lens_less_than_1000[6]	39	1			T15	2		T46	1		T35	1
lens_less_than_1000[7]	14	1			T79	1		T80	1		T46	1
lens_less_than_1000[8]	16	1			T22	2		T79	1		T255	2
lens_less_than_1000[9]	5	1			T239	1		T290	3		T204	1
len_2	12	1			T291	1		T46	1		T72	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	2	42	95.45	2

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x1] , index[0x2]]	[lens_less_than_1000[9]]	--	--	2

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	38	1			T19	1		T6	1		T22	1
index[0x0]	lens_less_than_1000[1]	29	1			T26	1		T89	1		T80	1
index[0x0]	lens_less_than_1000[2]	28	1			T26	1		T46	2		T292	1
index[0x0]	lens_less_than_1000[3]	22	1			T23	2		T100	1		T293	1
index[0x0]	lens_less_than_1000[4]	15	1			T80	1		T52	1		T294	1
index[0x0]	lens_less_than_1000[5]	7	1			T81	2		T36	1		T295	1
index[0x0]	lens_less_than_1000[6]	11	1			T15	1		T296	2		T297	1
index[0x0]	lens_less_than_1000[7]	5	1			T95	1		T298	3		T24	1
index[0x0]	lens_less_than_1000[8]	2	1			T299	1		T286	1		-	-
index[0x0]	lens_less_than_1000[9]	4	1			T290	3		T204	1		-	-
index[0x0]	len_2	4	1			T300	2		T301	1		T302	1
index[0x1]	lens_less_than_1000[0]	59	1			T6	1		T15	1		T22	3
index[0x1]	lens_less_than_1000[1]	38	1			T6	1		T7	1		T15	1
index[0x1]	lens_less_than_1000[2]	26	1			T6	1		T20	1		T86	1
index[0x1]	lens_less_than_1000[3]	16	1			T29	1		T256	1		T50	1
index[0x1]	lens_less_than_1000[4]	10	1			T13	1		T70	1		T266	1
index[0x1]	lens_less_than_1000[5]	11	1			T80	1		T52	1		T95	1
index[0x1]	lens_less_than_1000[6]	8	1			T15	1		T231	1		T303	1
index[0x1]	lens_less_than_1000[7]	5	1			T80	1		T95	1		T96	1
index[0x1]	lens_less_than_1000[8]	1	1			T87	1		-	-		-	-
index[0x1]	len_2	4	1			T291	1		T273	1		T187	1
index[0x2]	lens_less_than_1000[0]	36	1			T16	1		T26	1		T200	1
index[0x2]	lens_less_than_1000[1]	47	1			T1	1		T6	2		T64	1
index[0x2]	lens_less_than_1000[2]	24	1			T85	1		T23	1		T80	1
index[0x2]	lens_less_than_1000[3]	20	1			T22	1		T33	1		T49	1
index[0x2]	lens_less_than_1000[4]	16	1			T226	1		T101	1		T304	3
index[0x2]	lens_less_than_1000[5]	6	1			T305	1		T306	1		T236	1
index[0x2]	lens_less_than_1000[6]	9	1			T232	1		T307	1		T114	1
index[0x2]	lens_less_than_1000[7]	2	1			T79	1		T306	1		-	-
index[0x2]	lens_less_than_1000[8]	4	1			T22	2		T255	2		-	-
index[0x2]	len_2	2	1			T46	1		T72	1		-	-
index[0x3]	lens_less_than_1000[0]	48	1			T22	1		T201	1		T80	1
index[0x3]	lens_less_than_1000[1]	34	1			T1	1		T22	2		T86	1
index[0x3]	lens_less_than_1000[2]	30	1			T78	2		T50	1		T308	1
index[0x3]	lens_less_than_1000[3]	16	1			T29	1		T42	1		T16	1
index[0x3]	lens_less_than_1000[4]	13	1			T91	1		T309	1		T95	1
index[0x3]	lens_less_than_1000[5]	10	1			T22	1		T64	1		T46	2
index[0x3]	lens_less_than_1000[6]	11	1			T46	1		T35	1		T59	1
index[0x3]	lens_less_than_1000[7]	2	1			T46	1		T114	1		-	-
index[0x3]	lens_less_than_1000[8]	9	1			T79	1		T40	5		T297	1
index[0x3]	lens_less_than_1000[9]	1	1			T239	1		-	-		-	-
index[0x3]	len_2	2	1			T310	1		T302	1		-	-