Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.74	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	5	35	87.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	5	35	87.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	48	1			T2	1		T5	1		T19	4
class_index[0x1]	63	1			T20	1		T82	1		T15	1
class_index[0x2]	59	1			T1	1		T19	1		T6	2
class_index[0x3]	55	1			T19	1		T89	1		T44	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	92	1			T1	1		T2	1		T6	2
intr_timeout_cnt[1]	50	1			T5	1		T20	1		T15	1
intr_timeout_cnt[2]	24	1			T19	2		T89	1		T80	1
intr_timeout_cnt[3]	8	1			T86	1		T23	1		T100	1
intr_timeout_cnt[4]	9	1			T54	3		T269	1		T270	2
intr_timeout_cnt[5]	14	1			T19	4		T271	1		T59	1
intr_timeout_cnt[6]	5	1			T109	1		T113	1		T272	1
intr_timeout_cnt[7]	7	1			T50	2		T100	1		T104	1
intr_timeout_cnt[8]	11	1			T20	1		T50	1		T101	1
intr_timeout_cnt[9]	5	1			T104	1		T273	1		T113	3

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	5	35	87.50	5

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[5] , intr_timeout_cnt[6]]	--	--	2
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	26	1			T2	1		T80	1		T46	1
class_index[0x0]	intr_timeout_cnt[1]	8	1			T5	1		T85	1		T80	1
class_index[0x0]	intr_timeout_cnt[2]	1	1			T274	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[3]	1	1			T23	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[4]	1	1			T270	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[5]	7	1			T19	4		T59	1		T275	1
class_index[0x0]	intr_timeout_cnt[7]	1	1			T104	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[8]	2	1			T20	1		T276	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	1	1			T104	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	27	1			T82	1		T80	1		T52	1
class_index[0x1]	intr_timeout_cnt[1]	9	1			T20	1		T15	1		T23	1
class_index[0x1]	intr_timeout_cnt[2]	10	1			T49	1		T100	1		T242	1
class_index[0x1]	intr_timeout_cnt[3]	3	1			T86	1		T190	1		T277	1
class_index[0x1]	intr_timeout_cnt[4]	4	1			T54	3		T269	1		-	-
class_index[0x1]	intr_timeout_cnt[5]	4	1			T271	1		T185	1		T278	1
class_index[0x1]	intr_timeout_cnt[6]	3	1			T113	1		T270	1		T278	1
class_index[0x1]	intr_timeout_cnt[7]	1	1			T279	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	2	1			T50	1		T236	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	22	1			T1	1		T6	2		T22	1
class_index[0x2]	intr_timeout_cnt[1]	14	1			T65	1		T121	1		T280	1
class_index[0x2]	intr_timeout_cnt[2]	7	1			T19	1		T80	1		T49	1
class_index[0x2]	intr_timeout_cnt[3]	3	1			T281	1		T183	1		T276	1
class_index[0x2]	intr_timeout_cnt[4]	2	1			T270	1		T282	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	3	1			T283	1		T109	1		T284	1
class_index[0x2]	intr_timeout_cnt[6]	2	1			T109	1		T272	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	1	1			T100	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[8]	1	1			T285	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	4	1			T273	1		T113	3		-	-
class_index[0x3]	intr_timeout_cnt[0]	17	1			T52	1		T103	1		T242	1
class_index[0x3]	intr_timeout_cnt[1]	19	1			T44	1		T102	1		T275	1
class_index[0x3]	intr_timeout_cnt[2]	6	1			T19	1		T89	1		T272	1
class_index[0x3]	intr_timeout_cnt[3]	1	1			T100	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[4]	2	1			T286	1		T287	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	4	1			T50	2		T288	1		T269	1
class_index[0x3]	intr_timeout_cnt[8]	6	1			T101	1		T104	1		T289	1