Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	361011	1			T1	33		T2	25		T3	19
all_values[1]	361011	1			T1	33		T2	25		T3	19
all_values[2]	361011	1			T1	33		T2	25		T3	19
all_values[3]	361011	1			T1	33		T2	25		T3	19

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

718553

1

T1

73

T2

50

T4

3517

auto[1]

725491

1

T1

59

T2

50

T3

76

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

856324

1

T1

69

T2

52

T3

66

auto[1]

587720

1

T1

63

T2

48

T3

10

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	102415	1			T1	7		T2	6		T4	442
all_values[0]	auto[0]	auto[1]	76894	1			T1	7		T2	6		T4	436
all_values[0]	auto[1]	auto[0]	104355	1			T1	10		T2	7		T3	17
all_values[0]	auto[1]	auto[1]	77347	1			T1	9		T2	6		T3	2
all_values[1]	auto[0]	auto[0]	107193	1			T1	8		T2	6		T4	448
all_values[1]	auto[0]	auto[1]	72888	1			T1	8		T2	6		T4	446
all_values[1]	auto[1]	auto[0]	107953	1			T1	10		T2	7		T3	17
all_values[1]	auto[1]	auto[1]	72977	1			T1	7		T2	6		T3	2
all_values[2]	auto[0]	auto[0]	107697	1			T1	9		T2	5		T4	432
all_values[2]	auto[0]	auto[1]	71497	1			T1	9		T2	4		T4	423
all_values[2]	auto[1]	auto[0]	109322	1			T1	8		T2	8		T3	18
all_values[2]	auto[1]	auto[1]	72495	1			T1	7		T2	8		T3	1
all_values[3]	auto[0]	auto[0]	108087	1			T1	13		T2	9		T4	446
all_values[3]	auto[0]	auto[1]	71882	1			T1	12		T2	8		T4	444
all_values[3]	auto[1]	auto[0]	109302	1			T1	4		T2	4		T3	14
all_values[3]	auto[1]	auto[1]	71740	1			T1	4		T2	4		T3	5