Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	361011	1			T1	33		T2	25		T3	19
all_pins[1]	361011	1			T1	33		T2	25		T3	19
all_pins[2]	361011	1			T1	33		T2	25		T3	19
all_pins[3]	361011	1			T1	33		T2	25		T3	19

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1149485	1			T1	105		T2	76		T3	66
values[0x1]	294559	1			T1	27		T2	24		T3	10
transitions[0x0=>0x1]	194813	1			T1	17		T2	14		T3	9
transitions[0x1=>0x0]	195067	1			T1	17		T2	14		T3	10

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	283664	1			T1	24		T2	19		T3	17
all_pins[0]	values[0x1]	77347	1			T1	9		T2	6		T3	2
all_pins[0]	transitions[0x0=>0x1]	76676	1			T1	9		T2	6		T3	1
all_pins[0]	transitions[0x1=>0x0]	71323	1			T1	4		T2	4		T3	5
all_pins[1]	values[0x0]	288034	1			T1	26		T2	19		T3	17
all_pins[1]	values[0x1]	72977	1			T1	7		T2	6		T3	2
all_pins[1]	transitions[0x0=>0x1]	39659	1			T1	2		T2	3		T3	2
all_pins[1]	transitions[0x1=>0x0]	44029	1			T1	4		T2	3		T3	2
all_pins[2]	values[0x0]	288516	1			T1	26		T2	17		T3	18
all_pins[2]	values[0x1]	72495	1			T1	7		T2	8		T3	1
all_pins[2]	transitions[0x0=>0x1]	39571	1			T1	3		T2	5		T3	1
all_pins[2]	transitions[0x1=>0x0]	40053	1			T1	3		T2	3		T3	2
all_pins[3]	values[0x0]	289271	1			T1	29		T2	21		T3	14
all_pins[3]	values[0x1]	71740	1			T1	4		T2	4		T3	5
all_pins[3]	transitions[0x0=>0x1]	38907	1			T1	3		T3	5		T4	219
all_pins[3]	transitions[0x1=>0x0]	39662	1			T1	6		T2	4		T3	1