Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	91040	1			T4	1119		T20	382		T13	220
accum_cnt_1000	245885	1			T4	1239		T6	36		T20	2375
accum_cnt_100	28679	1			T4	64		T19	7		T6	116
accum_cnt_50	68890	1			T1	25		T2	16		T4	66
accum_cnt_10	196940	1			T1	32		T2	19		T3	11
accum_cnt_0	386634	1			T1	31		T2	61		T3	37

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	265769	1			T1	22		T2	24		T3	12
class_index[0x1]	265769	1			T1	22		T2	24		T3	12
class_index[0x2]	265769	1			T1	22		T2	24		T3	12
class_index[0x3]	265769	1			T1	22		T2	24		T3	12

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	26884	1			T20	294		T13	220		T16	180
class_index[0x0]	accum_cnt_1000	63776	1			T6	36		T20	285		T7	800
class_index[0x0]	accum_cnt_100	7600	1			T6	73		T20	321		T7	58
class_index[0x0]	accum_cnt_50	14800	1			T1	17		T5	2		T19	7
class_index[0x0]	accum_cnt_10	54812	1			T1	5		T2	13		T17	17
class_index[0x0]	accum_cnt_0	82051	1			T2	11		T3	12		T4	1383
class_index[0x1]	accum_cnt_2000	21686	1			T20	18		T78	694		T79	242
class_index[0x1]	accum_cnt_1000	65308	1			T20	873		T7	813		T15	15
class_index[0x1]	accum_cnt_100	8467	1			T19	7		T6	20		T20	68
class_index[0x1]	accum_cnt_50	18142	1			T5	13		T19	9		T6	80
class_index[0x1]	accum_cnt_10	42105	1			T3	5		T4	2		T5	4
class_index[0x1]	accum_cnt_0	99716	1			T1	22		T2	24		T3	7
class_index[0x2]	accum_cnt_2000	20924	1			T4	553		T78	633		T257	133
class_index[0x2]	accum_cnt_1000	52847	1			T4	745		T20	64		T15	23
class_index[0x2]	accum_cnt_100	6139	1			T4	35		T6	23		T20	20
class_index[0x2]	accum_cnt_50	20606	1			T2	16		T4	33		T5	6
class_index[0x2]	accum_cnt_10	56151	1			T1	16		T2	6		T4	9
class_index[0x2]	accum_cnt_0	101673	1			T1	6		T2	2		T3	12
class_index[0x3]	accum_cnt_2000	21546	1			T4	566		T20	70		T64	417
class_index[0x3]	accum_cnt_1000	63954	1			T4	494		T20	1153		T22	130
class_index[0x3]	accum_cnt_100	6473	1			T4	29		T20	178		T15	43
class_index[0x3]	accum_cnt_50	15342	1			T1	8		T4	33		T5	10
class_index[0x3]	accum_cnt_10	43872	1			T1	11		T3	6		T4	10
class_index[0x3]	accum_cnt_0	103194	1			T1	3		T2	24		T3	6