Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	2769	1			T6	23		T7	1		T28	96
alert[0x1]	5858	1			T5	3		T28	105		T23	1
alert[0x2]	6406	1			T8	1		T28	221		T89	2
alert[0x3]	5311	1			T7	1		T28	257		T69	1
alert[0x4]	3676	1			T6	3		T7	1		T15	2
alert[0x5]	4446	1			T6	30		T15	42		T16	1
alert[0x6]	3541	1			T6	91		T20	9		T15	360
alert[0x7]	3856	1			T3	1		T7	1		T28	236
alert[0x8]	7739	1			T9	1		T28	56		T251	1
alert[0x9]	2415	1			T6	18		T20	9		T8	1
alert[0xa]	10175	1			T19	3		T20	1		T15	8
alert[0xb]	4263	1			T3	1		T15	2		T28	195
alert[0xc]	3382	1			T6	33		T20	1		T28	41
alert[0xd]	5796	1			T8	1		T69	1		T23	36
alert[0xe]	5555	1			T6	130		T28	2		T77	64
alert[0xf]	7382	1			T6	76		T8	1		T28	53
alert[0x10]	11052	1			T19	7		T28	67		T69	2
alert[0x11]	4333	1			T19	4		T15	13		T89	1
alert[0x12]	4329	1			T28	224		T69	1		T33	62
alert[0x13]	5320	1			T6	282		T8	1		T15	1
alert[0x14]	5914	1			T8	1		T28	65		T248	1
alert[0x15]	5140	1			T15	41		T80	32		T251	1
alert[0x16]	5033	1			T15	51		T16	1		T248	1
alert[0x17]	10786	1			T6	2		T20	6		T86	1
alert[0x18]	5973	1			T6	9		T15	10		T16	35
alert[0x19]	7951	1			T19	32		T6	338		T20	3
alert[0x1a]	6874	1			T19	1		T8	1		T28	926
alert[0x1b]	5754	1			T3	1		T6	3073		T77	58
alert[0x1c]	6777	1			T6	64		T16	3		T28	1468
alert[0x1d]	5773	1			T5	5		T8	1		T28	147
alert[0x1e]	3480	1			T20	4		T28	405		T89	27
alert[0x1f]	6248	1			T15	5		T28	22		T23	3
alert[0x20]	6466	1			T6	28		T15	16		T28	99
alert[0x21]	4257	1			T16	7		T258	1		T72	21
alert[0x22]	941	1			T8	1		T15	2		T28	27
alert[0x23]	4305	1			T6	1645		T28	166		T69	2
alert[0x24]	2097	1			T46	22		T251	1		T72	118
alert[0x25]	7068	1			T15	5		T86	27		T259	31
alert[0x26]	5415	1			T6	1		T8	2		T15	12
alert[0x27]	6288	1			T19	1		T6	44		T28	46
alert[0x28]	8288	1			T20	5		T23	12		T80	13
alert[0x29]	1828	1			T15	1		T9	1		T69	1
alert[0x2a]	7220	1			T19	1		T6	24		T15	1
alert[0x2b]	6143	1			T6	71		T77	3		T259	44
alert[0x2c]	4540	1			T6	278		T28	283		T77	487
alert[0x2d]	5657	1			T3	1		T15	2		T28	180
alert[0x2e]	4298	1			T80	27		T46	6		T258	1
alert[0x2f]	3184	1			T16	23		T28	179		T67	1
alert[0x30]	4720	1			T6	19		T20	2		T28	174
alert[0x31]	1684	1			T6	41		T8	1		T16	55
alert[0x32]	2330	1			T6	201		T20	2		T8	1
alert[0x33]	1913	1			T20	2		T86	6		T23	4
alert[0x34]	2903	1			T15	2		T77	2		T248	1
alert[0x35]	2847	1			T3	1		T28	112		T86	203
alert[0x36]	5058	1			T86	20		T80	29		T251	1
alert[0x37]	4785	1			T6	157		T259	1		T46	3
alert[0x38]	12427	1			T3	1		T15	1		T28	61
alert[0x39]	4881	1			T20	1		T16	3		T28	20
alert[0x3a]	9669	1			T15	54		T248	1		T23	5
alert[0x3b]	6371	1			T6	144		T8	1		T69	1
alert[0x3c]	4941	1			T19	20		T28	121		T23	10
alert[0x3d]	7805	1			T6	58		T8	1		T23	5
alert[0x3e]	3681	1			T6	20		T15	2		T86	119
alert[0x3f]	8727	1			T28	711		T69	1		T80	123
alert[0x40]	9804	1			T9	1		T28	408		T89	4

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	100412	1			T3	2		T5	2		T19	2
class_i[0x1]	117135	1			T19	67		T6	6879		T8	1
class_i[0x2]	69954	1			T6	24		T20	3		T8	9
class_i[0x3]	68347	1			T3	4		T5	6		T20	2

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

355198

1

T5

8

T19

69

T6

6903

alert_ping_fail

650

1

T3

6

T8

15

T7

4

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	2754	1			T6	23		T28	96		T259	1
alert_integrity_fail	alert[0x1]	5847	1			T5	3		T28	105		T23	1
alert_integrity_fail	alert[0x2]	6400	1			T28	221		T89	2		T46	191
alert_integrity_fail	alert[0x3]	5302	1			T28	257		T80	434		T46	23
alert_integrity_fail	alert[0x4]	3671	1			T6	3		T15	2		T46	4
alert_integrity_fail	alert[0x5]	4436	1			T6	30		T15	42		T16	1
alert_integrity_fail	alert[0x6]	3524	1			T6	91		T20	9		T15	360
alert_integrity_fail	alert[0x7]	3840	1			T28	236		T80	17		T46	97
alert_integrity_fail	alert[0x8]	7724	1			T28	56		T49	5		T254	414
alert_integrity_fail	alert[0x9]	2401	1			T6	18		T20	9		T80	84
alert_integrity_fail	alert[0xa]	10157	1			T19	3		T20	1		T15	8
alert_integrity_fail	alert[0xb]	4254	1			T15	2		T28	195		T77	5
alert_integrity_fail	alert[0xc]	3376	1			T6	33		T20	1		T28	41
alert_integrity_fail	alert[0xd]	5789	1			T23	36		T46	20		T72	28
alert_integrity_fail	alert[0xe]	5545	1			T6	130		T28	2		T77	64
alert_integrity_fail	alert[0xf]	7374	1			T6	76		T28	53		T77	14
alert_integrity_fail	alert[0x10]	11045	1			T19	7		T28	67		T77	6
alert_integrity_fail	alert[0x11]	4330	1			T19	4		T15	13		T89	1
alert_integrity_fail	alert[0x12]	4322	1			T28	224		T33	62		T49	13
alert_integrity_fail	alert[0x13]	5307	1			T6	282		T15	1		T77	50
alert_integrity_fail	alert[0x14]	5902	1			T28	65		T80	65		T33	30
alert_integrity_fail	alert[0x15]	5122	1			T15	41		T80	32		T254	225
alert_integrity_fail	alert[0x16]	5018	1			T15	51		T16	1		T259	1
alert_integrity_fail	alert[0x17]	10777	1			T6	2		T20	6		T86	1
alert_integrity_fail	alert[0x18]	5965	1			T6	9		T15	10		T16	35
alert_integrity_fail	alert[0x19]	7945	1			T19	32		T6	338		T20	3
alert_integrity_fail	alert[0x1a]	6866	1			T19	1		T28	926		T77	7
alert_integrity_fail	alert[0x1b]	5742	1			T6	3073		T77	58		T89	2
alert_integrity_fail	alert[0x1c]	6770	1			T6	64		T16	3		T28	1468
alert_integrity_fail	alert[0x1d]	5767	1			T5	5		T28	147		T89	4
alert_integrity_fail	alert[0x1e]	3475	1			T20	4		T28	405		T89	27
alert_integrity_fail	alert[0x1f]	6239	1			T15	5		T28	22		T23	3
alert_integrity_fail	alert[0x20]	6457	1			T6	28		T15	16		T28	99
alert_integrity_fail	alert[0x21]	4250	1			T16	7		T72	21		T40	4
alert_integrity_fail	alert[0x22]	928	1			T15	2		T28	27		T77	91
alert_integrity_fail	alert[0x23]	4297	1			T6	1645		T28	166		T80	207
alert_integrity_fail	alert[0x24]	2088	1			T46	22		T72	118		T228	95
alert_integrity_fail	alert[0x25]	7054	1			T15	5		T86	27		T259	31
alert_integrity_fail	alert[0x26]	5404	1			T6	1		T15	12		T16	29
alert_integrity_fail	alert[0x27]	6278	1			T19	1		T6	44		T28	46
alert_integrity_fail	alert[0x28]	8281	1			T20	5		T23	12		T80	13
alert_integrity_fail	alert[0x29]	1816	1			T15	1		T80	21		T46	24
alert_integrity_fail	alert[0x2a]	7206	1			T19	1		T6	24		T15	1
alert_integrity_fail	alert[0x2b]	6133	1			T6	71		T77	3		T259	44
alert_integrity_fail	alert[0x2c]	4523	1			T6	278		T28	283		T77	487
alert_integrity_fail	alert[0x2d]	5647	1			T15	2		T28	180		T86	2
alert_integrity_fail	alert[0x2e]	4281	1			T80	27		T46	6		T33	251
alert_integrity_fail	alert[0x2f]	3170	1			T16	23		T28	179		T72	560
alert_integrity_fail	alert[0x30]	4711	1			T6	19		T20	2		T28	174
alert_integrity_fail	alert[0x31]	1675	1			T6	41		T16	55		T28	9
alert_integrity_fail	alert[0x32]	2320	1			T6	201		T20	2		T16	6
alert_integrity_fail	alert[0x33]	1897	1			T20	2		T86	6		T23	4
alert_integrity_fail	alert[0x34]	2898	1			T15	2		T77	2		T80	2
alert_integrity_fail	alert[0x35]	2835	1			T28	112		T86	203		T80	145
alert_integrity_fail	alert[0x36]	5048	1			T86	20		T80	29		T108	1
alert_integrity_fail	alert[0x37]	4777	1			T6	157		T259	1		T46	3
alert_integrity_fail	alert[0x38]	12417	1			T15	1		T28	61		T77	20
alert_integrity_fail	alert[0x39]	4874	1			T20	1		T16	3		T28	20
alert_integrity_fail	alert[0x3a]	9657	1			T15	54		T23	5		T259	14
alert_integrity_fail	alert[0x3b]	6367	1			T6	144		T86	1		T80	26
alert_integrity_fail	alert[0x3c]	4932	1			T19	20		T28	121		T23	10
alert_integrity_fail	alert[0x3d]	7797	1			T6	58		T23	5		T80	7
alert_integrity_fail	alert[0x3e]	3676	1			T6	20		T15	2		T86	119
alert_integrity_fail	alert[0x3f]	8719	1			T28	711		T80	123		T46	1
alert_integrity_fail	alert[0x40]	9799	1			T28	408		T89	4		T33	18
alert_ping_fail	alert[0x0]	15	1			T7	1		T69	1		T248	1
alert_ping_fail	alert[0x1]	11	1			T258	1		T313	1		T314	1
alert_ping_fail	alert[0x2]	6	1			T8	1		T315	1		T316	1
alert_ping_fail	alert[0x3]	9	1			T7	1		T69	1		T317	1
alert_ping_fail	alert[0x4]	5	1			T7	1		T317	1		T318	1
alert_ping_fail	alert[0x5]	10	1			T292	1		T34	1		T35	1
alert_ping_fail	alert[0x6]	17	1			T34	1		T319	1		T320	2
alert_ping_fail	alert[0x7]	16	1			T3	1		T7	1		T69	1
alert_ping_fail	alert[0x8]	15	1			T9	1		T251	1		T292	1
alert_ping_fail	alert[0x9]	14	1			T8	1		T248	1		T306	1
alert_ping_fail	alert[0xa]	18	1			T248	2		T292	1		T319	1
alert_ping_fail	alert[0xb]	9	1			T3	1		T69	1		T34	1
alert_ping_fail	alert[0xc]	6	1			T306	2		T321	1		T322	1
alert_ping_fail	alert[0xd]	7	1			T8	1		T69	1		T314	1
alert_ping_fail	alert[0xe]	10	1			T248	2		T251	1		T323	3
alert_ping_fail	alert[0xf]	8	1			T8	1		T251	1		T323	1
alert_ping_fail	alert[0x10]	7	1			T69	2		T248	1		T323	1
alert_ping_fail	alert[0x11]	3	1			T34	1		T306	1		T324	1
alert_ping_fail	alert[0x12]	7	1			T69	1		T321	2		T325	1
alert_ping_fail	alert[0x13]	13	1			T8	1		T248	2		T34	1
alert_ping_fail	alert[0x14]	12	1			T8	1		T248	1		T34	1
alert_ping_fail	alert[0x15]	18	1			T251	1		T258	1		T323	1
alert_ping_fail	alert[0x16]	15	1			T248	1		T292	1		T73	1
alert_ping_fail	alert[0x17]	9	1			T251	1		T107	1		T326	1
alert_ping_fail	alert[0x18]	8	1			T327	1		T328	1		T329	1
alert_ping_fail	alert[0x19]	6	1			T248	1		T34	1		T234	1
alert_ping_fail	alert[0x1a]	8	1			T8	1		T258	1		T319	1
alert_ping_fail	alert[0x1b]	12	1			T3	1		T258	1		T306	1
alert_ping_fail	alert[0x1c]	7	1			T69	1		T319	1		T330	1
alert_ping_fail	alert[0x1d]	6	1			T8	1		T73	1		T331	1
alert_ping_fail	alert[0x1e]	5	1			T323	1		T317	1		T322	1
alert_ping_fail	alert[0x1f]	9	1			T323	1		T332	1		T325	1
alert_ping_fail	alert[0x20]	9	1			T251	1		T258	2		T333	1
alert_ping_fail	alert[0x21]	7	1			T258	1		T34	1		T318	1
alert_ping_fail	alert[0x22]	13	1			T8	1		T292	1		T334	1
alert_ping_fail	alert[0x23]	8	1			T69	2		T34	1		T323	1
alert_ping_fail	alert[0x24]	9	1			T251	1		T306	1		T318	1
alert_ping_fail	alert[0x25]	14	1			T258	2		T335	1		T318	1
alert_ping_fail	alert[0x26]	11	1			T8	2		T248	1		T258	1
alert_ping_fail	alert[0x27]	10	1			T69	2		T258	1		T319	1
alert_ping_fail	alert[0x28]	7	1			T319	1		T318	1		T234	1
alert_ping_fail	alert[0x29]	12	1			T9	1		T69	1		T251	1
alert_ping_fail	alert[0x2a]	14	1			T336	2		T314	1		T21	1
alert_ping_fail	alert[0x2b]	10	1			T258	1		T107	2		T317	1
alert_ping_fail	alert[0x2c]	17	1			T226	1		T327	1		T337	1
alert_ping_fail	alert[0x2d]	10	1			T3	1		T313	1		T330	1
alert_ping_fail	alert[0x2e]	17	1			T258	1		T34	1		T319	1
alert_ping_fail	alert[0x2f]	14	1			T67	1		T251	1		T35	1
alert_ping_fail	alert[0x30]	9	1			T338	1		T337	1		T317	1
alert_ping_fail	alert[0x31]	9	1			T8	1		T258	1		T319	1
alert_ping_fail	alert[0x32]	10	1			T8	1		T251	1		T258	1
alert_ping_fail	alert[0x33]	16	1			T251	1		T258	1		T34	2
alert_ping_fail	alert[0x34]	5	1			T248	1		T315	1		T339	1
alert_ping_fail	alert[0x35]	12	1			T3	1		T248	1		T258	1
alert_ping_fail	alert[0x36]	10	1			T251	1		T323	1		T335	1
alert_ping_fail	alert[0x37]	8	1			T258	1		T313	1		T321	1
alert_ping_fail	alert[0x38]	10	1			T3	1		T323	1		T340	1
alert_ping_fail	alert[0x39]	7	1			T338	1		T234	1		T322	1
alert_ping_fail	alert[0x3a]	12	1			T248	1		T292	1		T34	1
alert_ping_fail	alert[0x3b]	4	1			T8	1		T69	1		T319	1
alert_ping_fail	alert[0x3c]	9	1			T251	2		T321	2		T339	1
alert_ping_fail	alert[0x3d]	8	1			T8	1		T251	1		T292	2
alert_ping_fail	alert[0x3e]	5	1			T234	1		T328	1		T341	1
alert_ping_fail	alert[0x3f]	8	1			T69	1		T258	1		T34	1
alert_ping_fail	alert[0x40]	5	1			T9	1		T248	2		T292	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	100229	1			T5	2		T19	2		T20	40
alert_integrity_fail	class_i[0x1]	116998	1			T19	67		T6	6879		T86	44
alert_integrity_fail	class_i[0x2]	69800	1			T6	24		T20	3		T16	4
alert_integrity_fail	class_i[0x3]	68171	1			T5	6		T20	2		T28	15
alert_ping_fail	class_i[0x0]	183	1			T3	2		T8	2		T9	1
alert_ping_fail	class_i[0x1]	137	1			T8	1		T7	4		T9	1
alert_ping_fail	class_i[0x2]	154	1			T8	9		T69	15		T248	19
alert_ping_fail	class_i[0x3]	176	1			T3	4		T8	3		T9	1