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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.66 99.99 98.74 100.00 100.00 100.00 99.38 99.52


Total test records in report: 832
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T774 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1560186942 Jul 21 05:58:39 PM PDT 24 Jul 21 05:59:16 PM PDT 24 2879396501 ps
T775 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.4266694983 Jul 21 05:58:53 PM PDT 24 Jul 21 05:59:01 PM PDT 24 306914158 ps
T154 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2501389375 Jul 21 05:58:46 PM PDT 24 Jul 21 06:03:57 PM PDT 24 8761183514 ps
T776 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.426822417 Jul 21 05:58:53 PM PDT 24 Jul 21 05:59:36 PM PDT 24 507109785 ps
T777 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3365227693 Jul 21 05:58:59 PM PDT 24 Jul 21 05:59:26 PM PDT 24 5493195474 ps
T778 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.95093767 Jul 21 05:58:41 PM PDT 24 Jul 21 06:01:31 PM PDT 24 4636242918 ps
T180 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.624916085 Jul 21 05:58:46 PM PDT 24 Jul 21 06:00:03 PM PDT 24 1064696917 ps
T779 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3301410068 Jul 21 05:58:50 PM PDT 24 Jul 21 05:58:56 PM PDT 24 110449699 ps
T170 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2370030391 Jul 21 05:58:56 PM PDT 24 Jul 21 05:59:00 PM PDT 24 114257317 ps
T780 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1659504444 Jul 21 05:58:39 PM PDT 24 Jul 21 05:58:48 PM PDT 24 76304161 ps
T139 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1631724517 Jul 21 05:58:37 PM PDT 24 Jul 21 06:04:05 PM PDT 24 26986069687 ps
T781 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.4217007278 Jul 21 05:58:58 PM PDT 24 Jul 21 05:59:12 PM PDT 24 694090129 ps
T145 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.661783304 Jul 21 05:58:43 PM PDT 24 Jul 21 06:07:16 PM PDT 24 7476110822 ps
T782 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3167799623 Jul 21 05:58:45 PM PDT 24 Jul 21 05:58:48 PM PDT 24 8153639 ps
T783 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2172388866 Jul 21 05:59:03 PM PDT 24 Jul 21 05:59:05 PM PDT 24 7680575 ps
T784 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3402104026 Jul 21 05:59:03 PM PDT 24 Jul 21 05:59:05 PM PDT 24 12833412 ps
T785 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1805662935 Jul 21 05:58:40 PM PDT 24 Jul 21 05:58:49 PM PDT 24 243591151 ps
T137 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3459128034 Jul 21 05:58:43 PM PDT 24 Jul 21 06:18:11 PM PDT 24 55463712185 ps
T786 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1553064229 Jul 21 05:58:52 PM PDT 24 Jul 21 05:58:58 PM PDT 24 51536252 ps
T787 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.651263373 Jul 21 05:58:39 PM PDT 24 Jul 21 05:58:52 PM PDT 24 568941859 ps
T138 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.888234178 Jul 21 05:58:35 PM PDT 24 Jul 21 06:03:40 PM PDT 24 3942884784 ps
T788 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.462344924 Jul 21 05:58:34 PM PDT 24 Jul 21 05:58:44 PM PDT 24 131755789 ps
T789 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3820059924 Jul 21 05:58:39 PM PDT 24 Jul 21 06:01:47 PM PDT 24 5941443942 ps
T790 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3691932774 Jul 21 05:58:47 PM PDT 24 Jul 21 05:58:53 PM PDT 24 119378345 ps
T155 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1164796478 Jul 21 05:58:59 PM PDT 24 Jul 21 06:09:28 PM PDT 24 19309235674 ps
T791 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.419578860 Jul 21 05:58:40 PM PDT 24 Jul 21 05:58:49 PM PDT 24 67543409 ps
T792 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.3910610618 Jul 21 05:58:47 PM PDT 24 Jul 21 05:59:03 PM PDT 24 94051065 ps
T793 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1241042442 Jul 21 05:58:48 PM PDT 24 Jul 21 05:58:52 PM PDT 24 64911594 ps
T794 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3183373746 Jul 21 05:58:49 PM PDT 24 Jul 21 05:59:02 PM PDT 24 684947067 ps
T148 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.553473172 Jul 21 05:58:59 PM PDT 24 Jul 21 06:17:44 PM PDT 24 59685164664 ps
T795 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3847857386 Jul 21 05:59:04 PM PDT 24 Jul 21 05:59:06 PM PDT 24 11564866 ps
T796 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.512389152 Jul 21 05:58:56 PM PDT 24 Jul 21 05:59:11 PM PDT 24 255216591 ps
T797 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1601796975 Jul 21 05:58:41 PM PDT 24 Jul 21 05:58:50 PM PDT 24 206629183 ps
T798 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3169209248 Jul 21 05:58:47 PM PDT 24 Jul 21 05:59:10 PM PDT 24 692382298 ps
T799 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1082500757 Jul 21 05:58:56 PM PDT 24 Jul 21 05:59:05 PM PDT 24 977865968 ps
T149 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2297072470 Jul 21 05:58:47 PM PDT 24 Jul 21 06:01:57 PM PDT 24 2723977203 ps
T800 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1683116481 Jul 21 05:58:46 PM PDT 24 Jul 21 05:58:57 PM PDT 24 224799879 ps
T801 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2859198062 Jul 21 05:59:03 PM PDT 24 Jul 21 05:59:05 PM PDT 24 11895263 ps
T802 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.906794749 Jul 21 05:58:53 PM PDT 24 Jul 21 05:59:38 PM PDT 24 13896728001 ps
T157 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1945482507 Jul 21 05:58:39 PM PDT 24 Jul 21 06:01:15 PM PDT 24 4211715549 ps
T803 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2352121561 Jul 21 05:58:58 PM PDT 24 Jul 21 05:59:16 PM PDT 24 1080406103 ps
T804 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1401900806 Jul 21 05:59:01 PM PDT 24 Jul 21 05:59:11 PM PDT 24 132381365 ps
T805 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.201076148 Jul 21 05:59:03 PM PDT 24 Jul 21 05:59:04 PM PDT 24 8630634 ps
T806 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3480448618 Jul 21 05:59:09 PM PDT 24 Jul 21 05:59:11 PM PDT 24 9278503 ps
T807 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2000985923 Jul 21 05:58:50 PM PDT 24 Jul 21 05:59:08 PM PDT 24 2209710612 ps
T808 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1107006905 Jul 21 05:58:49 PM PDT 24 Jul 21 05:58:51 PM PDT 24 8045433 ps
T809 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2401797678 Jul 21 05:58:39 PM PDT 24 Jul 21 05:59:09 PM PDT 24 338358152 ps
T810 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1410233194 Jul 21 05:59:11 PM PDT 24 Jul 21 05:59:13 PM PDT 24 12532226 ps
T811 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2585591038 Jul 21 05:58:49 PM PDT 24 Jul 21 05:58:52 PM PDT 24 36608042 ps
T812 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1612677912 Jul 21 05:58:43 PM PDT 24 Jul 21 05:58:57 PM PDT 24 472362507 ps
T167 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2596524539 Jul 21 05:58:40 PM PDT 24 Jul 21 05:58:48 PM PDT 24 213473750 ps
T813 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.986031597 Jul 21 05:58:31 PM PDT 24 Jul 21 05:58:38 PM PDT 24 83440817 ps
T150 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2234516649 Jul 21 05:58:47 PM PDT 24 Jul 21 06:03:50 PM PDT 24 3762559113 ps
T144 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1333449034 Jul 21 05:58:55 PM PDT 24 Jul 21 06:01:25 PM PDT 24 4452089317 ps
T159 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2542481290 Jul 21 05:58:53 PM PDT 24 Jul 21 06:08:22 PM PDT 24 10114784162 ps
T177 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.113497452 Jul 21 05:58:48 PM PDT 24 Jul 21 05:59:16 PM PDT 24 177593120 ps
T814 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2643042800 Jul 21 05:58:45 PM PDT 24 Jul 21 05:58:56 PM PDT 24 397898165 ps
T815 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.714225909 Jul 21 05:58:46 PM PDT 24 Jul 21 05:58:59 PM PDT 24 93313228 ps
T816 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1722284769 Jul 21 05:58:33 PM PDT 24 Jul 21 05:58:38 PM PDT 24 123657431 ps
T151 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2388602736 Jul 21 05:58:45 PM PDT 24 Jul 21 06:03:43 PM PDT 24 4430357042 ps
T817 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.519887929 Jul 21 05:58:48 PM PDT 24 Jul 21 05:58:50 PM PDT 24 28355403 ps
T818 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3511771844 Jul 21 05:58:57 PM PDT 24 Jul 21 05:59:04 PM PDT 24 123440210 ps
T819 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2374529629 Jul 21 05:58:50 PM PDT 24 Jul 21 05:58:56 PM PDT 24 143865115 ps
T820 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2773268080 Jul 21 05:58:38 PM PDT 24 Jul 21 05:59:00 PM PDT 24 988716555 ps
T821 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.909939706 Jul 21 05:58:53 PM PDT 24 Jul 21 05:59:00 PM PDT 24 67111018 ps
T822 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2524639293 Jul 21 05:58:47 PM PDT 24 Jul 21 05:58:59 PM PDT 24 62008980 ps
T823 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2519006363 Jul 21 05:58:34 PM PDT 24 Jul 21 05:58:36 PM PDT 24 12858683 ps
T143 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2015058356 Jul 21 05:58:57 PM PDT 24 Jul 21 06:05:20 PM PDT 24 5990448662 ps
T824 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2999883213 Jul 21 05:58:58 PM PDT 24 Jul 21 05:59:01 PM PDT 24 15301289 ps
T825 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.561106456 Jul 21 05:58:45 PM PDT 24 Jul 21 05:58:58 PM PDT 24 182909159 ps
T152 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1824658309 Jul 21 05:58:31 PM PDT 24 Jul 21 06:00:17 PM PDT 24 1666196555 ps
T156 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2162560637 Jul 21 05:58:50 PM PDT 24 Jul 21 06:08:34 PM PDT 24 15222290814 ps
T206 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1062821178 Jul 21 05:58:32 PM PDT 24 Jul 21 06:10:39 PM PDT 24 14004736275 ps
T826 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3101831611 Jul 21 05:58:39 PM PDT 24 Jul 21 05:58:47 PM PDT 24 24089722 ps
T827 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.768006872 Jul 21 05:58:53 PM PDT 24 Jul 21 05:58:58 PM PDT 24 28029904 ps
T828 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1870849538 Jul 21 05:58:38 PM PDT 24 Jul 21 05:58:49 PM PDT 24 111667568 ps
T829 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2967874813 Jul 21 05:59:04 PM PDT 24 Jul 21 05:59:06 PM PDT 24 6403557 ps
T142 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2770652510 Jul 21 05:58:46 PM PDT 24 Jul 21 06:03:40 PM PDT 24 9334030919 ps
T830 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.789416052 Jul 21 05:58:40 PM PDT 24 Jul 21 05:59:25 PM PDT 24 2329664361 ps
T158 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1059279517 Jul 21 05:58:37 PM PDT 24 Jul 21 06:03:44 PM PDT 24 4202048976 ps
T831 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3558004727 Jul 21 05:58:45 PM PDT 24 Jul 21 06:01:28 PM PDT 24 4427896542 ps
T832 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2605596764 Jul 21 05:58:48 PM PDT 24 Jul 21 05:59:30 PM PDT 24 2754384026 ps

Test location /workspace/coverage/default/30.alert_handler_stress_all.1306831912
Short name T6
Test name
Test status
Simulation time 78467157091 ps
CPU time 1368.43 seconds
Started Jul 21 06:09:40 PM PDT 24
Finished Jul 21 06:32:29 PM PDT 24
Peak memory 289984 kb
Host smart-f3f3efa7-e359-4473-a53e-92a01b346f10
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306831912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1306831912
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.860292655
Short name T16
Test name
Test status
Simulation time 344354117149 ps
CPU time 8976.18 seconds
Started Jul 21 06:09:40 PM PDT 24
Finished Jul 21 08:39:18 PM PDT 24
Peak memory 394984 kb
Host smart-8f10f3e2-73be-43b2-890f-99c92f6588e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860292655 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.860292655
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.2825807035
Short name T10
Test name
Test status
Simulation time 448209854 ps
CPU time 20.88 seconds
Started Jul 21 06:07:45 PM PDT 24
Finished Jul 21 06:08:06 PM PDT 24
Peak memory 275316 kb
Host smart-176fb8eb-7d27-4dac-8289-f3a20dc54435
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2825807035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.2825807035
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2791537380
Short name T160
Test name
Test status
Simulation time 1167467194 ps
CPU time 41.47 seconds
Started Jul 21 05:58:55 PM PDT 24
Finished Jul 21 05:59:38 PM PDT 24
Peak memory 247028 kb
Host smart-aab2928e-4153-42e6-9b9a-aef5b006b4f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2791537380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2791537380
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1022091024
Short name T125
Test name
Test status
Simulation time 11328191580 ps
CPU time 367.19 seconds
Started Jul 21 05:58:35 PM PDT 24
Finished Jul 21 06:04:43 PM PDT 24
Peak memory 265524 kb
Host smart-aa9b3903-5f25-4ffa-bc12-bf65f1a3ec09
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1022091024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1022091024
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.98106088
Short name T38
Test name
Test status
Simulation time 45680906892 ps
CPU time 2669.75 seconds
Started Jul 21 06:10:30 PM PDT 24
Finished Jul 21 06:55:00 PM PDT 24
Peak memory 289212 kb
Host smart-c2a607ea-5c4b-483e-a3a5-de92ea1f99f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98106088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.98106088
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.366951220
Short name T67
Test name
Test status
Simulation time 33029279895 ps
CPU time 2050.56 seconds
Started Jul 21 06:08:06 PM PDT 24
Finished Jul 21 06:42:17 PM PDT 24
Peak memory 281840 kb
Host smart-3a7f8df0-4f41-4043-b323-3b355e5ede7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366951220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.366951220
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.843063235
Short name T46
Test name
Test status
Simulation time 85638605396 ps
CPU time 5116.46 seconds
Started Jul 21 06:10:31 PM PDT 24
Finished Jul 21 07:35:48 PM PDT 24
Peak memory 338884 kb
Host smart-fe46801a-f03f-4825-8ca6-db71be7da3ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843063235 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.843063235
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.594623171
Short name T78
Test name
Test status
Simulation time 83093800111 ps
CPU time 1547.29 seconds
Started Jul 21 06:08:39 PM PDT 24
Finished Jul 21 06:34:26 PM PDT 24
Peak memory 289520 kb
Host smart-895a1fd4-2fa0-469b-b274-46c0522c7f11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594623171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.594623171
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.535443169
Short name T109
Test name
Test status
Simulation time 69268680327 ps
CPU time 2206.18 seconds
Started Jul 21 06:07:38 PM PDT 24
Finished Jul 21 06:44:24 PM PDT 24
Peak memory 289656 kb
Host smart-4eb1e846-a748-4dac-b536-cb34de03ecc8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535443169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_hand
ler_stress_all.535443169
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2060261849
Short name T124
Test name
Test status
Simulation time 44525136659 ps
CPU time 1129.55 seconds
Started Jul 21 05:58:33 PM PDT 24
Finished Jul 21 06:17:23 PM PDT 24
Peak memory 273396 kb
Host smart-aa69d8a0-01cc-440b-bbbf-e5f20e13262f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060261849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2060261849
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2860234074
Short name T51
Test name
Test status
Simulation time 34043326914 ps
CPU time 1989.77 seconds
Started Jul 21 06:08:44 PM PDT 24
Finished Jul 21 06:41:55 PM PDT 24
Peak memory 281824 kb
Host smart-8c9c4306-c62b-4fe7-93b5-3b1b115ba33d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860234074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2860234074
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3481393422
Short name T127
Test name
Test status
Simulation time 60627692458 ps
CPU time 316.87 seconds
Started Jul 21 05:58:59 PM PDT 24
Finished Jul 21 06:04:17 PM PDT 24
Peak memory 265592 kb
Host smart-f5564892-47f0-4245-b4ef-7879e59565b8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3481393422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3481393422
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.4257994851
Short name T501
Test name
Test status
Simulation time 35672385153 ps
CPU time 2098.62 seconds
Started Jul 21 06:10:45 PM PDT 24
Finished Jul 21 06:45:44 PM PDT 24
Peak memory 272984 kb
Host smart-6749c177-e4ca-4f7c-b6df-8cb27277b43d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257994851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.4257994851
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2831581121
Short name T101
Test name
Test status
Simulation time 112625769258 ps
CPU time 3532.19 seconds
Started Jul 21 06:07:35 PM PDT 24
Finished Jul 21 07:06:28 PM PDT 24
Peak memory 290024 kb
Host smart-1b2e06a9-2c4e-4270-83f4-1c07a8b5d168
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831581121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2831581121
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.891123702
Short name T21
Test name
Test status
Simulation time 5772698519 ps
CPU time 237.42 seconds
Started Jul 21 06:07:44 PM PDT 24
Finished Jul 21 06:11:42 PM PDT 24
Peak memory 255844 kb
Host smart-6b1eb791-4ba0-4f24-964e-e2bbe2b70e44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891123702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.891123702
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1293851279
Short name T7
Test name
Test status
Simulation time 60538785651 ps
CPU time 1647.59 seconds
Started Jul 21 06:11:33 PM PDT 24
Finished Jul 21 06:39:01 PM PDT 24
Peak memory 272980 kb
Host smart-3b3c5075-07af-4aa7-bc21-9418db908edc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293851279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1293851279
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2234516649
Short name T150
Test name
Test status
Simulation time 3762559113 ps
CPU time 302.49 seconds
Started Jul 21 05:58:47 PM PDT 24
Finished Jul 21 06:03:50 PM PDT 24
Peak memory 265548 kb
Host smart-f7bb0bd4-e986-4cf3-bb75-5f002a35bd7a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2234516649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.2234516649
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2401773243
Short name T23
Test name
Test status
Simulation time 241757670400 ps
CPU time 3210.9 seconds
Started Jul 21 06:09:17 PM PDT 24
Finished Jul 21 07:02:48 PM PDT 24
Peak memory 289308 kb
Host smart-26ee0e43-b19f-4c16-8680-f5579392dc2b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401773243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2401773243
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.546879458
Short name T364
Test name
Test status
Simulation time 10749339 ps
CPU time 1.6 seconds
Started Jul 21 05:59:05 PM PDT 24
Finished Jul 21 05:59:07 PM PDT 24
Peak memory 237772 kb
Host smart-917d5f8e-5906-40df-aa53-15ce5c459a21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=546879458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.546879458
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.440195518
Short name T258
Test name
Test status
Simulation time 16586438197 ps
CPU time 692.39 seconds
Started Jul 21 06:07:31 PM PDT 24
Finished Jul 21 06:19:04 PM PDT 24
Peak memory 249056 kb
Host smart-378330d2-bc71-472e-b905-90120aee3f36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440195518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.440195518
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3488729769
Short name T130
Test name
Test status
Simulation time 4311301557 ps
CPU time 670.49 seconds
Started Jul 21 05:58:55 PM PDT 24
Finished Jul 21 06:10:06 PM PDT 24
Peak memory 265648 kb
Host smart-8a1fa969-c047-410d-85ca-48ed776c1cad
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488729769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3488729769
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.464271150
Short name T342
Test name
Test status
Simulation time 33935139378 ps
CPU time 2150.36 seconds
Started Jul 21 06:07:29 PM PDT 24
Finished Jul 21 06:43:20 PM PDT 24
Peak memory 283292 kb
Host smart-16cd4fb2-93e0-4982-bde2-58128aa02468
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464271150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.464271150
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3861114955
Short name T135
Test name
Test status
Simulation time 15212139894 ps
CPU time 1209.3 seconds
Started Jul 21 05:58:55 PM PDT 24
Finished Jul 21 06:19:04 PM PDT 24
Peak memory 265796 kb
Host smart-e26152c9-ccf1-4f32-8ead-2a25b38f2610
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861114955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3861114955
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.87332609
Short name T248
Test name
Test status
Simulation time 9971044585 ps
CPU time 425.67 seconds
Started Jul 21 06:09:01 PM PDT 24
Finished Jul 21 06:16:07 PM PDT 24
Peak memory 249136 kb
Host smart-3bec21ab-b038-4cce-b325-a0188c55a4d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87332609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.87332609
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3459128034
Short name T137
Test name
Test status
Simulation time 55463712185 ps
CPU time 1166.39 seconds
Started Jul 21 05:58:43 PM PDT 24
Finished Jul 21 06:18:11 PM PDT 24
Peak memory 265812 kb
Host smart-e91fdd4a-3727-4560-ad76-566e61595aa0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459128034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3459128034
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.294471427
Short name T80
Test name
Test status
Simulation time 239693886441 ps
CPU time 4141.87 seconds
Started Jul 21 06:10:37 PM PDT 24
Finished Jul 21 07:19:40 PM PDT 24
Peak memory 316472 kb
Host smart-8b373462-6aa2-4925-82f8-402feb4988fd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=294471427 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.294471427
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.72041311
Short name T73
Test name
Test status
Simulation time 44645387788 ps
CPU time 2353.38 seconds
Started Jul 21 06:08:15 PM PDT 24
Finished Jul 21 06:47:29 PM PDT 24
Peak memory 285324 kb
Host smart-268712f6-d6eb-4a58-9d7e-74796f774e81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72041311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.72041311
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.3359999348
Short name T322
Test name
Test status
Simulation time 65524676994 ps
CPU time 573.56 seconds
Started Jul 21 06:10:29 PM PDT 24
Finished Jul 21 06:20:03 PM PDT 24
Peak memory 255684 kb
Host smart-319ab141-c731-460d-b702-4ae9d082aa9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359999348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3359999348
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3717193748
Short name T128
Test name
Test status
Simulation time 2052046023 ps
CPU time 224.37 seconds
Started Jul 21 05:58:48 PM PDT 24
Finished Jul 21 06:02:33 PM PDT 24
Peak memory 273028 kb
Host smart-aaa0c3e6-63a2-4d4d-8a43-ac0302516862
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3717193748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.3717193748
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.3271105958
Short name T50
Test name
Test status
Simulation time 55681709192 ps
CPU time 3398.01 seconds
Started Jul 21 06:08:37 PM PDT 24
Finished Jul 21 07:05:16 PM PDT 24
Peak memory 301104 kb
Host smart-19b3d894-1bb7-4070-b79f-3eceaeb15ff8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271105958 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.3271105958
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.996685632
Short name T325
Test name
Test status
Simulation time 53965817777 ps
CPU time 625.45 seconds
Started Jul 21 06:08:57 PM PDT 24
Finished Jul 21 06:19:23 PM PDT 24
Peak memory 248036 kb
Host smart-fe390c80-f35d-4f5b-ac9b-6723ce7a209d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996685632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.996685632
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.571869239
Short name T226
Test name
Test status
Simulation time 152391400735 ps
CPU time 2176.32 seconds
Started Jul 21 06:10:40 PM PDT 24
Finished Jul 21 06:46:57 PM PDT 24
Peak memory 289524 kb
Host smart-69f1c4ae-ec83-496b-ac2d-602f90a88673
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571869239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.571869239
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.4049379723
Short name T22
Test name
Test status
Simulation time 11876510635 ps
CPU time 832.7 seconds
Started Jul 21 06:10:58 PM PDT 24
Finished Jul 21 06:24:52 PM PDT 24
Peak memory 265492 kb
Host smart-2efb61b4-a432-47a7-ad91-5292c343c3d8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049379723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.4049379723
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.1164796478
Short name T155
Test name
Test status
Simulation time 19309235674 ps
CPU time 627.93 seconds
Started Jul 21 05:58:59 PM PDT 24
Finished Jul 21 06:09:28 PM PDT 24
Peak memory 265332 kb
Host smart-456380f8-79b1-4539-8afc-cf11e7254fad
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164796478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.1164796478
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.805504155
Short name T166
Test name
Test status
Simulation time 5169697502 ps
CPU time 90.9 seconds
Started Jul 21 05:58:38 PM PDT 24
Finished Jul 21 06:00:11 PM PDT 24
Peak memory 238892 kb
Host smart-1a57bd88-af64-44d3-acc5-a147f975c596
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=805504155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.805504155
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.852611368
Short name T273
Test name
Test status
Simulation time 41941617646 ps
CPU time 5021.87 seconds
Started Jul 21 06:08:21 PM PDT 24
Finished Jul 21 07:32:04 PM PDT 24
Peak memory 354880 kb
Host smart-6384c52f-dbd6-4808-92da-45f86bbee343
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852611368 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.852611368
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2566837038
Short name T352
Test name
Test status
Simulation time 63998885968 ps
CPU time 1304.96 seconds
Started Jul 21 06:07:33 PM PDT 24
Finished Jul 21 06:29:19 PM PDT 24
Peak memory 289716 kb
Host smart-c8490377-6bed-4564-88db-822b62778dec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566837038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2566837038
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2297072470
Short name T149
Test name
Test status
Simulation time 2723977203 ps
CPU time 189.45 seconds
Started Jul 21 05:58:47 PM PDT 24
Finished Jul 21 06:01:57 PM PDT 24
Peak memory 271888 kb
Host smart-ad865e14-1e66-4bbb-9ee7-c6a3394424e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2297072470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.2297072470
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.410689053
Short name T345
Test name
Test status
Simulation time 33253394469 ps
CPU time 2190.03 seconds
Started Jul 21 06:08:51 PM PDT 24
Finished Jul 21 06:45:22 PM PDT 24
Peak memory 290120 kb
Host smart-b82a2df1-0c7f-4b1a-85b6-d2269df83321
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410689053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.410689053
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.4198047978
Short name T306
Test name
Test status
Simulation time 62735113208 ps
CPU time 286.03 seconds
Started Jul 21 06:09:36 PM PDT 24
Finished Jul 21 06:14:23 PM PDT 24
Peak memory 249000 kb
Host smart-ed05ae75-5872-4f94-83e7-8c35205cdc66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198047978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.4198047978
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.550327126
Short name T8
Test name
Test status
Simulation time 9978043711 ps
CPU time 353 seconds
Started Jul 21 06:10:37 PM PDT 24
Finished Jul 21 06:16:30 PM PDT 24
Peak memory 249104 kb
Host smart-23325983-ea2d-430d-8f5b-b90e0ea4c609
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550327126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.550327126
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1428658555
Short name T270
Test name
Test status
Simulation time 94353520800 ps
CPU time 1626.51 seconds
Started Jul 21 06:11:33 PM PDT 24
Finished Jul 21 06:38:40 PM PDT 24
Peak memory 273696 kb
Host smart-5bc2ce28-8e15-4e41-b5e0-a210048e6cb9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428658555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1428658555
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2967563802
Short name T133
Test name
Test status
Simulation time 31470607503 ps
CPU time 1070.54 seconds
Started Jul 21 05:58:39 PM PDT 24
Finished Jul 21 06:16:33 PM PDT 24
Peak memory 265576 kb
Host smart-5489fe61-7786-46f2-b2e6-863916f76f9e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967563802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2967563802
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1075905626
Short name T232
Test name
Test status
Simulation time 24183741890 ps
CPU time 1358.22 seconds
Started Jul 21 06:07:30 PM PDT 24
Finished Jul 21 06:30:09 PM PDT 24
Peak memory 265480 kb
Host smart-74329217-08da-4783-bcf8-9c057f89f83c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075905626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1075905626
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1254100909
Short name T165
Test name
Test status
Simulation time 10172517 ps
CPU time 1.68 seconds
Started Jul 21 05:59:03 PM PDT 24
Finished Jul 21 05:59:05 PM PDT 24
Peak memory 236808 kb
Host smart-83e46936-6d79-4d6a-90c4-69050b06d625
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1254100909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1254100909
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.2661236977
Short name T344
Test name
Test status
Simulation time 84204958990 ps
CPU time 2327.37 seconds
Started Jul 21 06:08:30 PM PDT 24
Finished Jul 21 06:47:18 PM PDT 24
Peak memory 273028 kb
Host smart-7cd4bb80-f7a3-4d9d-8aab-11654dbd15be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2661236977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2661236977
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2955508745
Short name T302
Test name
Test status
Simulation time 26264512772 ps
CPU time 2132.53 seconds
Started Jul 21 06:08:26 PM PDT 24
Finished Jul 21 06:43:59 PM PDT 24
Peak memory 306216 kb
Host smart-48ebee74-3b9e-4e7a-ac94-e474ee4aca3b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955508745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2955508745
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.373964301
Short name T689
Test name
Test status
Simulation time 10064752018 ps
CPU time 399.69 seconds
Started Jul 21 06:09:47 PM PDT 24
Finished Jul 21 06:16:27 PM PDT 24
Peak memory 248024 kb
Host smart-018144ef-39e9-49ec-8212-49d8039dcbaf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373964301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.373964301
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2388602736
Short name T151
Test name
Test status
Simulation time 4430357042 ps
CPU time 297.92 seconds
Started Jul 21 05:58:45 PM PDT 24
Finished Jul 21 06:03:43 PM PDT 24
Peak memory 273024 kb
Host smart-927c2531-82b7-4b33-abe1-5b218fa56ad9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2388602736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.2388602736
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2935771436
Short name T216
Test name
Test status
Simulation time 110768542 ps
CPU time 3.3 seconds
Started Jul 21 06:07:27 PM PDT 24
Finished Jul 21 06:07:30 PM PDT 24
Peak memory 249176 kb
Host smart-161a3769-0493-4643-9811-740cee395b84
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2935771436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2935771436
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.3317654730
Short name T223
Test name
Test status
Simulation time 155409083 ps
CPU time 4.02 seconds
Started Jul 21 06:07:27 PM PDT 24
Finished Jul 21 06:07:31 PM PDT 24
Peak memory 249188 kb
Host smart-61ed6c8e-0838-453f-94be-881c14804065
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3317654730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3317654730
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.2262745471
Short name T221
Test name
Test status
Simulation time 34543242 ps
CPU time 3.44 seconds
Started Jul 21 06:08:14 PM PDT 24
Finished Jul 21 06:08:18 PM PDT 24
Peak memory 249208 kb
Host smart-fc019340-fc39-41bb-b0b6-7efff713a372
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2262745471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2262745471
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.4234421674
Short name T219
Test name
Test status
Simulation time 58631545 ps
CPU time 3.66 seconds
Started Jul 21 06:08:19 PM PDT 24
Finished Jul 21 06:08:23 PM PDT 24
Peak memory 249204 kb
Host smart-4f10923f-a5b0-4ef7-832d-fec1a6ac07c4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4234421674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.4234421674
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1046044483
Short name T107
Test name
Test status
Simulation time 11505939547 ps
CPU time 984.78 seconds
Started Jul 21 06:08:21 PM PDT 24
Finished Jul 21 06:24:46 PM PDT 24
Peak memory 273032 kb
Host smart-7c86fdf6-2abf-451f-9e23-12369bf30b5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046044483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1046044483
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1079919618
Short name T19
Test name
Test status
Simulation time 5201598612 ps
CPU time 47.18 seconds
Started Jul 21 06:08:14 PM PDT 24
Finished Jul 21 06:09:02 PM PDT 24
Peak memory 256060 kb
Host smart-44e623df-2763-4d94-b764-dbae31152cdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10799
19618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1079919618
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1762353802
Short name T285
Test name
Test status
Simulation time 183056406 ps
CPU time 22.48 seconds
Started Jul 21 06:08:52 PM PDT 24
Finished Jul 21 06:09:15 PM PDT 24
Peak memory 248920 kb
Host smart-dbdb9b9a-f835-4377-b5b8-25cc1f03fde0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17623
53802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1762353802
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.2966418133
Short name T239
Test name
Test status
Simulation time 130614842760 ps
CPU time 2350.69 seconds
Started Jul 21 06:09:22 PM PDT 24
Finished Jul 21 06:48:33 PM PDT 24
Peak memory 290120 kb
Host smart-28354389-0aa2-40d9-a3fc-d108329b5d02
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966418133 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.2966418133
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.571720251
Short name T104
Test name
Test status
Simulation time 11107924583 ps
CPU time 68.13 seconds
Started Jul 21 06:09:27 PM PDT 24
Finished Jul 21 06:10:36 PM PDT 24
Peak memory 256732 kb
Host smart-ee088023-c510-4d60-94f6-668d7cedece5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57172
0251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.571720251
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2713972877
Short name T190
Test name
Test status
Simulation time 17931079924 ps
CPU time 1660.52 seconds
Started Jul 21 06:09:34 PM PDT 24
Finished Jul 21 06:37:15 PM PDT 24
Peak memory 290016 kb
Host smart-82e0254f-5b6f-45ba-9d92-b2044a08c7ee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713972877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2713972877
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2958473901
Short name T276
Test name
Test status
Simulation time 651112997 ps
CPU time 47.56 seconds
Started Jul 21 06:10:45 PM PDT 24
Finished Jul 21 06:11:33 PM PDT 24
Peak memory 257200 kb
Host smart-32e26c12-9503-4e1b-a9eb-0f87cf4cb7d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29584
73901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2958473901
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3678645390
Short name T100
Test name
Test status
Simulation time 59314838382 ps
CPU time 2504.36 seconds
Started Jul 21 06:07:46 PM PDT 24
Finished Jul 21 06:49:31 PM PDT 24
Peak memory 289300 kb
Host smart-e19abf9f-278e-471c-bbbe-75480f3eb601
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678645390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3678645390
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.2710373172
Short name T286
Test name
Test status
Simulation time 37684106438 ps
CPU time 2067.58 seconds
Started Jul 21 06:08:03 PM PDT 24
Finished Jul 21 06:42:31 PM PDT 24
Peak memory 306332 kb
Host smart-5ab91b38-ab87-4df9-996b-dc9a0741a05d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710373172 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.2710373172
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2370030391
Short name T170
Test name
Test status
Simulation time 114257317 ps
CPU time 2.97 seconds
Started Jul 21 05:58:56 PM PDT 24
Finished Jul 21 05:59:00 PM PDT 24
Peak memory 238052 kb
Host smart-e3879ad5-1b84-4a6f-8b71-fa1c02c3df8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2370030391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2370030391
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.713395943
Short name T134
Test name
Test status
Simulation time 70348899404 ps
CPU time 903.09 seconds
Started Jul 21 05:58:38 PM PDT 24
Finished Jul 21 06:13:43 PM PDT 24
Peak memory 265540 kb
Host smart-4a4f7759-08bb-4f17-9b46-426ac0229225
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713395943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.713395943
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.550871065
Short name T24
Test name
Test status
Simulation time 134885771073 ps
CPU time 3796.95 seconds
Started Jul 21 06:09:23 PM PDT 24
Finished Jul 21 07:12:41 PM PDT 24
Peak memory 305896 kb
Host smart-e34cc399-4379-4143-a343-b5a92c33ec58
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550871065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.550871065
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.51465655
Short name T714
Test name
Test status
Simulation time 13972840 ps
CPU time 1.49 seconds
Started Jul 21 05:58:53 PM PDT 24
Finished Jul 21 05:58:55 PM PDT 24
Peak memory 236876 kb
Host smart-de149ef8-ba9b-4054-b232-8821db041eb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=51465655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.51465655
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.4015194043
Short name T351
Test name
Test status
Simulation time 48450910520 ps
CPU time 2384.38 seconds
Started Jul 21 06:07:30 PM PDT 24
Finished Jul 21 06:47:15 PM PDT 24
Peak memory 289708 kb
Host smart-18d40e95-6080-4ae1-b517-320cdc8eddd6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015194043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.4015194043
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.766330339
Short name T269
Test name
Test status
Simulation time 31495777337 ps
CPU time 3208.02 seconds
Started Jul 21 06:07:30 PM PDT 24
Finished Jul 21 07:00:58 PM PDT 24
Peak memory 321596 kb
Host smart-25b02738-9bc5-4112-823a-035ffd74a12b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766330339 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.766330339
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2728376963
Short name T36
Test name
Test status
Simulation time 23908972407 ps
CPU time 1557.67 seconds
Started Jul 21 06:08:24 PM PDT 24
Finished Jul 21 06:34:22 PM PDT 24
Peak memory 273532 kb
Host smart-f3223d1d-ff30-4831-b4ad-f7c7cd8da1d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728376963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2728376963
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.176115191
Short name T296
Test name
Test status
Simulation time 164830036414 ps
CPU time 2639.09 seconds
Started Jul 21 06:08:37 PM PDT 24
Finished Jul 21 06:52:37 PM PDT 24
Peak memory 285012 kb
Host smart-24b14753-0df4-48f0-8690-cacf91a4224f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176115191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.176115191
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.1585986687
Short name T274
Test name
Test status
Simulation time 22438941143 ps
CPU time 1540.07 seconds
Started Jul 21 06:08:48 PM PDT 24
Finished Jul 21 06:34:28 PM PDT 24
Peak memory 286904 kb
Host smart-d0815341-480e-42dd-ba4d-f1dc2a45b1ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585986687 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.1585986687
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3073170851
Short name T328
Test name
Test status
Simulation time 58701562354 ps
CPU time 397.13 seconds
Started Jul 21 06:07:31 PM PDT 24
Finished Jul 21 06:14:09 PM PDT 24
Peak memory 249148 kb
Host smart-e0898a38-5537-4118-b386-2d22357b93bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073170851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3073170851
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.2758644768
Short name T279
Test name
Test status
Simulation time 61859686843 ps
CPU time 5658.91 seconds
Started Jul 21 06:07:32 PM PDT 24
Finished Jul 21 07:41:52 PM PDT 24
Peak memory 322904 kb
Host smart-4081a906-68f1-4272-8f22-489875b4b807
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758644768 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.2758644768
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.3224415383
Short name T204
Test name
Test status
Simulation time 101455198024 ps
CPU time 2920.59 seconds
Started Jul 21 06:09:36 PM PDT 24
Finished Jul 21 06:58:17 PM PDT 24
Peak memory 290096 kb
Host smart-8e045d7b-0f2b-4c58-86fd-222b0713f4a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224415383 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.3224415383
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.3538383930
Short name T87
Test name
Test status
Simulation time 60319787638 ps
CPU time 3601.07 seconds
Started Jul 21 06:10:40 PM PDT 24
Finished Jul 21 07:10:42 PM PDT 24
Peak memory 299212 kb
Host smart-e0853f52-60c2-4239-b71f-c3f67820e696
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538383930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.3538383930
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3234780473
Short name T140
Test name
Test status
Simulation time 7264277403 ps
CPU time 161.45 seconds
Started Jul 21 05:58:53 PM PDT 24
Finished Jul 21 06:01:35 PM PDT 24
Peak memory 265592 kb
Host smart-353d5843-4c2b-4e5a-88ff-0eeaba90e7a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3234780473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3234780473
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3395169029
Short name T169
Test name
Test status
Simulation time 1801001790 ps
CPU time 75.18 seconds
Started Jul 21 05:58:56 PM PDT 24
Finished Jul 21 06:00:12 PM PDT 24
Peak memory 237472 kb
Host smart-1b33205f-6c0f-44d5-8ea8-1be747ded594
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3395169029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3395169029
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.1389138820
Short name T132
Test name
Test status
Simulation time 5026922653 ps
CPU time 353.2 seconds
Started Jul 21 05:59:00 PM PDT 24
Finished Jul 21 06:04:54 PM PDT 24
Peak memory 273336 kb
Host smart-0b444536-dd50-4773-a7cc-e20eb63bee0f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1389138820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.1389138820
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.161400967
Short name T161
Test name
Test status
Simulation time 898216498 ps
CPU time 69.78 seconds
Started Jul 21 05:58:32 PM PDT 24
Finished Jul 21 05:59:42 PM PDT 24
Peak memory 240676 kb
Host smart-450a2363-b2bb-4635-af57-efdef23ff02b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=161400967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.161400967
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.816407258
Short name T168
Test name
Test status
Simulation time 51904199 ps
CPU time 4.36 seconds
Started Jul 21 05:58:40 PM PDT 24
Finished Jul 21 05:58:48 PM PDT 24
Peak memory 238196 kb
Host smart-bd102b4a-0c69-4d82-aef8-4928763d8bf5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=816407258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.816407258
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.2162560637
Short name T156
Test name
Test status
Simulation time 15222290814 ps
CPU time 583.55 seconds
Started Jul 21 05:58:50 PM PDT 24
Finished Jul 21 06:08:34 PM PDT 24
Peak memory 269024 kb
Host smart-0fcde939-5f99-40d1-9fc7-136981e2ad5d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162560637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2162560637
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.113497452
Short name T177
Test name
Test status
Simulation time 177593120 ps
CPU time 27.77 seconds
Started Jul 21 05:58:48 PM PDT 24
Finished Jul 21 05:59:16 PM PDT 24
Peak memory 248912 kb
Host smart-f85bdabf-f523-4be4-8630-845b50d6bc55
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=113497452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.113497452
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1799519494
Short name T153
Test name
Test status
Simulation time 12829590601 ps
CPU time 527.22 seconds
Started Jul 21 05:58:48 PM PDT 24
Finished Jul 21 06:07:36 PM PDT 24
Peak memory 265800 kb
Host smart-13f0ee47-378b-4c00-b255-cbf1c36fd4bb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799519494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.1799519494
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1890241680
Short name T172
Test name
Test status
Simulation time 1201231689 ps
CPU time 35.35 seconds
Started Jul 21 05:58:53 PM PDT 24
Finished Jul 21 05:59:29 PM PDT 24
Peak memory 245932 kb
Host smart-48a01399-3bf5-4614-8828-7916f8b32a51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1890241680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1890241680
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1923878667
Short name T141
Test name
Test status
Simulation time 2801118675 ps
CPU time 182.27 seconds
Started Jul 21 05:58:55 PM PDT 24
Finished Jul 21 06:01:58 PM PDT 24
Peak memory 267192 kb
Host smart-ccb4ab45-3fcb-4a89-ad45-8ef54f03bdcf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1923878667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1923878667
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.2596524539
Short name T167
Test name
Test status
Simulation time 213473750 ps
CPU time 4.63 seconds
Started Jul 21 05:58:40 PM PDT 24
Finished Jul 21 05:58:48 PM PDT 24
Peak memory 237772 kb
Host smart-fcc48b25-8c22-4df4-8cd7-07b7b7e51a7c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2596524539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.2596524539
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.592487350
Short name T182
Test name
Test status
Simulation time 586732827 ps
CPU time 21.49 seconds
Started Jul 21 05:58:31 PM PDT 24
Finished Jul 21 05:58:54 PM PDT 24
Peak memory 240696 kb
Host smart-b2769b5a-c93b-4307-b625-2de2a5072a86
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=592487350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.592487350
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3908740943
Short name T176
Test name
Test status
Simulation time 1297262191 ps
CPU time 44.52 seconds
Started Jul 21 05:58:52 PM PDT 24
Finished Jul 21 05:59:38 PM PDT 24
Peak memory 240668 kb
Host smart-2d084ffc-077e-4e04-b51d-e45e0e260b69
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3908740943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3908740943
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2762226644
Short name T174
Test name
Test status
Simulation time 105159586 ps
CPU time 2.58 seconds
Started Jul 21 05:58:59 PM PDT 24
Finished Jul 21 05:59:03 PM PDT 24
Peak memory 236656 kb
Host smart-1854f744-e13b-4747-99fe-6ff5f368e930
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2762226644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2762226644
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.242720186
Short name T173
Test name
Test status
Simulation time 505335189 ps
CPU time 44.03 seconds
Started Jul 21 05:58:59 PM PDT 24
Finished Jul 21 05:59:44 PM PDT 24
Peak memory 240728 kb
Host smart-7189b403-14cf-41fe-bc8c-b6419c7be47c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=242720186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.242720186
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3143432377
Short name T171
Test name
Test status
Simulation time 7366286141 ps
CPU time 38.29 seconds
Started Jul 21 05:58:52 PM PDT 24
Finished Jul 21 05:59:32 PM PDT 24
Peak memory 237916 kb
Host smart-fe48a972-80a6-46e6-8088-60142be7dc07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3143432377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3143432377
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.418837549
Short name T181
Test name
Test status
Simulation time 1915955782 ps
CPU time 33.06 seconds
Started Jul 21 05:58:45 PM PDT 24
Finished Jul 21 05:59:19 PM PDT 24
Peak memory 240576 kb
Host smart-0a458433-ca21-4275-8041-898768ec2948
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=418837549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.418837549
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.624916085
Short name T180
Test name
Test status
Simulation time 1064696917 ps
CPU time 75.8 seconds
Started Jul 21 05:58:46 PM PDT 24
Finished Jul 21 06:00:03 PM PDT 24
Peak memory 240628 kb
Host smart-5c47a791-8c62-4dba-beb9-709540f38b22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=624916085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.624916085
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.693258042
Short name T25
Test name
Test status
Simulation time 6620703680 ps
CPU time 50.27 seconds
Started Jul 21 06:11:27 PM PDT 24
Finished Jul 21 06:12:18 PM PDT 24
Peak memory 249464 kb
Host smart-3975ef44-d244-4da3-9c15-1e84adfca9f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69325
8042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.693258042
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3457671805
Short name T765
Test name
Test status
Simulation time 3345874588 ps
CPU time 236.33 seconds
Started Jul 21 05:58:37 PM PDT 24
Finished Jul 21 06:02:36 PM PDT 24
Peak memory 240884 kb
Host smart-64720b75-f5be-492e-b36c-87de11f2605b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3457671805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3457671805
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1720757191
Short name T713
Test name
Test status
Simulation time 1674683979 ps
CPU time 202.56 seconds
Started Jul 21 05:58:32 PM PDT 24
Finished Jul 21 06:01:55 PM PDT 24
Peak memory 237712 kb
Host smart-2fae08a4-2c42-4bab-9a4c-0ccf41154eb4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1720757191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1720757191
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.986031597
Short name T813
Test name
Test status
Simulation time 83440817 ps
CPU time 5.64 seconds
Started Jul 21 05:58:31 PM PDT 24
Finished Jul 21 05:58:38 PM PDT 24
Peak memory 248964 kb
Host smart-321acbb8-746f-4db5-9f35-442fa143b5b8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=986031597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.986031597
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3651862647
Short name T753
Test name
Test status
Simulation time 97160987 ps
CPU time 7.75 seconds
Started Jul 21 05:58:38 PM PDT 24
Finished Jul 21 05:58:48 PM PDT 24
Peak memory 240792 kb
Host smart-e1b95602-33e1-4a11-9718-328acff0117e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651862647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.3651862647
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.928961802
Short name T739
Test name
Test status
Simulation time 222120091 ps
CPU time 5.12 seconds
Started Jul 21 05:58:34 PM PDT 24
Finished Jul 21 05:58:40 PM PDT 24
Peak memory 236868 kb
Host smart-2bc21db2-961e-4f49-bef3-74d3ca8ad11d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=928961802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.928961802
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3026969602
Short name T265
Test name
Test status
Simulation time 11364781 ps
CPU time 1.35 seconds
Started Jul 21 05:58:30 PM PDT 24
Finished Jul 21 05:58:33 PM PDT 24
Peak memory 237720 kb
Host smart-0c0f4a8d-b0b4-478f-9987-8c799bf83eec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3026969602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3026969602
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1707571873
Short name T771
Test name
Test status
Simulation time 163140113 ps
CPU time 24.18 seconds
Started Jul 21 05:58:35 PM PDT 24
Finished Jul 21 05:59:01 PM PDT 24
Peak memory 248924 kb
Host smart-8c884be1-2278-415b-999d-6682fd2e8e48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1707571873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1707571873
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1062821178
Short name T206
Test name
Test status
Simulation time 14004736275 ps
CPU time 725.92 seconds
Started Jul 21 05:58:32 PM PDT 24
Finished Jul 21 06:10:39 PM PDT 24
Peak memory 272288 kb
Host smart-09c15505-0bd7-4716-bf15-4ca166c58fd0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1062821178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1062821178
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2870568509
Short name T770
Test name
Test status
Simulation time 499133324 ps
CPU time 15.75 seconds
Started Jul 21 05:58:35 PM PDT 24
Finished Jul 21 05:58:51 PM PDT 24
Peak memory 248868 kb
Host smart-12778f8f-cf7d-4909-b860-a8affdc7a936
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2870568509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2870568509
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1526044705
Short name T197
Test name
Test status
Simulation time 1986267775 ps
CPU time 73.75 seconds
Started Jul 21 05:58:31 PM PDT 24
Finished Jul 21 05:59:46 PM PDT 24
Peak memory 237788 kb
Host smart-642f8331-69ed-4fd2-bada-9366f14fb5dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1526044705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1526044705
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2544527927
Short name T721
Test name
Test status
Simulation time 25905340615 ps
CPU time 392.57 seconds
Started Jul 21 05:58:35 PM PDT 24
Finished Jul 21 06:05:09 PM PDT 24
Peak memory 240768 kb
Host smart-daea1641-f921-445e-b15a-e4b98fcdffdb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2544527927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2544527927
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.462344924
Short name T788
Test name
Test status
Simulation time 131755789 ps
CPU time 9.72 seconds
Started Jul 21 05:58:34 PM PDT 24
Finished Jul 21 05:58:44 PM PDT 24
Peak memory 249244 kb
Host smart-a4bc9130-d37a-453c-8320-a7e68393e5ff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=462344924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.462344924
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2998824071
Short name T730
Test name
Test status
Simulation time 101486741 ps
CPU time 5.36 seconds
Started Jul 21 05:58:32 PM PDT 24
Finished Jul 21 05:58:38 PM PDT 24
Peak memory 239364 kb
Host smart-de1c814d-aca6-4dd2-9df3-27c2af5d8609
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998824071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.2998824071
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.4120231367
Short name T757
Test name
Test status
Simulation time 94040714 ps
CPU time 7.99 seconds
Started Jul 21 05:58:33 PM PDT 24
Finished Jul 21 05:58:41 PM PDT 24
Peak memory 237692 kb
Host smart-298d68ff-9afa-463f-8f94-95f1275fdad5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4120231367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.4120231367
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2519006363
Short name T823
Test name
Test status
Simulation time 12858683 ps
CPU time 1.44 seconds
Started Jul 21 05:58:34 PM PDT 24
Finished Jul 21 05:58:36 PM PDT 24
Peak memory 236816 kb
Host smart-8c38e7ec-59d0-4d60-b232-afe291e9dc3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2519006363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2519006363
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.740593786
Short name T193
Test name
Test status
Simulation time 727443851 ps
CPU time 43.19 seconds
Started Jul 21 05:58:36 PM PDT 24
Finished Jul 21 05:59:20 PM PDT 24
Peak memory 248924 kb
Host smart-e443a3df-8988-4cba-8dc9-96fcbaed8571
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=740593786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outs
tanding.740593786
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.888234178
Short name T138
Test name
Test status
Simulation time 3942884784 ps
CPU time 305.17 seconds
Started Jul 21 05:58:35 PM PDT 24
Finished Jul 21 06:03:40 PM PDT 24
Peak memory 265748 kb
Host smart-de24431a-46df-4425-8174-28eace9c4249
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=888234178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_error
s.888234178
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.3155417964
Short name T122
Test name
Test status
Simulation time 23954709120 ps
CPU time 505.05 seconds
Started Jul 21 05:58:35 PM PDT 24
Finished Jul 21 06:07:02 PM PDT 24
Peak memory 265600 kb
Host smart-00d8441a-93cd-4d41-9b32-1ad5534f10a9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155417964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.3155417964
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3517150776
Short name T729
Test name
Test status
Simulation time 34872252 ps
CPU time 6.17 seconds
Started Jul 21 05:58:33 PM PDT 24
Finished Jul 21 05:58:40 PM PDT 24
Peak memory 249984 kb
Host smart-19341cf6-4879-44a6-a962-26bd7147a318
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3517150776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3517150776
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.1241042442
Short name T793
Test name
Test status
Simulation time 64911594 ps
CPU time 3.7 seconds
Started Jul 21 05:58:48 PM PDT 24
Finished Jul 21 05:58:52 PM PDT 24
Peak memory 238540 kb
Host smart-c8e11ab8-75c5-42b5-84c5-36cdebc8b4f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241042442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.1241042442
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.38188536
Short name T760
Test name
Test status
Simulation time 112397193 ps
CPU time 4.65 seconds
Started Jul 21 05:58:45 PM PDT 24
Finished Jul 21 05:58:50 PM PDT 24
Peak memory 236836 kb
Host smart-11d685cd-02ed-40d0-8f3e-0c545e8b9a7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=38188536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.38188536
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.519887929
Short name T817
Test name
Test status
Simulation time 28355403 ps
CPU time 1.61 seconds
Started Jul 21 05:58:48 PM PDT 24
Finished Jul 21 05:58:50 PM PDT 24
Peak memory 236968 kb
Host smart-7c2ef6ca-50a6-4f57-ad1e-1b9722b41e2c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=519887929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.519887929
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3169209248
Short name T798
Test name
Test status
Simulation time 692382298 ps
CPU time 21.69 seconds
Started Jul 21 05:58:47 PM PDT 24
Finished Jul 21 05:59:10 PM PDT 24
Peak memory 245948 kb
Host smart-80d1a56b-e312-4646-8f74-122b07ffb9c1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3169209248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3169209248
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1683116481
Short name T800
Test name
Test status
Simulation time 224799879 ps
CPU time 9.65 seconds
Started Jul 21 05:58:46 PM PDT 24
Finished Jul 21 05:58:57 PM PDT 24
Peak memory 253372 kb
Host smart-204dc878-8bdd-46e9-a3f3-f77c18f71a80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1683116481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1683116481
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.773876168
Short name T162
Test name
Test status
Simulation time 310594091 ps
CPU time 48.55 seconds
Started Jul 21 05:58:52 PM PDT 24
Finished Jul 21 05:59:41 PM PDT 24
Peak memory 237812 kb
Host smart-dea2d0af-5dfa-45f6-8926-b42ed083e705
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=773876168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.773876168
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2524639293
Short name T822
Test name
Test status
Simulation time 62008980 ps
CPU time 10.69 seconds
Started Jul 21 05:58:47 PM PDT 24
Finished Jul 21 05:58:59 PM PDT 24
Peak memory 257080 kb
Host smart-2594c86a-5541-4769-8ac2-908f2a15a847
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524639293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2524639293
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1082500757
Short name T799
Test name
Test status
Simulation time 977865968 ps
CPU time 8.08 seconds
Started Jul 21 05:58:56 PM PDT 24
Finished Jul 21 05:59:05 PM PDT 24
Peak memory 240712 kb
Host smart-d6c5d448-abb8-4511-939b-2487851351ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1082500757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1082500757
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1107006905
Short name T808
Test name
Test status
Simulation time 8045433 ps
CPU time 1.31 seconds
Started Jul 21 05:58:49 PM PDT 24
Finished Jul 21 05:58:51 PM PDT 24
Peak memory 235780 kb
Host smart-5ca6b4cd-3c25-44ad-bc09-669a52aa3edd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1107006905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1107006905
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.714225909
Short name T815
Test name
Test status
Simulation time 93313228 ps
CPU time 11.33 seconds
Started Jul 21 05:58:46 PM PDT 24
Finished Jul 21 05:58:59 PM PDT 24
Peak memory 245028 kb
Host smart-4f43feb3-58a9-4f0e-957d-a72a8f0c68c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=714225909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_out
standing.714225909
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.672099832
Short name T123
Test name
Test status
Simulation time 4267635814 ps
CPU time 347.96 seconds
Started Jul 21 05:58:48 PM PDT 24
Finished Jul 21 06:04:37 PM PDT 24
Peak memory 265472 kb
Host smart-565dc205-f296-43ac-bc6a-9c3044219e71
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672099832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.672099832
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1430419504
Short name T727
Test name
Test status
Simulation time 320201614 ps
CPU time 9.78 seconds
Started Jul 21 05:58:48 PM PDT 24
Finished Jul 21 05:58:58 PM PDT 24
Peak memory 247920 kb
Host smart-7efe4c2b-5e51-48b1-bce0-8c1ba9ef6ba0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1430419504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1430419504
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3062730053
Short name T718
Test name
Test status
Simulation time 51512755 ps
CPU time 4.87 seconds
Started Jul 21 05:58:59 PM PDT 24
Finished Jul 21 05:59:05 PM PDT 24
Peak memory 240772 kb
Host smart-96ccc6d2-f598-4b79-8af4-ee39c3ad105e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062730053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3062730053
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.909939706
Short name T821
Test name
Test status
Simulation time 67111018 ps
CPU time 5.54 seconds
Started Jul 21 05:58:53 PM PDT 24
Finished Jul 21 05:59:00 PM PDT 24
Peak memory 240384 kb
Host smart-e6ccba38-ddc5-47cf-a0e6-fdb3b41089a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=909939706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.909939706
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3167799623
Short name T782
Test name
Test status
Simulation time 8153639 ps
CPU time 1.44 seconds
Started Jul 21 05:58:45 PM PDT 24
Finished Jul 21 05:58:48 PM PDT 24
Peak memory 237620 kb
Host smart-225083ae-b167-4435-a0bd-c7ab388fec22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3167799623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3167799623
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.426822417
Short name T776
Test name
Test status
Simulation time 507109785 ps
CPU time 42.22 seconds
Started Jul 21 05:58:53 PM PDT 24
Finished Jul 21 05:59:36 PM PDT 24
Peak memory 246008 kb
Host smart-61d46c98-d4dd-491f-b9f3-0c815de063fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=426822417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.426822417
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.561106456
Short name T825
Test name
Test status
Simulation time 182909159 ps
CPU time 11.72 seconds
Started Jul 21 05:58:45 PM PDT 24
Finished Jul 21 05:58:58 PM PDT 24
Peak memory 248972 kb
Host smart-1a9e1e1b-2b5e-4101-9e53-baab2e56572b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=561106456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.561106456
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2585591038
Short name T811
Test name
Test status
Simulation time 36608042 ps
CPU time 3 seconds
Started Jul 21 05:58:49 PM PDT 24
Finished Jul 21 05:58:52 PM PDT 24
Peak memory 237996 kb
Host smart-d4478c59-50f5-4ed5-9c52-30b0c21e55b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2585591038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2585591038
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.768006872
Short name T827
Test name
Test status
Simulation time 28029904 ps
CPU time 4.49 seconds
Started Jul 21 05:58:53 PM PDT 24
Finished Jul 21 05:58:58 PM PDT 24
Peak memory 254680 kb
Host smart-07686ec3-0bf5-4f7b-91bb-a565bcb8ebaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768006872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 13.alert_handler_csr_mem_rw_with_rand_reset.768006872
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2625968912
Short name T731
Test name
Test status
Simulation time 50138315 ps
CPU time 5.39 seconds
Started Jul 21 05:58:51 PM PDT 24
Finished Jul 21 05:58:57 PM PDT 24
Peak memory 237760 kb
Host smart-7e11b607-3cbc-4105-a361-c37ca5af77a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2625968912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2625968912
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.906794749
Short name T802
Test name
Test status
Simulation time 13896728001 ps
CPU time 44.86 seconds
Started Jul 21 05:58:53 PM PDT 24
Finished Jul 21 05:59:38 PM PDT 24
Peak memory 248964 kb
Host smart-9eb91ba3-1bf5-4be7-b456-dacbb1074de6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=906794749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_out
standing.906794749
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2017243859
Short name T131
Test name
Test status
Simulation time 9309655909 ps
CPU time 352.26 seconds
Started Jul 21 05:58:55 PM PDT 24
Finished Jul 21 06:04:48 PM PDT 24
Peak memory 272940 kb
Host smart-e76a185d-e2e7-45ae-bb9b-7400e60b6fa5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2017243859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2017243859
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3679023962
Short name T712
Test name
Test status
Simulation time 205772231 ps
CPU time 8.01 seconds
Started Jul 21 05:58:51 PM PDT 24
Finished Jul 21 05:58:59 PM PDT 24
Peak memory 254284 kb
Host smart-4d03f95a-cb3b-4f68-a624-b95ae5bed8a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3679023962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3679023962
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.4266694983
Short name T775
Test name
Test status
Simulation time 306914158 ps
CPU time 7.19 seconds
Started Jul 21 05:58:53 PM PDT 24
Finished Jul 21 05:59:01 PM PDT 24
Peak memory 240728 kb
Host smart-42401d37-a2eb-40a9-8ae7-9172ed35ef37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266694983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.4266694983
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1553064229
Short name T786
Test name
Test status
Simulation time 51536252 ps
CPU time 4.67 seconds
Started Jul 21 05:58:52 PM PDT 24
Finished Jul 21 05:58:58 PM PDT 24
Peak memory 236724 kb
Host smart-e694bacc-0886-4eb4-b05a-ef8694a12c77
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1553064229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1553064229
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2007526692
Short name T737
Test name
Test status
Simulation time 7576037 ps
CPU time 1.51 seconds
Started Jul 21 05:58:50 PM PDT 24
Finished Jul 21 05:58:52 PM PDT 24
Peak memory 237712 kb
Host smart-c24e5148-ee82-47ef-85a2-b81bca9499fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2007526692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2007526692
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3875602847
Short name T751
Test name
Test status
Simulation time 262299061 ps
CPU time 19.43 seconds
Started Jul 21 05:58:50 PM PDT 24
Finished Jul 21 05:59:10 PM PDT 24
Peak memory 245928 kb
Host smart-72859f0c-20f4-4a09-b3cb-2a54336a753a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3875602847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.3875602847
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1333449034
Short name T144
Test name
Test status
Simulation time 4452089317 ps
CPU time 149.51 seconds
Started Jul 21 05:58:55 PM PDT 24
Finished Jul 21 06:01:25 PM PDT 24
Peak memory 257508 kb
Host smart-3b94fb75-b4e3-4ddb-ad87-92ca33c7efac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1333449034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.1333449034
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2542481290
Short name T159
Test name
Test status
Simulation time 10114784162 ps
CPU time 567.51 seconds
Started Jul 21 05:58:53 PM PDT 24
Finished Jul 21 06:08:22 PM PDT 24
Peak memory 265676 kb
Host smart-f943cdc5-0a29-4f1e-893a-926998ca9a7d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542481290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.2542481290
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2941387958
Short name T724
Test name
Test status
Simulation time 758385720 ps
CPU time 26.61 seconds
Started Jul 21 05:58:51 PM PDT 24
Finished Jul 21 05:59:18 PM PDT 24
Peak memory 256800 kb
Host smart-399bf0bb-9b8f-4615-bb7a-cbe31981c022
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2941387958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2941387958
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.3572215586
Short name T746
Test name
Test status
Simulation time 421155491 ps
CPU time 9.1 seconds
Started Jul 21 05:58:55 PM PDT 24
Finished Jul 21 05:59:05 PM PDT 24
Peak memory 241360 kb
Host smart-98e3a48d-6280-4905-b415-a33a6be41a12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572215586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.3572215586
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.3212309163
Short name T756
Test name
Test status
Simulation time 438986111 ps
CPU time 4.49 seconds
Started Jul 21 05:58:52 PM PDT 24
Finished Jul 21 05:58:58 PM PDT 24
Peak memory 237740 kb
Host smart-802310e0-d2a2-4ce7-ad87-449e046c92df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3212309163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.3212309163
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2981436460
Short name T748
Test name
Test status
Simulation time 8523936 ps
CPU time 1.44 seconds
Started Jul 21 05:58:59 PM PDT 24
Finished Jul 21 05:59:02 PM PDT 24
Peak memory 237796 kb
Host smart-74bc7932-a2ba-471c-8e45-c94043fe3dc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2981436460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2981436460
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.4152557856
Short name T178
Test name
Test status
Simulation time 871606893 ps
CPU time 12.39 seconds
Started Jul 21 05:58:53 PM PDT 24
Finished Jul 21 05:59:06 PM PDT 24
Peak memory 245956 kb
Host smart-81c0dfb1-7eab-460b-b802-d5e3d9a904c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4152557856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.4152557856
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.2655124280
Short name T759
Test name
Test status
Simulation time 453536387 ps
CPU time 7.1 seconds
Started Jul 21 05:58:51 PM PDT 24
Finished Jul 21 05:58:58 PM PDT 24
Peak memory 252800 kb
Host smart-c009402c-fa90-4a4b-9843-fa5a2a69f688
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2655124280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.2655124280
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1401900806
Short name T804
Test name
Test status
Simulation time 132381365 ps
CPU time 9.6 seconds
Started Jul 21 05:59:01 PM PDT 24
Finished Jul 21 05:59:11 PM PDT 24
Peak memory 252828 kb
Host smart-431398ff-1a5b-461b-be5e-fcbd7f1542fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401900806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.1401900806
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.2622681003
Short name T194
Test name
Test status
Simulation time 52520293 ps
CPU time 5.29 seconds
Started Jul 21 05:58:52 PM PDT 24
Finished Jul 21 05:58:58 PM PDT 24
Peak memory 237764 kb
Host smart-752f7f12-4532-4f1d-90f2-46cd7fd9ad3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2622681003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.2622681003
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2888065782
Short name T164
Test name
Test status
Simulation time 9108967 ps
CPU time 1.3 seconds
Started Jul 21 05:58:52 PM PDT 24
Finished Jul 21 05:58:54 PM PDT 24
Peak memory 236812 kb
Host smart-badc05c0-2f3e-4c76-9af1-738c8c94f520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2888065782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2888065782
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.676806730
Short name T198
Test name
Test status
Simulation time 4101001420 ps
CPU time 37.35 seconds
Started Jul 21 05:58:57 PM PDT 24
Finished Jul 21 05:59:36 PM PDT 24
Peak memory 245032 kb
Host smart-ebff7ced-4d14-418e-a255-e5f522d24db5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=676806730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out
standing.676806730
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2584819533
Short name T767
Test name
Test status
Simulation time 792735797 ps
CPU time 12.3 seconds
Started Jul 21 05:58:54 PM PDT 24
Finished Jul 21 05:59:07 PM PDT 24
Peak memory 248968 kb
Host smart-cf30b07c-19ec-483a-93f1-d0d8fd5cd529
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2584819533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2584819533
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1274223428
Short name T709
Test name
Test status
Simulation time 63424867 ps
CPU time 5.8 seconds
Started Jul 21 05:58:58 PM PDT 24
Finished Jul 21 05:59:05 PM PDT 24
Peak memory 249068 kb
Host smart-9774b32a-e5cf-484a-843e-eb21e68cf3f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274223428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1274223428
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3959222614
Short name T719
Test name
Test status
Simulation time 183632226 ps
CPU time 7.74 seconds
Started Jul 21 05:58:58 PM PDT 24
Finished Jul 21 05:59:07 PM PDT 24
Peak memory 237764 kb
Host smart-1f133fa6-0357-4eed-bf32-575e5734be03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3959222614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3959222614
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.343549679
Short name T738
Test name
Test status
Simulation time 12634533 ps
CPU time 1.49 seconds
Started Jul 21 05:58:57 PM PDT 24
Finished Jul 21 05:58:59 PM PDT 24
Peak memory 237676 kb
Host smart-53836603-5e19-4bcc-9fc1-25f06adf4112
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=343549679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.343549679
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2797839969
Short name T761
Test name
Test status
Simulation time 603820110 ps
CPU time 36.06 seconds
Started Jul 21 05:58:57 PM PDT 24
Finished Jul 21 05:59:35 PM PDT 24
Peak memory 245024 kb
Host smart-4f45a6a6-a728-44eb-a194-97ed6d5d9aec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2797839969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2797839969
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.1517314817
Short name T146
Test name
Test status
Simulation time 8700291599 ps
CPU time 295.76 seconds
Started Jul 21 05:58:59 PM PDT 24
Finished Jul 21 06:03:56 PM PDT 24
Peak memory 265572 kb
Host smart-b4af1372-1dc2-4955-81c6-9484bd0f5396
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517314817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.1517314817
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2352121561
Short name T803
Test name
Test status
Simulation time 1080406103 ps
CPU time 16.77 seconds
Started Jul 21 05:58:58 PM PDT 24
Finished Jul 21 05:59:16 PM PDT 24
Peak memory 248928 kb
Host smart-d3cca2c7-f467-47f8-9798-d310ef62da25
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2352121561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2352121561
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3511771844
Short name T818
Test name
Test status
Simulation time 123440210 ps
CPU time 5.09 seconds
Started Jul 21 05:58:57 PM PDT 24
Finished Jul 21 05:59:04 PM PDT 24
Peak memory 241940 kb
Host smart-b4e4192c-981a-40ef-91c4-c993fd153dd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511771844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3511771844
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.98606688
Short name T728
Test name
Test status
Simulation time 199241123 ps
CPU time 4.89 seconds
Started Jul 21 05:59:01 PM PDT 24
Finished Jul 21 05:59:06 PM PDT 24
Peak memory 240580 kb
Host smart-c3eebe57-c102-48ef-8435-f6a8e798090c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=98606688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.98606688
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2223031991
Short name T359
Test name
Test status
Simulation time 12806151 ps
CPU time 1.72 seconds
Started Jul 21 05:58:56 PM PDT 24
Finished Jul 21 05:58:58 PM PDT 24
Peak memory 237740 kb
Host smart-414a699a-7b3b-47db-9033-e22cbe5931ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2223031991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2223031991
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1943464993
Short name T264
Test name
Test status
Simulation time 670414712 ps
CPU time 49.13 seconds
Started Jul 21 05:58:57 PM PDT 24
Finished Jul 21 05:59:47 PM PDT 24
Peak memory 245928 kb
Host smart-e1b9f873-b9b7-42c4-bb09-c024ff80fb47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1943464993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1943464993
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2015058356
Short name T143
Test name
Test status
Simulation time 5990448662 ps
CPU time 381.69 seconds
Started Jul 21 05:58:57 PM PDT 24
Finished Jul 21 06:05:20 PM PDT 24
Peak memory 265608 kb
Host smart-eea56229-9f73-4d04-a008-24876071f3c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2015058356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.2015058356
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.553473172
Short name T148
Test name
Test status
Simulation time 59685164664 ps
CPU time 1123.75 seconds
Started Jul 21 05:58:59 PM PDT 24
Finished Jul 21 06:17:44 PM PDT 24
Peak memory 265804 kb
Host smart-5abb4194-a0d4-4753-8995-ec8a1c82f5c1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553473172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.553473172
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.4217007278
Short name T781
Test name
Test status
Simulation time 694090129 ps
CPU time 12.76 seconds
Started Jul 21 05:58:58 PM PDT 24
Finished Jul 21 05:59:12 PM PDT 24
Peak memory 254984 kb
Host smart-19bcfbeb-7fad-4e3e-a1cb-2b771d3c30d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4217007278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.4217007278
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3028233800
Short name T768
Test name
Test status
Simulation time 75136649 ps
CPU time 6.59 seconds
Started Jul 21 05:58:56 PM PDT 24
Finished Jul 21 05:59:03 PM PDT 24
Peak memory 239760 kb
Host smart-388ba204-48aa-4fec-a0ea-667a2f625fc7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028233800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.3028233800
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.4230781612
Short name T263
Test name
Test status
Simulation time 60044735 ps
CPU time 5.38 seconds
Started Jul 21 05:58:56 PM PDT 24
Finished Jul 21 05:59:03 PM PDT 24
Peak memory 236796 kb
Host smart-3c29d68c-d731-4636-9d5c-7dd777581e75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4230781612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.4230781612
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2999883213
Short name T824
Test name
Test status
Simulation time 15301289 ps
CPU time 1.25 seconds
Started Jul 21 05:58:58 PM PDT 24
Finished Jul 21 05:59:01 PM PDT 24
Peak memory 237788 kb
Host smart-6792bb1e-f5a3-4115-b529-15e4f4f2c608
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2999883213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2999883213
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3365227693
Short name T777
Test name
Test status
Simulation time 5493195474 ps
CPU time 26.54 seconds
Started Jul 21 05:58:59 PM PDT 24
Finished Jul 21 05:59:26 PM PDT 24
Peak memory 245888 kb
Host smart-1b369283-582e-4611-b190-1b1eaef6392f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3365227693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3365227693
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2843231307
Short name T126
Test name
Test status
Simulation time 22598620699 ps
CPU time 469.56 seconds
Started Jul 21 05:58:58 PM PDT 24
Finished Jul 21 06:06:49 PM PDT 24
Peak memory 265576 kb
Host smart-0c775d7d-6657-4ab9-9472-1f725fe68577
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843231307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2843231307
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.512389152
Short name T796
Test name
Test status
Simulation time 255216591 ps
CPU time 13.79 seconds
Started Jul 21 05:58:56 PM PDT 24
Finished Jul 21 05:59:11 PM PDT 24
Peak memory 247724 kb
Host smart-d90a53c1-197c-4ec2-86ac-031e3ff9d9a4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=512389152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.512389152
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3357033729
Short name T179
Test name
Test status
Simulation time 12163895193 ps
CPU time 272.52 seconds
Started Jul 21 05:58:31 PM PDT 24
Finished Jul 21 06:03:04 PM PDT 24
Peak memory 240780 kb
Host smart-870f7e9f-c41d-40fb-bd65-c7e75ca380ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3357033729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3357033729
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3926743476
Short name T742
Test name
Test status
Simulation time 3271572361 ps
CPU time 110.33 seconds
Started Jul 21 05:58:31 PM PDT 24
Finished Jul 21 06:00:23 PM PDT 24
Peak memory 240760 kb
Host smart-88877c3c-f439-4a0a-9f4a-d27676abf4d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3926743476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3926743476
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.1870849538
Short name T828
Test name
Test status
Simulation time 111667568 ps
CPU time 9.52 seconds
Started Jul 21 05:58:38 PM PDT 24
Finished Jul 21 05:58:49 PM PDT 24
Peak memory 249264 kb
Host smart-a5582129-f3ec-4870-9823-9c1f353b92f2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1870849538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.1870849538
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2029512074
Short name T175
Test name
Test status
Simulation time 413961275 ps
CPU time 8.34 seconds
Started Jul 21 05:58:42 PM PDT 24
Finished Jul 21 05:58:53 PM PDT 24
Peak memory 241068 kb
Host smart-64282e7e-082d-454f-9913-bd8202d2cdff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029512074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2029512074
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1722284769
Short name T816
Test name
Test status
Simulation time 123657431 ps
CPU time 4.46 seconds
Started Jul 21 05:58:33 PM PDT 24
Finished Jul 21 05:58:38 PM PDT 24
Peak memory 236952 kb
Host smart-50a010ce-8eac-41dd-a12c-7fe0286d44ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1722284769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1722284769
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3042731108
Short name T745
Test name
Test status
Simulation time 11666325 ps
CPU time 1.59 seconds
Started Jul 21 05:58:33 PM PDT 24
Finished Jul 21 05:58:36 PM PDT 24
Peak memory 237788 kb
Host smart-200b03f4-9cf7-40f4-8221-7f9670fd9388
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3042731108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3042731108
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2401797678
Short name T809
Test name
Test status
Simulation time 338358152 ps
CPU time 27.31 seconds
Started Jul 21 05:58:39 PM PDT 24
Finished Jul 21 05:59:09 PM PDT 24
Peak memory 245988 kb
Host smart-f7af6d76-6b21-49ec-830a-0dd2d168bad0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2401797678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2401797678
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1824658309
Short name T152
Test name
Test status
Simulation time 1666196555 ps
CPU time 104.54 seconds
Started Jul 21 05:58:31 PM PDT 24
Finished Jul 21 06:00:17 PM PDT 24
Peak memory 257320 kb
Host smart-f76cb590-5517-4e89-84a5-decff77cbf3f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1824658309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1824658309
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2499019620
Short name T734
Test name
Test status
Simulation time 189197447 ps
CPU time 13.78 seconds
Started Jul 21 05:58:34 PM PDT 24
Finished Jul 21 05:58:48 PM PDT 24
Peak memory 254168 kb
Host smart-8f59ca1e-3580-4b6f-9cfa-e796b36eecd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2499019620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2499019620
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.366347215
Short name T362
Test name
Test status
Simulation time 9818157 ps
CPU time 1.4 seconds
Started Jul 21 05:59:01 PM PDT 24
Finished Jul 21 05:59:03 PM PDT 24
Peak memory 235820 kb
Host smart-bf3ccad4-f3c0-4976-9c49-6b06fd2c1b13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=366347215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.366347215
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.149380013
Short name T743
Test name
Test status
Simulation time 21223485 ps
CPU time 1.38 seconds
Started Jul 21 05:58:57 PM PDT 24
Finished Jul 21 05:59:00 PM PDT 24
Peak memory 237764 kb
Host smart-ba96875d-810c-4b66-8eb0-4e67f7c9b62e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=149380013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.149380013
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.104598025
Short name T763
Test name
Test status
Simulation time 12295217 ps
CPU time 1.37 seconds
Started Jul 21 05:58:55 PM PDT 24
Finished Jul 21 05:58:58 PM PDT 24
Peak memory 236836 kb
Host smart-8155571f-5155-4688-9010-6da47091db0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=104598025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.104598025
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.10432857
Short name T358
Test name
Test status
Simulation time 20045762 ps
CPU time 1.33 seconds
Started Jul 21 05:59:06 PM PDT 24
Finished Jul 21 05:59:08 PM PDT 24
Peak memory 237732 kb
Host smart-b6c85ace-3c30-4e5c-8eec-7438b17b4af3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=10432857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.10432857
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3125219552
Short name T762
Test name
Test status
Simulation time 9562765 ps
CPU time 1.52 seconds
Started Jul 21 05:59:11 PM PDT 24
Finished Jul 21 05:59:13 PM PDT 24
Peak memory 235816 kb
Host smart-f20132e0-a546-498a-993a-d06a52f4ebf1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3125219552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3125219552
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.201076148
Short name T805
Test name
Test status
Simulation time 8630634 ps
CPU time 1.46 seconds
Started Jul 21 05:59:03 PM PDT 24
Finished Jul 21 05:59:04 PM PDT 24
Peak memory 237712 kb
Host smart-2bafe55a-fb9c-40c3-a44d-b5263bd95f07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=201076148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.201076148
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.829489345
Short name T747
Test name
Test status
Simulation time 9191153 ps
CPU time 1.36 seconds
Started Jul 21 05:59:02 PM PDT 24
Finished Jul 21 05:59:04 PM PDT 24
Peak memory 236828 kb
Host smart-6372797c-2b3f-4b50-ac42-450de0e5612d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=829489345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.829489345
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1934053529
Short name T750
Test name
Test status
Simulation time 12268853 ps
CPU time 1.41 seconds
Started Jul 21 05:59:04 PM PDT 24
Finished Jul 21 05:59:06 PM PDT 24
Peak memory 237760 kb
Host smart-c6ad7228-0f3b-4ecb-927a-cd0e1579ebd2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1934053529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1934053529
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2859198062
Short name T801
Test name
Test status
Simulation time 11895263 ps
CPU time 1.49 seconds
Started Jul 21 05:59:03 PM PDT 24
Finished Jul 21 05:59:05 PM PDT 24
Peak memory 236896 kb
Host smart-773b0c62-4e8d-4090-91f0-14473d8faff4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2859198062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2859198062
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2106456873
Short name T365
Test name
Test status
Simulation time 12148986 ps
CPU time 1.4 seconds
Started Jul 21 05:59:11 PM PDT 24
Finished Jul 21 05:59:13 PM PDT 24
Peak memory 235772 kb
Host smart-b833ecd0-6f22-44f7-bc6d-cb4955bbb52a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2106456873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2106456873
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.95093767
Short name T778
Test name
Test status
Simulation time 4636242918 ps
CPU time 166.98 seconds
Started Jul 21 05:58:41 PM PDT 24
Finished Jul 21 06:01:31 PM PDT 24
Peak memory 237828 kb
Host smart-6d901ecb-fbb3-4258-a81f-f39926b7e1bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=95093767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.95093767
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3820059924
Short name T789
Test name
Test status
Simulation time 5941443942 ps
CPU time 184.77 seconds
Started Jul 21 05:58:39 PM PDT 24
Finished Jul 21 06:01:47 PM PDT 24
Peak memory 240760 kb
Host smart-18dd557b-00b3-4f00-bfc1-61def1be162a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3820059924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3820059924
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1805662935
Short name T785
Test name
Test status
Simulation time 243591151 ps
CPU time 5.32 seconds
Started Jul 21 05:58:40 PM PDT 24
Finished Jul 21 05:58:49 PM PDT 24
Peak memory 248924 kb
Host smart-79bfdf53-8e71-42fc-a2c5-c1cebcdba508
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1805662935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1805662935
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.334225960
Short name T744
Test name
Test status
Simulation time 31435864 ps
CPU time 5.4 seconds
Started Jul 21 05:58:38 PM PDT 24
Finished Jul 21 05:58:46 PM PDT 24
Peak memory 240756 kb
Host smart-35cf29f5-e8a4-4c58-ac8c-f820479a5cf8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334225960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.alert_handler_csr_mem_rw_with_rand_reset.334225960
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.651263373
Short name T787
Test name
Test status
Simulation time 568941859 ps
CPU time 9.39 seconds
Started Jul 21 05:58:39 PM PDT 24
Finished Jul 21 05:58:52 PM PDT 24
Peak memory 237744 kb
Host smart-9496dcfe-09b6-437e-b956-b2ef94e26447
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=651263373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.651263373
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.786315568
Short name T360
Test name
Test status
Simulation time 9194684 ps
CPU time 1.38 seconds
Started Jul 21 05:58:39 PM PDT 24
Finished Jul 21 05:58:44 PM PDT 24
Peak memory 237780 kb
Host smart-40d3c79e-0047-4bc5-8ad1-a7e72d9819b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=786315568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.786315568
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.895709463
Short name T715
Test name
Test status
Simulation time 174830564 ps
CPU time 24.55 seconds
Started Jul 21 05:58:43 PM PDT 24
Finished Jul 21 05:59:09 PM PDT 24
Peak memory 249048 kb
Host smart-f8692f52-4ee7-439d-80ff-8e587538c697
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=895709463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outs
tanding.895709463
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1059279517
Short name T158
Test name
Test status
Simulation time 4202048976 ps
CPU time 304.67 seconds
Started Jul 21 05:58:37 PM PDT 24
Finished Jul 21 06:03:44 PM PDT 24
Peak memory 265560 kb
Host smart-c5d86b7e-7dc9-4ab1-93c7-30f69d631f42
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1059279517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1059279517
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2463424182
Short name T711
Test name
Test status
Simulation time 278595352 ps
CPU time 6.09 seconds
Started Jul 21 05:58:40 PM PDT 24
Finished Jul 21 05:58:50 PM PDT 24
Peak memory 248972 kb
Host smart-fd7b2c30-4053-46e2-8d70-6029d6fa3555
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2463424182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2463424182
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2801185094
Short name T752
Test name
Test status
Simulation time 65480130 ps
CPU time 3.51 seconds
Started Jul 21 05:58:38 PM PDT 24
Finished Jul 21 05:58:44 PM PDT 24
Peak memory 238112 kb
Host smart-1fabbfcc-8af8-4da8-8c3d-d08339398d50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2801185094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2801185094
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3820817796
Short name T758
Test name
Test status
Simulation time 8986784 ps
CPU time 1.51 seconds
Started Jul 21 05:59:05 PM PDT 24
Finished Jul 21 05:59:07 PM PDT 24
Peak memory 237788 kb
Host smart-a3eff625-f9fe-4ee6-89b1-ea619743744d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3820817796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3820817796
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3313037194
Short name T361
Test name
Test status
Simulation time 11712606 ps
CPU time 1.71 seconds
Started Jul 21 05:59:03 PM PDT 24
Finished Jul 21 05:59:05 PM PDT 24
Peak memory 237776 kb
Host smart-50294042-0d60-41a9-9ef7-0ca3a38fc144
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3313037194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3313037194
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.2775336908
Short name T773
Test name
Test status
Simulation time 9671662 ps
CPU time 1.59 seconds
Started Jul 21 05:59:04 PM PDT 24
Finished Jul 21 05:59:06 PM PDT 24
Peak memory 236868 kb
Host smart-7f9ed845-d6ea-48da-b1e2-b94d5c47e9fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2775336908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.2775336908
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.861090355
Short name T764
Test name
Test status
Simulation time 14196429 ps
CPU time 1.42 seconds
Started Jul 21 05:59:04 PM PDT 24
Finished Jul 21 05:59:06 PM PDT 24
Peak memory 235868 kb
Host smart-b236303a-9871-4a6d-b8aa-b1a9577f5924
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=861090355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.861090355
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.114765186
Short name T755
Test name
Test status
Simulation time 19302004 ps
CPU time 1.95 seconds
Started Jul 21 05:59:04 PM PDT 24
Finished Jul 21 05:59:07 PM PDT 24
Peak memory 237720 kb
Host smart-6b0efe5c-009f-4277-b324-3c4ee1480e95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=114765186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.114765186
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3847857386
Short name T795
Test name
Test status
Simulation time 11564866 ps
CPU time 1.49 seconds
Started Jul 21 05:59:04 PM PDT 24
Finished Jul 21 05:59:06 PM PDT 24
Peak memory 236820 kb
Host smart-66774a68-dcc3-4e23-b226-581ffdaf4449
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3847857386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3847857386
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3104049391
Short name T732
Test name
Test status
Simulation time 27323387 ps
CPU time 1.56 seconds
Started Jul 21 05:59:05 PM PDT 24
Finished Jul 21 05:59:07 PM PDT 24
Peak memory 236868 kb
Host smart-6024c47e-b21c-4201-ae2d-c0bf64bde8f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3104049391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.3104049391
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3480448618
Short name T806
Test name
Test status
Simulation time 9278503 ps
CPU time 1.51 seconds
Started Jul 21 05:59:09 PM PDT 24
Finished Jul 21 05:59:11 PM PDT 24
Peak memory 237756 kb
Host smart-423faaa9-59bb-4d01-bbbd-3944f65fb9d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3480448618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3480448618
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.566096564
Short name T749
Test name
Test status
Simulation time 19335192 ps
CPU time 1.48 seconds
Started Jul 21 05:59:04 PM PDT 24
Finished Jul 21 05:59:06 PM PDT 24
Peak memory 237792 kb
Host smart-f0d8204d-3f7c-478e-8df4-c9d02b94791a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=566096564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.566096564
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3180729977
Short name T726
Test name
Test status
Simulation time 15808509 ps
CPU time 1.68 seconds
Started Jul 21 05:59:05 PM PDT 24
Finished Jul 21 05:59:07 PM PDT 24
Peak memory 235892 kb
Host smart-e3c21277-57d8-4d98-aefd-d3319b6e540b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3180729977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3180729977
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2842598796
Short name T196
Test name
Test status
Simulation time 9166425831 ps
CPU time 144.91 seconds
Started Jul 21 05:58:38 PM PDT 24
Finished Jul 21 06:01:05 PM PDT 24
Peak memory 237816 kb
Host smart-deb31fda-2516-4390-a95b-60940375ee0c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2842598796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2842598796
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.876014260
Short name T754
Test name
Test status
Simulation time 15252346686 ps
CPU time 267.27 seconds
Started Jul 21 05:58:38 PM PDT 24
Finished Jul 21 06:03:08 PM PDT 24
Peak memory 237860 kb
Host smart-a179538f-d198-4314-9b94-a6026d4b5389
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=876014260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.876014260
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3101831611
Short name T826
Test name
Test status
Simulation time 24089722 ps
CPU time 3.82 seconds
Started Jul 21 05:58:39 PM PDT 24
Finished Jul 21 05:58:47 PM PDT 24
Peak memory 248888 kb
Host smart-67eb09db-69ef-449a-8002-7dbea604f2b5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3101831611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3101831611
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3717914523
Short name T262
Test name
Test status
Simulation time 476469204 ps
CPU time 9.47 seconds
Started Jul 21 05:58:38 PM PDT 24
Finished Jul 21 05:58:50 PM PDT 24
Peak memory 240816 kb
Host smart-5cf38819-10df-41ea-86c9-241c3cb661b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3717914523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3717914523
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.3920994907
Short name T733
Test name
Test status
Simulation time 96846797 ps
CPU time 8.06 seconds
Started Jul 21 05:58:39 PM PDT 24
Finished Jul 21 05:58:51 PM PDT 24
Peak memory 237772 kb
Host smart-45c5685c-e37d-45bd-b1af-7c122329f703
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3920994907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3920994907
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3853452413
Short name T723
Test name
Test status
Simulation time 10602427 ps
CPU time 1.37 seconds
Started Jul 21 05:58:39 PM PDT 24
Finished Jul 21 05:58:44 PM PDT 24
Peak memory 236856 kb
Host smart-8077075d-545e-4547-95dc-a7c869b0ce7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3853452413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.3853452413
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.789416052
Short name T830
Test name
Test status
Simulation time 2329664361 ps
CPU time 41.56 seconds
Started Jul 21 05:58:40 PM PDT 24
Finished Jul 21 05:59:25 PM PDT 24
Peak memory 245080 kb
Host smart-a452ab75-ac82-4579-9aa3-dce262071351
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=789416052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outs
tanding.789416052
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1631724517
Short name T139
Test name
Test status
Simulation time 26986069687 ps
CPU time 327.34 seconds
Started Jul 21 05:58:37 PM PDT 24
Finished Jul 21 06:04:05 PM PDT 24
Peak memory 265608 kb
Host smart-c4497162-61a5-4efb-a991-cce9c7bb4b22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1631724517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1631724517
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.661783304
Short name T145
Test name
Test status
Simulation time 7476110822 ps
CPU time 511.61 seconds
Started Jul 21 05:58:43 PM PDT 24
Finished Jul 21 06:07:16 PM PDT 24
Peak memory 265576 kb
Host smart-a436033c-5911-4ad8-8241-764026b2ef45
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661783304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.661783304
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.4048451509
Short name T741
Test name
Test status
Simulation time 254791262 ps
CPU time 14.3 seconds
Started Jul 21 05:58:40 PM PDT 24
Finished Jul 21 05:58:58 PM PDT 24
Peak memory 247724 kb
Host smart-5e7ec7a0-c31a-464f-9d37-dc8400160385
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4048451509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.4048451509
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.881233771
Short name T205
Test name
Test status
Simulation time 48436992 ps
CPU time 3.15 seconds
Started Jul 21 05:58:36 PM PDT 24
Finished Jul 21 05:58:40 PM PDT 24
Peak memory 237752 kb
Host smart-8b89379a-33c2-47fc-9932-fc4084dc808c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=881233771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.881233771
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3968750407
Short name T363
Test name
Test status
Simulation time 16897304 ps
CPU time 1.37 seconds
Started Jul 21 05:59:04 PM PDT 24
Finished Jul 21 05:59:05 PM PDT 24
Peak memory 236836 kb
Host smart-53211d83-ea78-4c1d-bf69-38e3b16b1348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3968750407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3968750407
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1702956443
Short name T735
Test name
Test status
Simulation time 8372644 ps
CPU time 1.52 seconds
Started Jul 21 05:59:05 PM PDT 24
Finished Jul 21 05:59:07 PM PDT 24
Peak memory 236788 kb
Host smart-247d76bd-a0f8-46de-84b1-581ff1e4f715
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1702956443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1702956443
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2261603980
Short name T722
Test name
Test status
Simulation time 25277058 ps
CPU time 1.56 seconds
Started Jul 21 05:59:03 PM PDT 24
Finished Jul 21 05:59:05 PM PDT 24
Peak memory 236760 kb
Host smart-b4279cf3-cd4a-4900-913a-182bdc9e04ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2261603980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2261603980
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2630716620
Short name T163
Test name
Test status
Simulation time 8933823 ps
CPU time 1.52 seconds
Started Jul 21 05:59:04 PM PDT 24
Finished Jul 21 05:59:07 PM PDT 24
Peak memory 236836 kb
Host smart-ce94ec0c-8b69-4d98-b6d0-6c87a27d2d74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2630716620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2630716620
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3402104026
Short name T784
Test name
Test status
Simulation time 12833412 ps
CPU time 1.45 seconds
Started Jul 21 05:59:03 PM PDT 24
Finished Jul 21 05:59:05 PM PDT 24
Peak memory 237780 kb
Host smart-e632dd16-971f-4d3d-8bc2-a29e633c0f76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3402104026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3402104026
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2967874813
Short name T829
Test name
Test status
Simulation time 6403557 ps
CPU time 1.41 seconds
Started Jul 21 05:59:04 PM PDT 24
Finished Jul 21 05:59:06 PM PDT 24
Peak memory 236848 kb
Host smart-69a8d285-3681-43a0-a325-f8eb4802561a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2967874813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2967874813
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2172388866
Short name T783
Test name
Test status
Simulation time 7680575 ps
CPU time 1.36 seconds
Started Jul 21 05:59:03 PM PDT 24
Finished Jul 21 05:59:05 PM PDT 24
Peak memory 237780 kb
Host smart-18212b1e-4978-457c-8578-0df94df705ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2172388866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2172388866
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1410233194
Short name T810
Test name
Test status
Simulation time 12532226 ps
CPU time 1.48 seconds
Started Jul 21 05:59:11 PM PDT 24
Finished Jul 21 05:59:13 PM PDT 24
Peak memory 237780 kb
Host smart-58b4b3c1-c669-4545-9d3d-60b9d611e24b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1410233194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1410233194
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1659504444
Short name T780
Test name
Test status
Simulation time 76304161 ps
CPU time 5.82 seconds
Started Jul 21 05:58:39 PM PDT 24
Finished Jul 21 05:58:48 PM PDT 24
Peak memory 240776 kb
Host smart-ffa7a8ba-d3b5-47f1-bc3a-5a95976ec6bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659504444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.1659504444
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.302081309
Short name T717
Test name
Test status
Simulation time 478397790 ps
CPU time 5.61 seconds
Started Jul 21 05:58:39 PM PDT 24
Finished Jul 21 05:58:47 PM PDT 24
Peak memory 237760 kb
Host smart-4a21c7ce-12d9-4c4a-90de-45c8bf6d0450
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=302081309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.302081309
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1580655901
Short name T725
Test name
Test status
Simulation time 12239992 ps
CPU time 1.81 seconds
Started Jul 21 05:58:38 PM PDT 24
Finished Jul 21 05:58:42 PM PDT 24
Peak memory 236812 kb
Host smart-b3851c63-f952-4a7b-a10a-a22565a5dfa8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1580655901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1580655901
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2773268080
Short name T820
Test name
Test status
Simulation time 988716555 ps
CPU time 19.18 seconds
Started Jul 21 05:58:38 PM PDT 24
Finished Jul 21 05:59:00 PM PDT 24
Peak memory 245912 kb
Host smart-554dd704-87f9-45f6-a0d9-c9d0924ec18f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2773268080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.2773268080
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1945482507
Short name T157
Test name
Test status
Simulation time 4211715549 ps
CPU time 152.71 seconds
Started Jul 21 05:58:39 PM PDT 24
Finished Jul 21 06:01:15 PM PDT 24
Peak memory 266156 kb
Host smart-bc689883-c6c8-4a05-83a2-edde6bfd374b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1945482507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1945482507
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1312771822
Short name T720
Test name
Test status
Simulation time 992577471 ps
CPU time 16.4 seconds
Started Jul 21 05:58:39 PM PDT 24
Finished Jul 21 05:58:58 PM PDT 24
Peak memory 248948 kb
Host smart-0e867dde-b520-46cf-8247-ad0a93f7904c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1312771822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1312771822
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1601796975
Short name T797
Test name
Test status
Simulation time 206629183 ps
CPU time 6.13 seconds
Started Jul 21 05:58:41 PM PDT 24
Finished Jul 21 05:58:50 PM PDT 24
Peak memory 257152 kb
Host smart-37186e32-1723-454e-b38d-fae1bc7df9e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601796975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1601796975
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.419578860
Short name T791
Test name
Test status
Simulation time 67543409 ps
CPU time 5.59 seconds
Started Jul 21 05:58:40 PM PDT 24
Finished Jul 21 05:58:49 PM PDT 24
Peak memory 237764 kb
Host smart-841cba22-6b2a-4902-af25-76963702b118
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=419578860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.419578860
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2282585656
Short name T736
Test name
Test status
Simulation time 14764852 ps
CPU time 1.75 seconds
Started Jul 21 05:58:38 PM PDT 24
Finished Jul 21 05:58:43 PM PDT 24
Peak memory 237784 kb
Host smart-df84ad32-7b0f-49d8-aff8-759dae298ce3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2282585656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2282585656
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1560186942
Short name T774
Test name
Test status
Simulation time 2879396501 ps
CPU time 34.57 seconds
Started Jul 21 05:58:39 PM PDT 24
Finished Jul 21 05:59:16 PM PDT 24
Peak memory 245084 kb
Host smart-4fdcf85a-ecf8-4764-9b3e-db3ff1977d85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1560186942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1560186942
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.4073730822
Short name T129
Test name
Test status
Simulation time 11140532218 ps
CPU time 158.06 seconds
Started Jul 21 05:58:40 PM PDT 24
Finished Jul 21 06:01:21 PM PDT 24
Peak memory 265624 kb
Host smart-c78374e0-0bee-4882-94a5-ff6555686e71
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4073730822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.4073730822
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.1612677912
Short name T812
Test name
Test status
Simulation time 472362507 ps
CPU time 12.66 seconds
Started Jul 21 05:58:43 PM PDT 24
Finished Jul 21 05:58:57 PM PDT 24
Peak memory 248968 kb
Host smart-d70a5662-2e10-4d90-9d5e-35c8931ae46c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1612677912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1612677912
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.107479627
Short name T740
Test name
Test status
Simulation time 82209863 ps
CPU time 5.8 seconds
Started Jul 21 05:58:52 PM PDT 24
Finished Jul 21 05:58:59 PM PDT 24
Peak memory 238824 kb
Host smart-84cac0bb-d59f-478f-9740-411bb63d24c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107479627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.107479627
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3301410068
Short name T779
Test name
Test status
Simulation time 110449699 ps
CPU time 5.73 seconds
Started Jul 21 05:58:50 PM PDT 24
Finished Jul 21 05:58:56 PM PDT 24
Peak memory 237828 kb
Host smart-eafe53e3-21f5-42ed-bcfb-1f296c35e4c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3301410068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3301410068
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3779692807
Short name T769
Test name
Test status
Simulation time 11183260 ps
CPU time 1.35 seconds
Started Jul 21 05:58:46 PM PDT 24
Finished Jul 21 05:58:48 PM PDT 24
Peak memory 236780 kb
Host smart-041d3dbf-e25f-41a8-93da-b5a243dbca88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3779692807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3779692807
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3183373746
Short name T794
Test name
Test status
Simulation time 684947067 ps
CPU time 12.97 seconds
Started Jul 21 05:58:49 PM PDT 24
Finished Jul 21 05:59:02 PM PDT 24
Peak memory 240732 kb
Host smart-42d56a6f-de1d-4d34-b8a9-3d7bf79aa683
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3183373746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3183373746
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2770652510
Short name T142
Test name
Test status
Simulation time 9334030919 ps
CPU time 293.24 seconds
Started Jul 21 05:58:46 PM PDT 24
Finished Jul 21 06:03:40 PM PDT 24
Peak memory 271316 kb
Host smart-a24734be-3aec-44fe-9d41-9bc13ea88af4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2770652510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.2770652510
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2826474001
Short name T147
Test name
Test status
Simulation time 2259907244 ps
CPU time 302.34 seconds
Started Jul 21 05:58:56 PM PDT 24
Finished Jul 21 06:04:00 PM PDT 24
Peak memory 270520 kb
Host smart-625f762c-2e90-400c-a926-518f638f1a1d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826474001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.2826474001
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2000985923
Short name T807
Test name
Test status
Simulation time 2209710612 ps
CPU time 17.77 seconds
Started Jul 21 05:58:50 PM PDT 24
Finished Jul 21 05:59:08 PM PDT 24
Peak memory 256744 kb
Host smart-39583c59-a247-46f3-94e8-a5392495e6e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2000985923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2000985923
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2643042800
Short name T814
Test name
Test status
Simulation time 397898165 ps
CPU time 9.62 seconds
Started Jul 21 05:58:45 PM PDT 24
Finished Jul 21 05:58:56 PM PDT 24
Peak memory 240356 kb
Host smart-bbcec343-ba99-4ace-b483-d85bba29b4fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643042800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.2643042800
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2925470736
Short name T195
Test name
Test status
Simulation time 50254564 ps
CPU time 4.77 seconds
Started Jul 21 05:58:46 PM PDT 24
Finished Jul 21 05:58:52 PM PDT 24
Peak memory 240640 kb
Host smart-b9b6e864-0c4d-4135-b61b-df7744e52f55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2925470736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2925470736
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.43168818
Short name T766
Test name
Test status
Simulation time 10657368 ps
CPU time 1.6 seconds
Started Jul 21 05:58:45 PM PDT 24
Finished Jul 21 05:58:47 PM PDT 24
Peak memory 237768 kb
Host smart-9b418896-0e85-4ef0-933f-7e8631d588de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=43168818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.43168818
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.3910610618
Short name T792
Test name
Test status
Simulation time 94051065 ps
CPU time 15.9 seconds
Started Jul 21 05:58:47 PM PDT 24
Finished Jul 21 05:59:03 PM PDT 24
Peak memory 248848 kb
Host smart-1995ed09-2180-4f08-a399-4a617054ffd9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3910610618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.3910610618
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3558004727
Short name T831
Test name
Test status
Simulation time 4427896542 ps
CPU time 161.62 seconds
Started Jul 21 05:58:45 PM PDT 24
Finished Jul 21 06:01:28 PM PDT 24
Peak memory 265616 kb
Host smart-02d74c1f-438a-4ceb-aa30-5ab90dee4c60
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3558004727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3558004727
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.139802827
Short name T136
Test name
Test status
Simulation time 17866759829 ps
CPU time 1140.65 seconds
Started Jul 21 05:58:49 PM PDT 24
Finished Jul 21 06:17:50 PM PDT 24
Peak memory 265516 kb
Host smart-ecb938be-a3c5-4980-a015-1c87b88ce9c4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139802827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.139802827
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3900641101
Short name T716
Test name
Test status
Simulation time 322859525 ps
CPU time 10.25 seconds
Started Jul 21 05:58:50 PM PDT 24
Finished Jul 21 05:59:01 PM PDT 24
Peak memory 256792 kb
Host smart-e061ba7f-b6ae-4cfc-b6df-f19b4b163259
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3900641101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3900641101
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3691932774
Short name T790
Test name
Test status
Simulation time 119378345 ps
CPU time 5.5 seconds
Started Jul 21 05:58:47 PM PDT 24
Finished Jul 21 05:58:53 PM PDT 24
Peak memory 257084 kb
Host smart-7bbe3bae-1040-4fb2-bf74-7d5b6dd55020
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691932774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3691932774
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2374529629
Short name T819
Test name
Test status
Simulation time 143865115 ps
CPU time 5.97 seconds
Started Jul 21 05:58:50 PM PDT 24
Finished Jul 21 05:58:56 PM PDT 24
Peak memory 237744 kb
Host smart-43c5707d-9870-4509-9d25-0e180575b77d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2374529629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2374529629
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.1561495180
Short name T772
Test name
Test status
Simulation time 21867532 ps
CPU time 1.36 seconds
Started Jul 21 05:58:49 PM PDT 24
Finished Jul 21 05:58:51 PM PDT 24
Peak memory 235792 kb
Host smart-88c43ebd-3883-46e7-9f2e-e421c61e6f27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1561495180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1561495180
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2605596764
Short name T832
Test name
Test status
Simulation time 2754384026 ps
CPU time 40.6 seconds
Started Jul 21 05:58:48 PM PDT 24
Finished Jul 21 05:59:30 PM PDT 24
Peak memory 246044 kb
Host smart-20f8096e-4396-4b1d-b72b-1df1a357fd22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2605596764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.2605596764
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2501389375
Short name T154
Test name
Test status
Simulation time 8761183514 ps
CPU time 310.18 seconds
Started Jul 21 05:58:46 PM PDT 24
Finished Jul 21 06:03:57 PM PDT 24
Peak memory 269504 kb
Host smart-9315a5e5-e084-4f8b-ba88-438325b7da9d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501389375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2501389375
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3015676795
Short name T710
Test name
Test status
Simulation time 109517440 ps
CPU time 4.25 seconds
Started Jul 21 05:58:45 PM PDT 24
Finished Jul 21 05:58:51 PM PDT 24
Peak memory 249092 kb
Host smart-2e2e7a49-1b8a-4bb4-ac9a-e1af5237f38b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3015676795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3015676795
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.2263428035
Short name T28
Test name
Test status
Simulation time 39611807226 ps
CPU time 2523.69 seconds
Started Jul 21 06:07:28 PM PDT 24
Finished Jul 21 06:49:33 PM PDT 24
Peak memory 289512 kb
Host smart-3d2edcff-5c3e-4424-9b0c-7c8ba1dea43d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263428035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2263428035
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.311412267
Short name T494
Test name
Test status
Simulation time 1627329620 ps
CPU time 19.13 seconds
Started Jul 21 06:07:21 PM PDT 24
Finished Jul 21 06:07:40 PM PDT 24
Peak memory 249020 kb
Host smart-49abff8b-bb44-4ba8-b735-b7f7169422e7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=311412267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.311412267
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.3596943876
Short name T522
Test name
Test status
Simulation time 123295057 ps
CPU time 4.84 seconds
Started Jul 21 06:07:21 PM PDT 24
Finished Jul 21 06:07:26 PM PDT 24
Peak memory 240816 kb
Host smart-35a3e941-c6ad-4371-b53d-fbbed6e476f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35969
43876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.3596943876
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.4053395857
Short name T702
Test name
Test status
Simulation time 896062143 ps
CPU time 60.38 seconds
Started Jul 21 06:07:22 PM PDT 24
Finished Jul 21 06:08:23 PM PDT 24
Peak memory 249016 kb
Host smart-08add1f8-79ec-40fa-bb1e-268b471a1da2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40533
95857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.4053395857
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3531304377
Short name T480
Test name
Test status
Simulation time 179332793536 ps
CPU time 1494.44 seconds
Started Jul 21 06:07:26 PM PDT 24
Finished Jul 21 06:32:21 PM PDT 24
Peak memory 273060 kb
Host smart-3e0beedc-9e2f-454f-9eac-e68f88e9268d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531304377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3531304377
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.2185359702
Short name T639
Test name
Test status
Simulation time 64742344535 ps
CPU time 236.71 seconds
Started Jul 21 06:07:19 PM PDT 24
Finished Jul 21 06:11:16 PM PDT 24
Peak memory 248956 kb
Host smart-fc5a6f04-0291-49d8-9d86-a792810bd98d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185359702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.2185359702
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.2062456717
Short name T229
Test name
Test status
Simulation time 1159865390 ps
CPU time 50.66 seconds
Started Jul 21 06:07:21 PM PDT 24
Finished Jul 21 06:08:12 PM PDT 24
Peak memory 248936 kb
Host smart-c2ba88fd-2906-446a-a136-07b47c59fe23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20624
56717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2062456717
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.1746827125
Short name T373
Test name
Test status
Simulation time 4125139890 ps
CPU time 65.2 seconds
Started Jul 21 06:07:28 PM PDT 24
Finished Jul 21 06:08:33 PM PDT 24
Peak memory 249084 kb
Host smart-78071653-287a-485a-9aaf-8f7e42e3f223
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17468
27125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.1746827125
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.613373527
Short name T12
Test name
Test status
Simulation time 672537012 ps
CPU time 28.52 seconds
Started Jul 21 06:07:21 PM PDT 24
Finished Jul 21 06:07:50 PM PDT 24
Peak memory 278920 kb
Host smart-228df6af-c198-48f9-8a33-6b91425ed090
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=613373527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.613373527
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1086074583
Short name T599
Test name
Test status
Simulation time 1654909207 ps
CPU time 45.07 seconds
Started Jul 21 06:07:21 PM PDT 24
Finished Jul 21 06:08:06 PM PDT 24
Peak memory 249008 kb
Host smart-171d1871-df2f-49af-9e35-fbb14a034d4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10860
74583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1086074583
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1623273805
Short name T448
Test name
Test status
Simulation time 1194243449 ps
CPU time 27.24 seconds
Started Jul 21 06:07:20 PM PDT 24
Finished Jul 21 06:07:47 PM PDT 24
Peak memory 257148 kb
Host smart-3a3092ad-eba1-4940-9a22-ae05c6e779a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16232
73805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1623273805
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.98638642
Short name T233
Test name
Test status
Simulation time 42461066390 ps
CPU time 2676.64 seconds
Started Jul 21 06:07:22 PM PDT 24
Finished Jul 21 06:51:59 PM PDT 24
Peak memory 290012 kb
Host smart-60676541-3669-4ed3-b722-b9e50cce7e5a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98638642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handl
er_stress_all.98638642
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.4048705501
Short name T56
Test name
Test status
Simulation time 61468305434 ps
CPU time 1862.83 seconds
Started Jul 21 06:07:27 PM PDT 24
Finished Jul 21 06:38:30 PM PDT 24
Peak memory 281940 kb
Host smart-bb185e23-00f4-49a6-889c-612b44f9d536
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048705501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.4048705501
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.477709107
Short name T706
Test name
Test status
Simulation time 531833964 ps
CPU time 25.33 seconds
Started Jul 21 06:07:29 PM PDT 24
Finished Jul 21 06:07:55 PM PDT 24
Peak memory 249000 kb
Host smart-1c0fe246-c9f6-4d35-bb74-360beaa3053e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=477709107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.477709107
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2163253547
Short name T62
Test name
Test status
Simulation time 792441293 ps
CPU time 64.31 seconds
Started Jul 21 06:07:28 PM PDT 24
Finished Jul 21 06:08:33 PM PDT 24
Peak memory 256564 kb
Host smart-3845feae-78f8-4112-9643-3d42fc631a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21632
53547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2163253547
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3586842631
Short name T554
Test name
Test status
Simulation time 433021423 ps
CPU time 33.64 seconds
Started Jul 21 06:07:30 PM PDT 24
Finished Jul 21 06:08:04 PM PDT 24
Peak memory 256328 kb
Host smart-cd62310f-50ec-487d-9b53-fd0a03912b5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35868
42631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3586842631
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3588181923
Short name T534
Test name
Test status
Simulation time 34966792642 ps
CPU time 723.05 seconds
Started Jul 21 06:07:29 PM PDT 24
Finished Jul 21 06:19:32 PM PDT 24
Peak memory 272980 kb
Host smart-834b6cca-2006-4ace-b622-34237d69cadf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588181923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3588181923
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.3851104640
Short name T324
Test name
Test status
Simulation time 39292212238 ps
CPU time 408.04 seconds
Started Jul 21 06:07:30 PM PDT 24
Finished Jul 21 06:14:19 PM PDT 24
Peak memory 249068 kb
Host smart-95728a32-5ebb-49b9-aaab-0a8f5a256159
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851104640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.3851104640
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1022078747
Short name T654
Test name
Test status
Simulation time 165911026 ps
CPU time 7.37 seconds
Started Jul 21 06:07:30 PM PDT 24
Finished Jul 21 06:07:38 PM PDT 24
Peak memory 249032 kb
Host smart-372a8d41-6343-467d-a863-f3545448cc5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10220
78747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1022078747
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2794884374
Short name T490
Test name
Test status
Simulation time 1254670384 ps
CPU time 25.19 seconds
Started Jul 21 06:07:22 PM PDT 24
Finished Jul 21 06:07:47 PM PDT 24
Peak memory 248928 kb
Host smart-1d894602-19fa-44dc-8dfd-71f960e8f734
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27948
84374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2794884374
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3401909680
Short name T32
Test name
Test status
Simulation time 622153492 ps
CPU time 28.67 seconds
Started Jul 21 06:07:29 PM PDT 24
Finished Jul 21 06:07:58 PM PDT 24
Peak memory 274172 kb
Host smart-35bb08e6-9e84-4249-8470-2c46413a7393
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3401909680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3401909680
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2197356856
Short name T275
Test name
Test status
Simulation time 3537160576 ps
CPU time 21.15 seconds
Started Jul 21 06:07:28 PM PDT 24
Finished Jul 21 06:07:50 PM PDT 24
Peak memory 248984 kb
Host smart-1db01345-ba47-45b7-8363-7aa3587057ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21973
56856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2197356856
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.1667924759
Short name T669
Test name
Test status
Simulation time 174221439 ps
CPU time 16.02 seconds
Started Jul 21 06:07:20 PM PDT 24
Finished Jul 21 06:07:37 PM PDT 24
Peak memory 257144 kb
Host smart-ce769277-71b6-4a0c-80c6-d596f16dd063
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16679
24759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.1667924759
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.2412621872
Short name T616
Test name
Test status
Simulation time 33391080447 ps
CPU time 1944.62 seconds
Started Jul 21 06:07:29 PM PDT 24
Finished Jul 21 06:39:54 PM PDT 24
Peak memory 288820 kb
Host smart-a8e0c457-2959-48ef-a196-c6c7d2906714
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412621872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.2412621872
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.339067618
Short name T93
Test name
Test status
Simulation time 42331772843 ps
CPU time 2352.81 seconds
Started Jul 21 06:08:13 PM PDT 24
Finished Jul 21 06:47:27 PM PDT 24
Peak memory 289760 kb
Host smart-c2fbc6c7-386d-49d9-8a17-7560bbfba7d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339067618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.339067618
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.649716639
Short name T686
Test name
Test status
Simulation time 240825685 ps
CPU time 14.33 seconds
Started Jul 21 06:08:14 PM PDT 24
Finished Jul 21 06:08:29 PM PDT 24
Peak memory 248984 kb
Host smart-b73e1a76-91ac-485d-8d7c-9fcdf475b292
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=649716639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.649716639
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.399621591
Short name T612
Test name
Test status
Simulation time 1763998166 ps
CPU time 136.42 seconds
Started Jul 21 06:08:14 PM PDT 24
Finished Jul 21 06:10:31 PM PDT 24
Peak memory 257128 kb
Host smart-d7df0c2e-e878-4eb3-91a9-bfe3e6ea0cad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39962
1591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.399621591
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.2228575524
Short name T457
Test name
Test status
Simulation time 502081929 ps
CPU time 9.16 seconds
Started Jul 21 06:08:07 PM PDT 24
Finished Jul 21 06:08:17 PM PDT 24
Peak memory 253988 kb
Host smart-f1449e6b-53a8-47c1-b6d4-5f0eec18e77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22285
75524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.2228575524
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2422335476
Short name T244
Test name
Test status
Simulation time 23753100274 ps
CPU time 1531.36 seconds
Started Jul 21 06:08:13 PM PDT 24
Finished Jul 21 06:33:45 PM PDT 24
Peak memory 273696 kb
Host smart-3ee87832-c024-4494-9b80-2af8f7085baa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422335476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2422335476
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.2532326883
Short name T315
Test name
Test status
Simulation time 23338555343 ps
CPU time 489.52 seconds
Started Jul 21 06:08:14 PM PDT 24
Finished Jul 21 06:16:24 PM PDT 24
Peak memory 255744 kb
Host smart-b935487d-677e-479c-b71f-15319967017b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532326883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.2532326883
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2024553021
Short name T610
Test name
Test status
Simulation time 222725634 ps
CPU time 15.68 seconds
Started Jul 21 06:08:05 PM PDT 24
Finished Jul 21 06:08:21 PM PDT 24
Peak memory 248932 kb
Host smart-be870826-4a46-460f-b77c-b2b98c6cda36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20245
53021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2024553021
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2280949245
Short name T471
Test name
Test status
Simulation time 2737215620 ps
CPU time 46 seconds
Started Jul 21 06:08:07 PM PDT 24
Finished Jul 21 06:08:54 PM PDT 24
Peak memory 248824 kb
Host smart-e90ccc8d-2d3a-4c42-8744-be18a849b02a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22809
49245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2280949245
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.285387692
Short name T120
Test name
Test status
Simulation time 2183743528 ps
CPU time 27.58 seconds
Started Jul 21 06:08:18 PM PDT 24
Finished Jul 21 06:08:46 PM PDT 24
Peak memory 248672 kb
Host smart-11665721-3b63-4ca2-8599-c53a8cf54fde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28538
7692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.285387692
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.2212695896
Short name T431
Test name
Test status
Simulation time 5428023306 ps
CPU time 51.95 seconds
Started Jul 21 06:08:07 PM PDT 24
Finished Jul 21 06:08:59 PM PDT 24
Peak memory 257344 kb
Host smart-3b110107-c9c2-4f3e-b95f-8929136daafb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22126
95896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2212695896
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1772320476
Short name T512
Test name
Test status
Simulation time 119046031977 ps
CPU time 3391.15 seconds
Started Jul 21 06:08:14 PM PDT 24
Finished Jul 21 07:04:46 PM PDT 24
Peak memory 289992 kb
Host smart-ac491af0-85f4-4560-a7d1-0ef4e51e7e17
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772320476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1772320476
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3174916166
Short name T508
Test name
Test status
Simulation time 40340115039 ps
CPU time 2515.99 seconds
Started Jul 21 06:08:13 PM PDT 24
Finished Jul 21 06:50:09 PM PDT 24
Peak memory 289896 kb
Host smart-8bfaaf18-6b97-4309-bc35-4722a34af6fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174916166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3174916166
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2546245246
Short name T548
Test name
Test status
Simulation time 325197202 ps
CPU time 17.39 seconds
Started Jul 21 06:08:19 PM PDT 24
Finished Jul 21 06:08:36 PM PDT 24
Peak memory 249024 kb
Host smart-99ba3fca-856b-4a7c-94f8-33f43a5efcae
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2546245246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2546245246
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.793849775
Short name T463
Test name
Test status
Simulation time 6077177195 ps
CPU time 188.14 seconds
Started Jul 21 06:08:13 PM PDT 24
Finished Jul 21 06:11:22 PM PDT 24
Peak memory 257312 kb
Host smart-212cc45c-01e3-43b7-af94-b91005c525b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79384
9775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.793849775
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.4194634363
Short name T697
Test name
Test status
Simulation time 51875429 ps
CPU time 3.82 seconds
Started Jul 21 06:08:15 PM PDT 24
Finished Jul 21 06:08:19 PM PDT 24
Peak memory 249016 kb
Host smart-0c6594d9-837e-42dc-b19f-bfbf331c8435
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41946
34363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.4194634363
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.1870647954
Short name T423
Test name
Test status
Simulation time 31393559303 ps
CPU time 1465.78 seconds
Started Jul 21 06:08:20 PM PDT 24
Finished Jul 21 06:32:46 PM PDT 24
Peak memory 288028 kb
Host smart-36443db6-1303-41ed-82de-b3d4bf376052
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1870647954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1870647954
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.2325707561
Short name T671
Test name
Test status
Simulation time 66095271588 ps
CPU time 343.37 seconds
Started Jul 21 06:08:20 PM PDT 24
Finished Jul 21 06:14:04 PM PDT 24
Peak memory 255512 kb
Host smart-8f3a80bf-ca05-4f42-b3d6-b646c5a96f4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325707561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2325707561
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.2409850453
Short name T388
Test name
Test status
Simulation time 48196369 ps
CPU time 4.45 seconds
Started Jul 21 06:08:13 PM PDT 24
Finished Jul 21 06:08:18 PM PDT 24
Peak memory 249044 kb
Host smart-5ec63567-57c5-4cb1-b580-93878082f05b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24098
50453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.2409850453
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2237925299
Short name T378
Test name
Test status
Simulation time 552436922 ps
CPU time 25.26 seconds
Started Jul 21 06:08:15 PM PDT 24
Finished Jul 21 06:08:40 PM PDT 24
Peak memory 249416 kb
Host smart-de9ca7b2-8846-4d24-a8ca-91423f0c62fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22379
25299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2237925299
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1147434332
Short name T598
Test name
Test status
Simulation time 126371724 ps
CPU time 4.73 seconds
Started Jul 21 06:08:14 PM PDT 24
Finished Jul 21 06:08:19 PM PDT 24
Peak memory 248928 kb
Host smart-01206da2-f9c8-43ea-b43c-bcea4c1f755b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11474
34332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1147434332
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1579789604
Short name T464
Test name
Test status
Simulation time 51777997841 ps
CPU time 847.07 seconds
Started Jul 21 06:08:19 PM PDT 24
Finished Jul 21 06:22:26 PM PDT 24
Peak memory 265464 kb
Host smart-0db39e6b-9e4e-4adf-8c0c-3cc691be816f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579789604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1579789604
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1571516069
Short name T212
Test name
Test status
Simulation time 58513721 ps
CPU time 3.27 seconds
Started Jul 21 06:08:25 PM PDT 24
Finished Jul 21 06:08:29 PM PDT 24
Peak memory 249172 kb
Host smart-5120ea19-7d7a-4931-8165-b26d667726ea
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1571516069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1571516069
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3232530608
Short name T690
Test name
Test status
Simulation time 21546630498 ps
CPU time 1260.32 seconds
Started Jul 21 06:08:20 PM PDT 24
Finished Jul 21 06:29:21 PM PDT 24
Peak memory 290044 kb
Host smart-0f0ff508-41f4-457f-a55e-3db088fabd26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232530608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3232530608
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3237153119
Short name T429
Test name
Test status
Simulation time 159683178 ps
CPU time 9.52 seconds
Started Jul 21 06:08:25 PM PDT 24
Finished Jul 21 06:08:35 PM PDT 24
Peak memory 248904 kb
Host smart-40f175c9-bed0-4a5e-bb15-a9e53d79014a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3237153119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3237153119
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.521157083
Short name T576
Test name
Test status
Simulation time 4849479522 ps
CPU time 66.44 seconds
Started Jul 21 06:08:18 PM PDT 24
Finished Jul 21 06:09:25 PM PDT 24
Peak memory 248788 kb
Host smart-2edcd13e-91a6-40aa-9321-da06accac2a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52115
7083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.521157083
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2654335120
Short name T605
Test name
Test status
Simulation time 702806850 ps
CPU time 14.56 seconds
Started Jul 21 06:08:20 PM PDT 24
Finished Jul 21 06:08:35 PM PDT 24
Peak memory 248988 kb
Host smart-5e620d19-ecf2-4a79-9544-2d8a59f87e32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26543
35120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2654335120
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.661978636
Short name T581
Test name
Test status
Simulation time 118624466569 ps
CPU time 3539.65 seconds
Started Jul 21 06:08:26 PM PDT 24
Finished Jul 21 07:07:26 PM PDT 24
Peak memory 290000 kb
Host smart-b7ffabf1-0136-4d4b-958b-2020c124cd44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661978636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.661978636
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.3036833792
Short name T329
Test name
Test status
Simulation time 72214085716 ps
CPU time 262.78 seconds
Started Jul 21 06:08:24 PM PDT 24
Finished Jul 21 06:12:47 PM PDT 24
Peak memory 249084 kb
Host smart-2ee2b4a6-c99c-4a8f-99c8-8c5a6f86bc06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036833792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3036833792
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.823934370
Short name T540
Test name
Test status
Simulation time 992220657 ps
CPU time 20.12 seconds
Started Jul 21 06:08:20 PM PDT 24
Finished Jul 21 06:08:41 PM PDT 24
Peak memory 256488 kb
Host smart-fefc5a79-5ca1-4b13-a187-d01938e9375e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82393
4370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.823934370
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.3153832991
Short name T565
Test name
Test status
Simulation time 188677829 ps
CPU time 8.01 seconds
Started Jul 21 06:08:22 PM PDT 24
Finished Jul 21 06:08:30 PM PDT 24
Peak memory 249140 kb
Host smart-f6ff66ae-f39a-4620-9593-b897b065523a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31538
32991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3153832991
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.2169472899
Short name T40
Test name
Test status
Simulation time 1989770763 ps
CPU time 53.65 seconds
Started Jul 21 06:08:21 PM PDT 24
Finished Jul 21 06:09:15 PM PDT 24
Peak memory 256212 kb
Host smart-59514d89-d6db-492c-9716-26466894c511
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21694
72899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.2169472899
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.142668644
Short name T367
Test name
Test status
Simulation time 4689444563 ps
CPU time 74.23 seconds
Started Jul 21 06:08:19 PM PDT 24
Finished Jul 21 06:09:33 PM PDT 24
Peak memory 249468 kb
Host smart-787f8ddd-ce80-4e12-8f02-7ed073bb96cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14266
8644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.142668644
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.1089970986
Short name T588
Test name
Test status
Simulation time 36100514223 ps
CPU time 2391.37 seconds
Started Jul 21 06:08:24 PM PDT 24
Finished Jul 21 06:48:16 PM PDT 24
Peak memory 290072 kb
Host smart-4a77ac8e-b90b-4004-ac60-33df59f0ff81
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089970986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.1089970986
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.4176917837
Short name T77
Test name
Test status
Simulation time 674095388658 ps
CPU time 7949.49 seconds
Started Jul 21 06:08:30 PM PDT 24
Finished Jul 21 08:21:01 PM PDT 24
Peak memory 322660 kb
Host smart-01171fa5-a45f-4e98-b791-e89b9701a545
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176917837 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.4176917837
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.2985664124
Short name T207
Test name
Test status
Simulation time 16362922 ps
CPU time 2.93 seconds
Started Jul 21 06:08:27 PM PDT 24
Finished Jul 21 06:08:30 PM PDT 24
Peak memory 249260 kb
Host smart-5f00e64f-488d-41ae-93e1-8d3a484eb0e2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2985664124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2985664124
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.494528591
Short name T523
Test name
Test status
Simulation time 21678075450 ps
CPU time 1403.94 seconds
Started Jul 21 06:08:25 PM PDT 24
Finished Jul 21 06:31:50 PM PDT 24
Peak memory 273572 kb
Host smart-26dd9463-ddad-4137-b449-891f91a429ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494528591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.494528591
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.2541123441
Short name T252
Test name
Test status
Simulation time 1948230463 ps
CPU time 23.13 seconds
Started Jul 21 06:08:25 PM PDT 24
Finished Jul 21 06:08:49 PM PDT 24
Peak memory 248972 kb
Host smart-3d221479-81ec-446c-9609-3edfcd4979b6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2541123441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.2541123441
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3505708172
Short name T648
Test name
Test status
Simulation time 1599031942 ps
CPU time 98.07 seconds
Started Jul 21 06:08:24 PM PDT 24
Finished Jul 21 06:10:03 PM PDT 24
Peak memory 257140 kb
Host smart-bf131dff-135a-48ba-a2d8-011f03a9eb4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35057
08172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3505708172
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.3543934047
Short name T68
Test name
Test status
Simulation time 3907062130 ps
CPU time 21.53 seconds
Started Jul 21 06:08:29 PM PDT 24
Finished Jul 21 06:08:51 PM PDT 24
Peak memory 248528 kb
Host smart-32f34dcc-ec20-4e4a-9fea-3256d2afeb26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35439
34047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.3543934047
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3296669043
Short name T311
Test name
Test status
Simulation time 98267051564 ps
CPU time 1441.73 seconds
Started Jul 21 06:08:26 PM PDT 24
Finished Jul 21 06:32:28 PM PDT 24
Peak memory 273268 kb
Host smart-4e19ba6c-5038-4e5c-88b7-cadba4f49559
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296669043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3296669043
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1160750862
Short name T519
Test name
Test status
Simulation time 7745762745 ps
CPU time 326.13 seconds
Started Jul 21 06:08:26 PM PDT 24
Finished Jul 21 06:13:52 PM PDT 24
Peak memory 257204 kb
Host smart-42187e25-ee21-4830-b7cc-a68e99ee1455
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1160750862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1160750862
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2427506984
Short name T99
Test name
Test status
Simulation time 52749610 ps
CPU time 4.58 seconds
Started Jul 21 06:08:25 PM PDT 24
Finished Jul 21 06:08:30 PM PDT 24
Peak memory 249012 kb
Host smart-430e1e33-85bc-4eeb-9917-47d027720f0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24275
06984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2427506984
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.4148270016
Short name T303
Test name
Test status
Simulation time 994437202 ps
CPU time 64.87 seconds
Started Jul 21 06:08:24 PM PDT 24
Finished Jul 21 06:09:29 PM PDT 24
Peak memory 256648 kb
Host smart-39ce13e5-cbae-4e72-b39b-e0b83cb77d48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41482
70016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.4148270016
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.1508726281
Short name T113
Test name
Test status
Simulation time 7688024131 ps
CPU time 38.82 seconds
Started Jul 21 06:08:24 PM PDT 24
Finished Jul 21 06:09:03 PM PDT 24
Peak memory 249084 kb
Host smart-a4bd34ef-4283-45be-9815-16a0d914eaf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15087
26281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.1508726281
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1118947434
Short name T637
Test name
Test status
Simulation time 1089577035 ps
CPU time 29.34 seconds
Started Jul 21 06:08:25 PM PDT 24
Finished Jul 21 06:08:55 PM PDT 24
Peak memory 257100 kb
Host smart-cc1130be-f1f3-40be-8b93-57758a600d31
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11189
47434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1118947434
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.658471533
Short name T217
Test name
Test status
Simulation time 46701548 ps
CPU time 2.51 seconds
Started Jul 21 06:08:40 PM PDT 24
Finished Jul 21 06:08:43 PM PDT 24
Peak memory 249124 kb
Host smart-cb52dded-0fdc-4d9b-acfd-a1f52a25aae4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=658471533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.658471533
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.826849254
Short name T13
Test name
Test status
Simulation time 75970402712 ps
CPU time 1395.2 seconds
Started Jul 21 06:08:37 PM PDT 24
Finished Jul 21 06:31:53 PM PDT 24
Peak memory 289984 kb
Host smart-445d7b9b-4502-494c-805f-7818437ede00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826849254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.826849254
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.865132314
Short name T595
Test name
Test status
Simulation time 1268776396 ps
CPU time 15.54 seconds
Started Jul 21 06:08:38 PM PDT 24
Finished Jul 21 06:08:54 PM PDT 24
Peak memory 248916 kb
Host smart-ce1a25da-6f46-405d-8594-e23a51d73fd4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=865132314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.865132314
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2370091179
Short name T43
Test name
Test status
Simulation time 17288952110 ps
CPU time 146.22 seconds
Started Jul 21 06:08:40 PM PDT 24
Finished Jul 21 06:11:06 PM PDT 24
Peak memory 257320 kb
Host smart-960722ae-b8fd-4c64-a219-b05c119c1cfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23700
91179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2370091179
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.2401737038
Short name T430
Test name
Test status
Simulation time 378509510 ps
CPU time 25.56 seconds
Started Jul 21 06:08:36 PM PDT 24
Finished Jul 21 06:09:02 PM PDT 24
Peak memory 257032 kb
Host smart-e47f284c-d009-497b-8c5b-137565adacba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24017
37038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2401737038
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2912482465
Short name T71
Test name
Test status
Simulation time 47846134182 ps
CPU time 1775.25 seconds
Started Jul 21 06:08:40 PM PDT 24
Finished Jul 21 06:38:16 PM PDT 24
Peak memory 272976 kb
Host smart-f0394f54-e4d1-4aee-ad6a-f6c1a083e449
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912482465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2912482465
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.1147020050
Short name T495
Test name
Test status
Simulation time 2271542237 ps
CPU time 96.2 seconds
Started Jul 21 06:08:41 PM PDT 24
Finished Jul 21 06:10:18 PM PDT 24
Peak memory 249064 kb
Host smart-e14ae8f5-620e-4aee-b3b2-20805b680bc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147020050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.1147020050
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.91506392
Short name T29
Test name
Test status
Simulation time 1603164722 ps
CPU time 35.99 seconds
Started Jul 21 06:08:37 PM PDT 24
Finished Jul 21 06:09:13 PM PDT 24
Peak memory 256448 kb
Host smart-88691b17-e573-4050-8d5a-6e216809ec5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91506
392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.91506392
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.4275974481
Short name T241
Test name
Test status
Simulation time 846414868 ps
CPU time 18.78 seconds
Started Jul 21 06:08:38 PM PDT 24
Finished Jul 21 06:08:57 PM PDT 24
Peak memory 249320 kb
Host smart-85f110f8-c2fc-4f56-b4cf-49e14b4df9a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42759
74481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.4275974481
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.3491502016
Short name T386
Test name
Test status
Simulation time 1469955979 ps
CPU time 21.65 seconds
Started Jul 21 06:08:38 PM PDT 24
Finished Jul 21 06:09:00 PM PDT 24
Peak memory 256256 kb
Host smart-25556915-5e3a-4e82-a66d-8e00d4e34798
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34915
02016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3491502016
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.1857000019
Short name T568
Test name
Test status
Simulation time 1167536326 ps
CPU time 10.41 seconds
Started Jul 21 06:08:42 PM PDT 24
Finished Jul 21 06:08:52 PM PDT 24
Peak memory 255092 kb
Host smart-de88df77-e936-4f0a-8216-85bb39d72d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18570
00019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.1857000019
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3831480714
Short name T538
Test name
Test status
Simulation time 33085157766 ps
CPU time 528.62 seconds
Started Jul 21 06:08:36 PM PDT 24
Finished Jul 21 06:17:25 PM PDT 24
Peak memory 257260 kb
Host smart-c8603dd6-777f-4a0c-8160-be84ba0810a0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831480714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3831480714
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.342401007
Short name T215
Test name
Test status
Simulation time 37788201 ps
CPU time 3.14 seconds
Started Jul 21 06:08:40 PM PDT 24
Finished Jul 21 06:08:43 PM PDT 24
Peak memory 249248 kb
Host smart-a3fba0bd-9bf5-400a-be53-90a67ce6ea3c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=342401007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.342401007
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.4130057637
Short name T118
Test name
Test status
Simulation time 32727083512 ps
CPU time 1903.3 seconds
Started Jul 21 06:08:39 PM PDT 24
Finished Jul 21 06:40:23 PM PDT 24
Peak memory 273620 kb
Host smart-4813e40a-dec2-4426-83f3-95bee16f6b43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4130057637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.4130057637
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.919766906
Short name T445
Test name
Test status
Simulation time 684674771 ps
CPU time 16.46 seconds
Started Jul 21 06:08:39 PM PDT 24
Finished Jul 21 06:08:55 PM PDT 24
Peak memory 248920 kb
Host smart-65d4cab3-83ea-4a66-a51e-d8f2e8f646e7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=919766906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.919766906
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1052004147
Short name T466
Test name
Test status
Simulation time 2446119488 ps
CPU time 142.39 seconds
Started Jul 21 06:08:39 PM PDT 24
Finished Jul 21 06:11:02 PM PDT 24
Peak memory 250028 kb
Host smart-0134e4d9-8c4b-405b-87b1-60c7f1b5a697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10520
04147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1052004147
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.3802426665
Short name T469
Test name
Test status
Simulation time 506702696 ps
CPU time 16.22 seconds
Started Jul 21 06:08:41 PM PDT 24
Finished Jul 21 06:08:58 PM PDT 24
Peak memory 249420 kb
Host smart-1b9fee89-4b0b-40b5-ac53-ca7b3993504c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38024
26665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.3802426665
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.1651709664
Short name T240
Test name
Test status
Simulation time 34369389367 ps
CPU time 757.46 seconds
Started Jul 21 06:08:41 PM PDT 24
Finished Jul 21 06:21:19 PM PDT 24
Peak memory 272800 kb
Host smart-285d5d18-00da-4b37-93f1-1f94720b548d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651709664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1651709664
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3788836087
Short name T684
Test name
Test status
Simulation time 57104927120 ps
CPU time 329.01 seconds
Started Jul 21 06:08:40 PM PDT 24
Finished Jul 21 06:14:09 PM PDT 24
Peak memory 249148 kb
Host smart-6c8d61ae-4fb2-4c1b-9ceb-ae22af79c69a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788836087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3788836087
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3325999198
Short name T575
Test name
Test status
Simulation time 17089825 ps
CPU time 2.82 seconds
Started Jul 21 06:08:38 PM PDT 24
Finished Jul 21 06:08:41 PM PDT 24
Peak memory 249044 kb
Host smart-cb581212-cf62-4429-a875-83ce8bb185b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33259
99198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3325999198
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3315003580
Short name T413
Test name
Test status
Simulation time 725338747 ps
CPU time 23.98 seconds
Started Jul 21 06:08:40 PM PDT 24
Finished Jul 21 06:09:04 PM PDT 24
Peak memory 248992 kb
Host smart-e796f585-8bda-40f6-9c59-922f142322cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33150
03580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3315003580
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2094292861
Short name T89
Test name
Test status
Simulation time 1071928906 ps
CPU time 44.3 seconds
Started Jul 21 06:08:39 PM PDT 24
Finished Jul 21 06:09:24 PM PDT 24
Peak memory 248340 kb
Host smart-3a54f216-9335-4316-a7ac-d44ec29e9d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20942
92861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2094292861
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.3768745
Short name T608
Test name
Test status
Simulation time 691558141 ps
CPU time 44.48 seconds
Started Jul 21 06:08:38 PM PDT 24
Finished Jul 21 06:09:23 PM PDT 24
Peak memory 257156 kb
Host smart-97576ff6-cd16-4d09-a23f-170255e9cf3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37687
45 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3768745
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2484738409
Short name T489
Test name
Test status
Simulation time 100799985698 ps
CPU time 2878.29 seconds
Started Jul 21 06:08:40 PM PDT 24
Finished Jul 21 06:56:39 PM PDT 24
Peak memory 281888 kb
Host smart-60ab93a0-0151-4fff-9558-14d5806f1b70
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484738409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2484738409
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.1776189837
Short name T630
Test name
Test status
Simulation time 26798808756 ps
CPU time 1889.47 seconds
Started Jul 21 06:08:38 PM PDT 24
Finished Jul 21 06:40:08 PM PDT 24
Peak memory 288612 kb
Host smart-a824cdfc-16e8-4f12-ace8-d476c714f0d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776189837 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.1776189837
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3084343684
Short name T224
Test name
Test status
Simulation time 51855913 ps
CPU time 4.17 seconds
Started Jul 21 06:08:44 PM PDT 24
Finished Jul 21 06:08:49 PM PDT 24
Peak memory 249232 kb
Host smart-51a87869-9f44-47fe-b2d6-5b108ddef1f2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3084343684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3084343684
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1747268351
Short name T391
Test name
Test status
Simulation time 10075222883 ps
CPU time 950.1 seconds
Started Jul 21 06:08:46 PM PDT 24
Finished Jul 21 06:24:37 PM PDT 24
Peak memory 273496 kb
Host smart-b5b23830-714e-4c7f-bb0f-eaa3a07cef68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747268351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1747268351
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.473599316
Short name T253
Test name
Test status
Simulation time 2114976137 ps
CPU time 17.47 seconds
Started Jul 21 06:08:42 PM PDT 24
Finished Jul 21 06:09:00 PM PDT 24
Peak memory 249004 kb
Host smart-e3eb97ec-e33b-4699-891d-11dd895433b3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=473599316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.473599316
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.1523712578
Short name T250
Test name
Test status
Simulation time 729670948 ps
CPU time 48.61 seconds
Started Jul 21 06:08:44 PM PDT 24
Finished Jul 21 06:09:33 PM PDT 24
Peak memory 256756 kb
Host smart-04a7ed6d-4e45-4249-addc-e81290065653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15237
12578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1523712578
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.714272106
Short name T456
Test name
Test status
Simulation time 1606418464 ps
CPU time 22.58 seconds
Started Jul 21 06:08:46 PM PDT 24
Finished Jul 21 06:09:09 PM PDT 24
Peak memory 256312 kb
Host smart-c80ffecf-c2c0-42f1-b55d-337ec969ac0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71427
2106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.714272106
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.314784961
Short name T356
Test name
Test status
Simulation time 26443646495 ps
CPU time 1603.97 seconds
Started Jul 21 06:08:44 PM PDT 24
Finished Jul 21 06:35:28 PM PDT 24
Peak memory 281848 kb
Host smart-031c6593-3976-4a8c-ba57-6cd55c2f63a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314784961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.314784961
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.1141136135
Short name T435
Test name
Test status
Simulation time 477269192980 ps
CPU time 2282.75 seconds
Started Jul 21 06:08:44 PM PDT 24
Finished Jul 21 06:46:47 PM PDT 24
Peak memory 283624 kb
Host smart-9539b801-0703-4dc5-94d0-3b944761b4ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141136135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1141136135
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1993135266
Short name T676
Test name
Test status
Simulation time 7604432611 ps
CPU time 283.42 seconds
Started Jul 21 06:08:44 PM PDT 24
Finished Jul 21 06:13:27 PM PDT 24
Peak memory 247948 kb
Host smart-5c65ed3f-8198-434e-8e67-b1cd27b1e7fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993135266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1993135266
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.3674058258
Short name T227
Test name
Test status
Simulation time 1237014219 ps
CPU time 34.61 seconds
Started Jul 21 06:08:40 PM PDT 24
Finished Jul 21 06:09:15 PM PDT 24
Peak memory 256512 kb
Host smart-4f5eda6c-2070-4cb0-b8e8-05bf6114845b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36740
58258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.3674058258
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.178889112
Short name T665
Test name
Test status
Simulation time 1633634499 ps
CPU time 31.6 seconds
Started Jul 21 06:08:42 PM PDT 24
Finished Jul 21 06:09:14 PM PDT 24
Peak memory 256212 kb
Host smart-c5c335c7-5ca2-485a-8046-44d7a84e9aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17888
9112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.178889112
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.47163675
Short name T249
Test name
Test status
Simulation time 26265436 ps
CPU time 3.83 seconds
Started Jul 21 06:08:46 PM PDT 24
Finished Jul 21 06:08:51 PM PDT 24
Peak memory 240396 kb
Host smart-2adae432-a3cd-4ff5-b113-93f8a1a73b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47163
675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.47163675
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.526751105
Short name T231
Test name
Test status
Simulation time 355958976 ps
CPU time 11.04 seconds
Started Jul 21 06:08:38 PM PDT 24
Finished Jul 21 06:08:49 PM PDT 24
Peak memory 255556 kb
Host smart-f821bfd1-b891-4dcb-b70d-7e5523c6d945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52675
1105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.526751105
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2643499805
Short name T681
Test name
Test status
Simulation time 74997251765 ps
CPU time 1953.85 seconds
Started Jul 21 06:08:46 PM PDT 24
Finished Jul 21 06:41:21 PM PDT 24
Peak memory 287224 kb
Host smart-79478570-fe79-4ec9-99b7-0e47278eb83c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643499805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2643499805
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.3474609343
Short name T108
Test name
Test status
Simulation time 129395997456 ps
CPU time 1084.59 seconds
Started Jul 21 06:08:44 PM PDT 24
Finished Jul 21 06:26:49 PM PDT 24
Peak memory 286096 kb
Host smart-8617186c-1abc-4eb7-a02e-f7a801518ca4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474609343 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.3474609343
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.884567841
Short name T211
Test name
Test status
Simulation time 17697504 ps
CPU time 3.11 seconds
Started Jul 21 06:08:49 PM PDT 24
Finished Jul 21 06:08:52 PM PDT 24
Peak memory 249148 kb
Host smart-1cc19304-89f2-4bd6-9db3-6822b89f2bf7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=884567841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.884567841
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3098757398
Short name T414
Test name
Test status
Simulation time 5060310770 ps
CPU time 43.9 seconds
Started Jul 21 06:08:51 PM PDT 24
Finished Jul 21 06:09:35 PM PDT 24
Peak memory 249044 kb
Host smart-c0246c6e-d294-4af3-b643-4586eb8fc51e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3098757398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3098757398
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.419749226
Short name T547
Test name
Test status
Simulation time 1865224239 ps
CPU time 75.9 seconds
Started Jul 21 06:08:44 PM PDT 24
Finished Jul 21 06:10:00 PM PDT 24
Peak memory 256728 kb
Host smart-cee39ec5-691d-46e2-ae47-6fea762d6a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41974
9226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.419749226
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3090954856
Short name T691
Test name
Test status
Simulation time 454793681 ps
CPU time 15.13 seconds
Started Jul 21 06:08:45 PM PDT 24
Finished Jul 21 06:09:00 PM PDT 24
Peak memory 249408 kb
Host smart-5fe6c1d8-9f05-42fc-8a0b-4762254e6be7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30909
54856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3090954856
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.1739256928
Short name T192
Test name
Test status
Simulation time 23784683005 ps
CPU time 1473.96 seconds
Started Jul 21 06:08:49 PM PDT 24
Finished Jul 21 06:33:23 PM PDT 24
Peak memory 273512 kb
Host smart-4dd56e96-855b-4b7a-a29e-b27b602bd61b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739256928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1739256928
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.3481882524
Short name T292
Test name
Test status
Simulation time 11240659918 ps
CPU time 232.29 seconds
Started Jul 21 06:08:52 PM PDT 24
Finished Jul 21 06:12:45 PM PDT 24
Peak memory 255488 kb
Host smart-11021b61-9542-46b9-9c66-d7cd24fc1cdc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481882524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.3481882524
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3087445549
Short name T695
Test name
Test status
Simulation time 4378364040 ps
CPU time 40.97 seconds
Started Jul 21 06:08:51 PM PDT 24
Finished Jul 21 06:09:32 PM PDT 24
Peak memory 257064 kb
Host smart-f945de87-8293-4d25-9600-bc9c9b759d1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30874
45549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3087445549
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2184895289
Short name T433
Test name
Test status
Simulation time 1333595115 ps
CPU time 33.02 seconds
Started Jul 21 06:08:43 PM PDT 24
Finished Jul 21 06:09:16 PM PDT 24
Peak memory 256508 kb
Host smart-61c390e1-cae2-4b28-8d3a-99ad682227cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21848
95289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2184895289
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.251036833
Short name T289
Test name
Test status
Simulation time 515638381 ps
CPU time 38.75 seconds
Started Jul 21 06:08:44 PM PDT 24
Finished Jul 21 06:09:23 PM PDT 24
Peak memory 248956 kb
Host smart-b014307a-ce5f-4763-ae6d-8dcff81c7cac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25103
6833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.251036833
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.1358329969
Short name T493
Test name
Test status
Simulation time 34297798 ps
CPU time 4.16 seconds
Started Jul 21 06:08:52 PM PDT 24
Finished Jul 21 06:08:56 PM PDT 24
Peak memory 249552 kb
Host smart-95e13f71-cee1-4463-af14-8b0d228200eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13583
29969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1358329969
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1313405166
Short name T44
Test name
Test status
Simulation time 5530824697 ps
CPU time 182.06 seconds
Started Jul 21 06:08:53 PM PDT 24
Finished Jul 21 06:11:56 PM PDT 24
Peak memory 257280 kb
Host smart-dbddb1f5-bc36-44fb-ad9a-f9a77cff42b5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313405166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1313405166
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1611958299
Short name T222
Test name
Test status
Simulation time 183486444 ps
CPU time 4.32 seconds
Started Jul 21 06:09:01 PM PDT 24
Finished Jul 21 06:09:06 PM PDT 24
Peak memory 249232 kb
Host smart-92a4a75c-15ee-40d4-85af-ab2133b9627e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1611958299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1611958299
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2166371703
Short name T604
Test name
Test status
Simulation time 177640180911 ps
CPU time 2194.97 seconds
Started Jul 21 06:08:49 PM PDT 24
Finished Jul 21 06:45:25 PM PDT 24
Peak memory 281840 kb
Host smart-cb6becad-6769-4e49-8331-bca030325f88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166371703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2166371703
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1974708553
Short name T438
Test name
Test status
Simulation time 6934388953 ps
CPU time 75.1 seconds
Started Jul 21 06:08:53 PM PDT 24
Finished Jul 21 06:10:09 PM PDT 24
Peak memory 249040 kb
Host smart-12adce2d-9b1c-49d0-8c3d-85c5b83c3139
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1974708553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1974708553
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.1269661219
Short name T371
Test name
Test status
Simulation time 1782253161 ps
CPU time 134.05 seconds
Started Jul 21 06:08:47 PM PDT 24
Finished Jul 21 06:11:02 PM PDT 24
Peak memory 257180 kb
Host smart-b076ac8b-0007-411f-b383-288b417075ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12696
61219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.1269661219
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.3168402731
Short name T551
Test name
Test status
Simulation time 3310575445 ps
CPU time 57 seconds
Started Jul 21 06:08:51 PM PDT 24
Finished Jul 21 06:09:48 PM PDT 24
Peak memory 256272 kb
Host smart-ca7e8024-61a2-45a4-9762-af18cb7469ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31684
02731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3168402731
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.2915713825
Short name T354
Test name
Test status
Simulation time 57400357982 ps
CPU time 3261.07 seconds
Started Jul 21 06:08:49 PM PDT 24
Finished Jul 21 07:03:11 PM PDT 24
Peak memory 289044 kb
Host smart-c9befd28-2444-4135-970c-176e0bba4fe0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915713825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2915713825
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2458640969
Short name T640
Test name
Test status
Simulation time 11711534848 ps
CPU time 1295.73 seconds
Started Jul 21 06:08:49 PM PDT 24
Finished Jul 21 06:30:25 PM PDT 24
Peak memory 289072 kb
Host smart-16b13210-0f5d-47bc-8abc-6d4ff71bb077
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458640969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2458640969
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1213349659
Short name T332
Test name
Test status
Simulation time 12654854525 ps
CPU time 127.58 seconds
Started Jul 21 06:08:47 PM PDT 24
Finished Jul 21 06:10:55 PM PDT 24
Peak memory 249104 kb
Host smart-03b0f98f-5b0d-4d46-a677-d861a318480a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213349659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1213349659
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3135721740
Short name T30
Test name
Test status
Simulation time 512822625 ps
CPU time 9.63 seconds
Started Jul 21 06:08:48 PM PDT 24
Finished Jul 21 06:08:58 PM PDT 24
Peak memory 249048 kb
Host smart-2def6076-62bb-4ba8-8833-1447a20a3d25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31357
21740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3135721740
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.4015735630
Short name T526
Test name
Test status
Simulation time 6436636830 ps
CPU time 48.02 seconds
Started Jul 21 06:08:50 PM PDT 24
Finished Jul 21 06:09:39 PM PDT 24
Peak memory 249096 kb
Host smart-12495921-a565-4c69-93cc-cb6edf4adf07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40157
35630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.4015735630
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.552804909
Short name T701
Test name
Test status
Simulation time 126543051 ps
CPU time 8.02 seconds
Started Jul 21 06:08:52 PM PDT 24
Finished Jul 21 06:09:01 PM PDT 24
Peak memory 249128 kb
Host smart-f215e422-ee96-44c6-81d6-462399a64dfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55280
4909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.552804909
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1014573730
Short name T468
Test name
Test status
Simulation time 12570143804 ps
CPU time 1323.54 seconds
Started Jul 21 06:08:50 PM PDT 24
Finished Jul 21 06:30:55 PM PDT 24
Peak memory 289888 kb
Host smart-2321e5c4-b54f-4ca3-b605-bc64a936bef2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014573730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1014573730
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.2097203674
Short name T218
Test name
Test status
Simulation time 35559411 ps
CPU time 3.52 seconds
Started Jul 21 06:08:56 PM PDT 24
Finished Jul 21 06:09:00 PM PDT 24
Peak memory 249232 kb
Host smart-dec4b61a-53ce-4d44-b098-40f65049f92e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2097203674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.2097203674
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1561571802
Short name T589
Test name
Test status
Simulation time 34076654469 ps
CPU time 1320.23 seconds
Started Jul 21 06:09:00 PM PDT 24
Finished Jul 21 06:31:01 PM PDT 24
Peak memory 289776 kb
Host smart-c2e143f4-35de-461b-b7e4-3982de987527
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561571802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1561571802
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3895788324
Short name T609
Test name
Test status
Simulation time 898850345 ps
CPU time 19.1 seconds
Started Jul 21 06:08:58 PM PDT 24
Finished Jul 21 06:09:17 PM PDT 24
Peak memory 249068 kb
Host smart-96adaee8-1e5b-4449-997d-114a93d5454f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3895788324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3895788324
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2052441606
Short name T527
Test name
Test status
Simulation time 4494562189 ps
CPU time 100.54 seconds
Started Jul 21 06:08:57 PM PDT 24
Finished Jul 21 06:10:38 PM PDT 24
Peak memory 256488 kb
Host smart-ff29dcd4-ac02-49f4-a15d-02fb2430df9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20524
41606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2052441606
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3437945194
Short name T384
Test name
Test status
Simulation time 1316911012 ps
CPU time 13.6 seconds
Started Jul 21 06:08:55 PM PDT 24
Finished Jul 21 06:09:09 PM PDT 24
Peak memory 255036 kb
Host smart-f6e778fd-9b22-47fb-aade-e794522f0341
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34379
45194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3437945194
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2580708393
Short name T337
Test name
Test status
Simulation time 59184688854 ps
CPU time 1315.3 seconds
Started Jul 21 06:08:56 PM PDT 24
Finished Jul 21 06:30:51 PM PDT 24
Peak memory 284888 kb
Host smart-834f5f4b-2083-4e6d-a84e-f08e2feb84c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580708393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2580708393
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.646984703
Short name T455
Test name
Test status
Simulation time 52254890534 ps
CPU time 3175 seconds
Started Jul 21 06:08:53 PM PDT 24
Finished Jul 21 07:01:48 PM PDT 24
Peak memory 290080 kb
Host smart-1ad33b8a-8367-4600-a725-51de669265dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646984703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.646984703
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3695493210
Short name T338
Test name
Test status
Simulation time 5649182381 ps
CPU time 243.83 seconds
Started Jul 21 06:08:54 PM PDT 24
Finished Jul 21 06:12:58 PM PDT 24
Peak memory 249208 kb
Host smart-7287972d-d6ff-4ac7-af71-576b3f036706
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695493210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3695493210
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.225535137
Short name T425
Test name
Test status
Simulation time 222245522 ps
CPU time 21.93 seconds
Started Jul 21 06:08:56 PM PDT 24
Finished Jul 21 06:09:18 PM PDT 24
Peak memory 249048 kb
Host smart-81a45ac1-24e3-4d3c-9ed4-010458204adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22553
5137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.225535137
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.2846835275
Short name T45
Test name
Test status
Simulation time 1096943014 ps
CPU time 19.42 seconds
Started Jul 21 06:08:56 PM PDT 24
Finished Jul 21 06:09:16 PM PDT 24
Peak memory 248544 kb
Host smart-d74a2229-6f99-442a-8d34-b1ae99506ec1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28468
35275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2846835275
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.702128666
Short name T256
Test name
Test status
Simulation time 230894115 ps
CPU time 14.57 seconds
Started Jul 21 06:08:56 PM PDT 24
Finished Jul 21 06:09:11 PM PDT 24
Peak memory 256416 kb
Host smart-aec6e39d-e311-47b8-bece-9e6c0079250a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70212
8666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.702128666
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.168167938
Short name T380
Test name
Test status
Simulation time 762061374 ps
CPU time 14.34 seconds
Started Jul 21 06:08:56 PM PDT 24
Finished Jul 21 06:09:10 PM PDT 24
Peak memory 248960 kb
Host smart-4783ddcf-e4fc-48c5-92e5-00680bff7316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16816
7938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.168167938
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.488618142
Short name T278
Test name
Test status
Simulation time 142001631315 ps
CPU time 2353.33 seconds
Started Jul 21 06:08:55 PM PDT 24
Finished Jul 21 06:48:09 PM PDT 24
Peak memory 289540 kb
Host smart-0a66060a-20df-4838-b20d-769991e32ea1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488618142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_han
dler_stress_all.488618142
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.785387283
Short name T261
Test name
Test status
Simulation time 15763031856 ps
CPU time 900.22 seconds
Started Jul 21 06:08:56 PM PDT 24
Finished Jul 21 06:23:57 PM PDT 24
Peak memory 271440 kb
Host smart-82c771a3-1652-4edf-857c-fb06212d78dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785387283 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.785387283
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2754347493
Short name T199
Test name
Test status
Simulation time 57717744 ps
CPU time 3.26 seconds
Started Jul 21 06:07:33 PM PDT 24
Finished Jul 21 06:07:37 PM PDT 24
Peak memory 249200 kb
Host smart-6638f0cc-7c32-48de-9655-ef6e493b6ef9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2754347493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2754347493
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3637248193
Short name T528
Test name
Test status
Simulation time 586547758 ps
CPU time 16.07 seconds
Started Jul 21 06:07:38 PM PDT 24
Finished Jul 21 06:07:54 PM PDT 24
Peak memory 249068 kb
Host smart-c2615ae2-418f-4af5-8034-8912e1660300
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3637248193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3637248193
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2657212928
Short name T582
Test name
Test status
Simulation time 206949589 ps
CPU time 14.7 seconds
Started Jul 21 06:07:33 PM PDT 24
Finished Jul 21 06:07:48 PM PDT 24
Peak memory 248504 kb
Host smart-78560a11-7aa9-4dc0-bf1a-6e591dd20cd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26572
12928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2657212928
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.3421527191
Short name T426
Test name
Test status
Simulation time 805393623 ps
CPU time 19.71 seconds
Started Jul 21 06:07:29 PM PDT 24
Finished Jul 21 06:07:49 PM PDT 24
Peak memory 256308 kb
Host smart-3c350c84-d118-4485-b25f-4dcbd90dcb47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34215
27191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3421527191
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.4239687171
Short name T353
Test name
Test status
Simulation time 373890181559 ps
CPU time 2952.09 seconds
Started Jul 21 06:07:38 PM PDT 24
Finished Jul 21 06:56:51 PM PDT 24
Peak memory 289644 kb
Host smart-389bf925-499c-4780-9456-62b8fa8bbd2c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239687171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.4239687171
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1169646622
Short name T444
Test name
Test status
Simulation time 8660050146 ps
CPU time 763.34 seconds
Started Jul 21 06:07:33 PM PDT 24
Finished Jul 21 06:20:17 PM PDT 24
Peak memory 273368 kb
Host smart-c2111afd-539c-44a9-86e1-40f46aa5c074
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169646622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1169646622
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1195100568
Short name T530
Test name
Test status
Simulation time 1736900120 ps
CPU time 29.29 seconds
Started Jul 21 06:07:32 PM PDT 24
Finished Jul 21 06:08:02 PM PDT 24
Peak memory 257184 kb
Host smart-cf881d59-854f-4c6f-a224-01bcc187b616
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11951
00568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1195100568
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.281194871
Short name T651
Test name
Test status
Simulation time 53406881 ps
CPU time 4.35 seconds
Started Jul 21 06:07:32 PM PDT 24
Finished Jul 21 06:07:37 PM PDT 24
Peak memory 249368 kb
Host smart-6d007a7c-b76f-4105-89d2-fcbe2bef06a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28119
4871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.281194871
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.3807092016
Short name T11
Test name
Test status
Simulation time 1674384482 ps
CPU time 23.51 seconds
Started Jul 21 06:07:38 PM PDT 24
Finished Jul 21 06:08:02 PM PDT 24
Peak memory 271576 kb
Host smart-16832334-3c71-45a8-b018-986d5421f7c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3807092016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3807092016
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.3489633077
Short name T54
Test name
Test status
Simulation time 232717404 ps
CPU time 31.79 seconds
Started Jul 21 06:07:36 PM PDT 24
Finished Jul 21 06:08:08 PM PDT 24
Peak memory 249096 kb
Host smart-854d1fdf-90eb-47d8-9131-1b7eddf99c01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34896
33077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3489633077
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.367353659
Short name T677
Test name
Test status
Simulation time 1589199791 ps
CPU time 44.7 seconds
Started Jul 21 06:07:28 PM PDT 24
Finished Jul 21 06:08:13 PM PDT 24
Peak memory 256676 kb
Host smart-fdf1385a-9881-4b58-93e3-3dd805f267c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36735
3659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.367353659
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.403864432
Short name T562
Test name
Test status
Simulation time 71033401735 ps
CPU time 2292.73 seconds
Started Jul 21 06:09:01 PM PDT 24
Finished Jul 21 06:47:14 PM PDT 24
Peak memory 273428 kb
Host smart-47556cc3-da1e-4bcc-8303-bc1f9f7f3cd1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403864432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.403864432
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.3372234420
Short name T368
Test name
Test status
Simulation time 1474804844 ps
CPU time 39.41 seconds
Started Jul 21 06:08:55 PM PDT 24
Finished Jul 21 06:09:34 PM PDT 24
Peak memory 248912 kb
Host smart-d29d901c-7c07-4f8e-827d-afb3548652a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33722
34420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.3372234420
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.963803678
Short name T583
Test name
Test status
Simulation time 123122790 ps
CPU time 7.71 seconds
Started Jul 21 06:08:58 PM PDT 24
Finished Jul 21 06:09:06 PM PDT 24
Peak memory 248956 kb
Host smart-28a3a9ea-2233-4e4b-9bce-620f8fc3c98b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96380
3678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.963803678
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.3015155043
Short name T592
Test name
Test status
Simulation time 32852878054 ps
CPU time 1747.88 seconds
Started Jul 21 06:09:01 PM PDT 24
Finished Jul 21 06:38:09 PM PDT 24
Peak memory 273596 kb
Host smart-0b5f2e65-62ef-4530-8d31-a73437179a39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015155043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.3015155043
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.1385410776
Short name T392
Test name
Test status
Simulation time 8255446905 ps
CPU time 912.16 seconds
Started Jul 21 06:09:02 PM PDT 24
Finished Jul 21 06:24:15 PM PDT 24
Peak memory 273816 kb
Host smart-56dba956-f70f-4262-bdb8-74a05d027c16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385410776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.1385410776
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.258204448
Short name T307
Test name
Test status
Simulation time 955695615 ps
CPU time 24.47 seconds
Started Jul 21 06:09:02 PM PDT 24
Finished Jul 21 06:09:27 PM PDT 24
Peak memory 256416 kb
Host smart-a04d3ec4-f748-4d15-a996-8c79958bf789
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25820
4448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.258204448
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.3320476676
Short name T237
Test name
Test status
Simulation time 599857332 ps
CPU time 8.87 seconds
Started Jul 21 06:08:57 PM PDT 24
Finished Jul 21 06:09:07 PM PDT 24
Peak memory 249320 kb
Host smart-274b3d23-0e8c-4434-8c60-fcb77c3cf855
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33204
76676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.3320476676
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1110243126
Short name T310
Test name
Test status
Simulation time 180195598 ps
CPU time 18.4 seconds
Started Jul 21 06:08:58 PM PDT 24
Finished Jul 21 06:09:17 PM PDT 24
Peak memory 249160 kb
Host smart-60b2c8ca-ffe2-4248-8b6f-331825b399ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11102
43126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1110243126
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1791147356
Short name T545
Test name
Test status
Simulation time 809159862 ps
CPU time 56.08 seconds
Started Jul 21 06:09:01 PM PDT 24
Finished Jul 21 06:09:58 PM PDT 24
Peak memory 256552 kb
Host smart-ca737980-4acb-43ed-99c2-e7460c8357f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17911
47356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1791147356
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.136253817
Short name T299
Test name
Test status
Simulation time 224383074534 ps
CPU time 3328.36 seconds
Started Jul 21 06:09:00 PM PDT 24
Finished Jul 21 07:04:29 PM PDT 24
Peak memory 298820 kb
Host smart-88319404-af50-42cf-8be3-ff84bf9ba4d9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136253817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_han
dler_stress_all.136253817
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3043938494
Short name T110
Test name
Test status
Simulation time 43984868571 ps
CPU time 1209.21 seconds
Started Jul 21 06:09:01 PM PDT 24
Finished Jul 21 06:29:11 PM PDT 24
Peak memory 281344 kb
Host smart-d3a1d5c5-b0d2-434d-ae48-3b2313ade9a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043938494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3043938494
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.339963770
Short name T379
Test name
Test status
Simulation time 18768058879 ps
CPU time 251.01 seconds
Started Jul 21 06:09:02 PM PDT 24
Finished Jul 21 06:13:13 PM PDT 24
Peak memory 257280 kb
Host smart-f8497ccf-817b-4498-8134-d012c7b6d70d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33996
3770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.339963770
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.364627683
Short name T597
Test name
Test status
Simulation time 1924180138 ps
CPU time 32.84 seconds
Started Jul 21 06:09:01 PM PDT 24
Finished Jul 21 06:09:35 PM PDT 24
Peak memory 248464 kb
Host smart-bc19b73f-791c-4ad4-b968-ed5c4d36534a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36462
7683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.364627683
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.2240276755
Short name T320
Test name
Test status
Simulation time 64110311905 ps
CPU time 1326.95 seconds
Started Jul 21 06:09:01 PM PDT 24
Finished Jul 21 06:31:09 PM PDT 24
Peak memory 289648 kb
Host smart-63721d14-e044-4e19-b719-7b73627cc79c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240276755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2240276755
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.2566415040
Short name T255
Test name
Test status
Simulation time 74151681072 ps
CPU time 1556.81 seconds
Started Jul 21 06:09:07 PM PDT 24
Finished Jul 21 06:35:04 PM PDT 24
Peak memory 289876 kb
Host smart-2bf20dd8-c52c-467e-ad44-eed2a8eca1a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2566415040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.2566415040
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2598112169
Short name T624
Test name
Test status
Simulation time 54875467 ps
CPU time 6.84 seconds
Started Jul 21 06:09:01 PM PDT 24
Finished Jul 21 06:09:08 PM PDT 24
Peak memory 248988 kb
Host smart-20a7151a-cdb5-4977-ab53-0a86ba242bea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25981
12169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2598112169
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2562043326
Short name T387
Test name
Test status
Simulation time 376881119 ps
CPU time 40.09 seconds
Started Jul 21 06:09:03 PM PDT 24
Finished Jul 21 06:09:44 PM PDT 24
Peak memory 257224 kb
Host smart-db0b815b-364f-4227-ad05-b0d69ed9848b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25620
43326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2562043326
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3746415219
Short name T660
Test name
Test status
Simulation time 999290026 ps
CPU time 31.3 seconds
Started Jul 21 06:09:02 PM PDT 24
Finished Jul 21 06:09:34 PM PDT 24
Peak memory 257172 kb
Host smart-4d935c79-7d21-4e4b-a603-51809145e11b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37464
15219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3746415219
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.3565999208
Short name T590
Test name
Test status
Simulation time 310401951 ps
CPU time 27.09 seconds
Started Jul 21 06:09:02 PM PDT 24
Finished Jul 21 06:09:29 PM PDT 24
Peak memory 256648 kb
Host smart-77c2a3cf-e580-42c6-99b5-3c8c2c9d2434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35659
99208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.3565999208
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2227503893
Short name T497
Test name
Test status
Simulation time 514924201655 ps
CPU time 4040.75 seconds
Started Jul 21 06:09:10 PM PDT 24
Finished Jul 21 07:16:32 PM PDT 24
Peak memory 298516 kb
Host smart-d168f4d5-9425-4fcd-aa0b-b35f04820aca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227503893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2227503893
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.396231904
Short name T59
Test name
Test status
Simulation time 159220342534 ps
CPU time 4149.28 seconds
Started Jul 21 06:09:07 PM PDT 24
Finished Jul 21 07:18:17 PM PDT 24
Peak memory 338676 kb
Host smart-30306c5a-2556-4f52-849f-5a63cfc66102
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396231904 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.396231904
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.191616948
Short name T60
Test name
Test status
Simulation time 61908360815 ps
CPU time 1870.14 seconds
Started Jul 21 06:09:13 PM PDT 24
Finished Jul 21 06:40:23 PM PDT 24
Peak memory 289132 kb
Host smart-13cc27cb-2150-445e-8a85-80e10f04bf26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191616948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.191616948
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2653453435
Short name T500
Test name
Test status
Simulation time 980365674 ps
CPU time 40.13 seconds
Started Jul 21 06:09:11 PM PDT 24
Finished Jul 21 06:09:52 PM PDT 24
Peak memory 257304 kb
Host smart-1fc22ae7-d198-4a51-9df9-68992fabaed7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26534
53435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2653453435
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2092590301
Short name T103
Test name
Test status
Simulation time 1224091342 ps
CPU time 19.57 seconds
Started Jul 21 06:09:08 PM PDT 24
Finished Jul 21 06:09:28 PM PDT 24
Peak memory 249448 kb
Host smart-9b048667-7748-40e5-b314-3aec63a3056e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20925
90301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2092590301
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.658941024
Short name T349
Test name
Test status
Simulation time 374835652491 ps
CPU time 1314.39 seconds
Started Jul 21 06:09:08 PM PDT 24
Finished Jul 21 06:31:02 PM PDT 24
Peak memory 273044 kb
Host smart-8ee6834c-0aed-4799-b138-a17451a4c5b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658941024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.658941024
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3281309015
Short name T257
Test name
Test status
Simulation time 70356446768 ps
CPU time 2243.98 seconds
Started Jul 21 06:09:08 PM PDT 24
Finished Jul 21 06:46:33 PM PDT 24
Peak memory 273468 kb
Host smart-f72440d3-b923-4201-a096-d31d21bfa435
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281309015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3281309015
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1866916886
Short name T317
Test name
Test status
Simulation time 39694102889 ps
CPU time 271.75 seconds
Started Jul 21 06:09:11 PM PDT 24
Finished Jul 21 06:13:43 PM PDT 24
Peak memory 254820 kb
Host smart-f6c2c13b-bb8b-4571-92ce-2a75c4b4eb1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866916886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1866916886
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.1961559761
Short name T458
Test name
Test status
Simulation time 1266637558 ps
CPU time 33.14 seconds
Started Jul 21 06:09:07 PM PDT 24
Finished Jul 21 06:09:41 PM PDT 24
Peak memory 257056 kb
Host smart-ff7e2fdf-06c4-4998-9690-b011ed8acf01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19615
59761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1961559761
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.1190970628
Short name T470
Test name
Test status
Simulation time 1994453412 ps
CPU time 47.17 seconds
Started Jul 21 06:09:09 PM PDT 24
Finished Jul 21 06:09:56 PM PDT 24
Peak memory 248536 kb
Host smart-68264fbc-c36f-46c2-b412-2da9a10bd4bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11909
70628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.1190970628
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3940660684
Short name T92
Test name
Test status
Simulation time 170146077 ps
CPU time 6.98 seconds
Started Jul 21 06:09:08 PM PDT 24
Finished Jul 21 06:09:16 PM PDT 24
Peak memory 248504 kb
Host smart-9f5af578-834d-428f-b291-755553149a63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39406
60684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3940660684
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.910069736
Short name T390
Test name
Test status
Simulation time 577092163 ps
CPU time 17.87 seconds
Started Jul 21 06:09:08 PM PDT 24
Finished Jul 21 06:09:27 PM PDT 24
Peak memory 254608 kb
Host smart-17f51cb7-8cb2-4f1b-87a2-9b2488a2eb0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91006
9736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.910069736
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3240370326
Short name T114
Test name
Test status
Simulation time 9178800921 ps
CPU time 1052.22 seconds
Started Jul 21 06:09:09 PM PDT 24
Finished Jul 21 06:26:42 PM PDT 24
Peak memory 289924 kb
Host smart-eb3e103c-07a8-432a-8d27-370324fce170
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240370326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3240370326
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.1108129253
Short name T183
Test name
Test status
Simulation time 377692412508 ps
CPU time 8600.42 seconds
Started Jul 21 06:09:06 PM PDT 24
Finished Jul 21 08:32:28 PM PDT 24
Peak memory 338160 kb
Host smart-69d22fbb-b086-463d-a18d-fe993db94276
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108129253 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.1108129253
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.3487458329
Short name T407
Test name
Test status
Simulation time 19612718689 ps
CPU time 1141.33 seconds
Started Jul 21 06:09:06 PM PDT 24
Finished Jul 21 06:28:08 PM PDT 24
Peak memory 272172 kb
Host smart-b499d828-4b34-45b1-b7c8-9bdef98cf461
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487458329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.3487458329
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3606768554
Short name T516
Test name
Test status
Simulation time 3192789524 ps
CPU time 181.81 seconds
Started Jul 21 06:09:08 PM PDT 24
Finished Jul 21 06:12:11 PM PDT 24
Peak memory 251192 kb
Host smart-4eac6d9b-33af-4394-af6a-c6c7c1e5956e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36067
68554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3606768554
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.329160470
Short name T85
Test name
Test status
Simulation time 2404951687 ps
CPU time 69.28 seconds
Started Jul 21 06:09:09 PM PDT 24
Finished Jul 21 06:10:19 PM PDT 24
Peak memory 250064 kb
Host smart-d78d35d6-84cd-4856-9619-941bb7587466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32916
0470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.329160470
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3423912313
Short name T336
Test name
Test status
Simulation time 480147732311 ps
CPU time 2265.37 seconds
Started Jul 21 06:09:15 PM PDT 24
Finished Jul 21 06:47:01 PM PDT 24
Peak memory 289676 kb
Host smart-66544a09-e03a-49af-82d7-473bc40cac44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423912313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3423912313
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2329313679
Short name T704
Test name
Test status
Simulation time 138721431588 ps
CPU time 2289.63 seconds
Started Jul 21 06:09:13 PM PDT 24
Finished Jul 21 06:47:23 PM PDT 24
Peak memory 281768 kb
Host smart-51a49fe8-6862-47e0-b918-455f2c8b2817
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329313679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2329313679
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.2608814356
Short name T69
Test name
Test status
Simulation time 51498513096 ps
CPU time 541.11 seconds
Started Jul 21 06:09:09 PM PDT 24
Finished Jul 21 06:18:11 PM PDT 24
Peak memory 249112 kb
Host smart-66687b56-dd32-4104-8282-e46e868430bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608814356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2608814356
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.814045276
Short name T201
Test name
Test status
Simulation time 663474174 ps
CPU time 45.38 seconds
Started Jul 21 06:09:09 PM PDT 24
Finished Jul 21 06:09:55 PM PDT 24
Peak memory 256368 kb
Host smart-c5016d2a-f9b4-4fa0-9287-3575e7c014a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81404
5276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.814045276
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3964965730
Short name T537
Test name
Test status
Simulation time 582799212 ps
CPU time 35.34 seconds
Started Jul 21 06:09:10 PM PDT 24
Finished Jul 21 06:09:46 PM PDT 24
Peak memory 248856 kb
Host smart-84d0dbbf-2cf9-481f-be26-15073a0d7327
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39649
65730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3964965730
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.16699705
Short name T453
Test name
Test status
Simulation time 140656231 ps
CPU time 17.5 seconds
Started Jul 21 06:09:12 PM PDT 24
Finished Jul 21 06:09:30 PM PDT 24
Peak memory 256460 kb
Host smart-67cb8de8-6c6d-44b8-b363-93ae60f4f293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16699
705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.16699705
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.1360515212
Short name T514
Test name
Test status
Simulation time 795116338 ps
CPU time 44.51 seconds
Started Jul 21 06:09:10 PM PDT 24
Finished Jul 21 06:09:55 PM PDT 24
Peak memory 248876 kb
Host smart-f290d1c5-4db9-4349-ae48-4816ec8d824d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13605
15212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.1360515212
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.3409804390
Short name T267
Test name
Test status
Simulation time 28327941830 ps
CPU time 2952.11 seconds
Started Jul 21 06:09:13 PM PDT 24
Finished Jul 21 06:58:26 PM PDT 24
Peak memory 322928 kb
Host smart-518971ef-cf17-4049-9ad1-2640fc1df683
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409804390 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.3409804390
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.4169279473
Short name T644
Test name
Test status
Simulation time 88551490004 ps
CPU time 2642.53 seconds
Started Jul 21 06:09:16 PM PDT 24
Finished Jul 21 06:53:19 PM PDT 24
Peak memory 284536 kb
Host smart-d251727c-fd25-44bb-aa1d-1040555edbc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169279473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.4169279473
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1373485259
Short name T374
Test name
Test status
Simulation time 17092188447 ps
CPU time 223.68 seconds
Started Jul 21 06:09:15 PM PDT 24
Finished Jul 21 06:13:00 PM PDT 24
Peak memory 257284 kb
Host smart-8a7caccd-888b-4c47-9d24-a30edd8147bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13734
85259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1373485259
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2062610547
Short name T376
Test name
Test status
Simulation time 116144741 ps
CPU time 4.68 seconds
Started Jul 21 06:09:15 PM PDT 24
Finished Jul 21 06:09:20 PM PDT 24
Peak memory 248884 kb
Host smart-f418dc7b-d2f4-4d01-9ba5-ff91badafa0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20626
10547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2062610547
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.3349555413
Short name T200
Test name
Test status
Simulation time 14950643096 ps
CPU time 1487.34 seconds
Started Jul 21 06:09:21 PM PDT 24
Finished Jul 21 06:34:09 PM PDT 24
Peak memory 289208 kb
Host smart-80cd8d05-df70-42d9-a291-f509d75fd816
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349555413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.3349555413
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.3994633015
Short name T26
Test name
Test status
Simulation time 31252401100 ps
CPU time 1002.89 seconds
Started Jul 21 06:09:22 PM PDT 24
Finished Jul 21 06:26:05 PM PDT 24
Peak memory 273312 kb
Host smart-c7f39a77-9a86-45e4-9284-1f13063fd8f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994633015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3994633015
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2849092211
Short name T9
Test name
Test status
Simulation time 2009768692 ps
CPU time 84.07 seconds
Started Jul 21 06:09:15 PM PDT 24
Finished Jul 21 06:10:40 PM PDT 24
Peak memory 247932 kb
Host smart-a4bcd5dc-a368-4baa-8e3b-a5a689f5307e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849092211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2849092211
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.3607342306
Short name T419
Test name
Test status
Simulation time 202326478 ps
CPU time 11.95 seconds
Started Jul 21 06:09:13 PM PDT 24
Finished Jul 21 06:09:25 PM PDT 24
Peak memory 248960 kb
Host smart-126552f7-20e3-4c2c-9881-48cc96629eb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36073
42306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3607342306
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.497828404
Short name T1
Test name
Test status
Simulation time 600608180 ps
CPU time 25.26 seconds
Started Jul 21 06:09:17 PM PDT 24
Finished Jul 21 06:09:42 PM PDT 24
Peak memory 249336 kb
Host smart-13aaefd0-701c-4543-b6f4-6478235095a7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49782
8404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.497828404
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1298147185
Short name T649
Test name
Test status
Simulation time 360029000 ps
CPU time 24.3 seconds
Started Jul 21 06:09:12 PM PDT 24
Finished Jul 21 06:09:36 PM PDT 24
Peak memory 248884 kb
Host smart-47e770ac-5e8f-481f-a706-944a78938458
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12981
47185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1298147185
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.2309259477
Short name T416
Test name
Test status
Simulation time 1098766034 ps
CPU time 71.1 seconds
Started Jul 21 06:09:14 PM PDT 24
Finished Jul 21 06:10:25 PM PDT 24
Peak memory 257140 kb
Host smart-902ff876-5ee4-4149-b38e-510c490c01aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23092
59477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.2309259477
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1967130336
Short name T580
Test name
Test status
Simulation time 1188668429 ps
CPU time 143.2 seconds
Started Jul 21 06:09:23 PM PDT 24
Finished Jul 21 06:11:47 PM PDT 24
Peak memory 257216 kb
Host smart-e6850363-4677-4be9-b268-ba3a7d810d41
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967130336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1967130336
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.123811630
Short name T55
Test name
Test status
Simulation time 58979607260 ps
CPU time 3453.7 seconds
Started Jul 21 06:09:23 PM PDT 24
Finished Jul 21 07:06:58 PM PDT 24
Peak memory 289796 kb
Host smart-d564eb61-93b7-4b3a-96a0-75f21db046c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=123811630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.123811630
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.2150283870
Short name T394
Test name
Test status
Simulation time 883182486 ps
CPU time 59.88 seconds
Started Jul 21 06:09:22 PM PDT 24
Finished Jul 21 06:10:23 PM PDT 24
Peak memory 256732 kb
Host smart-5e08784a-866c-42d2-b2d6-4b2dd0588207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21502
83870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.2150283870
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.460118242
Short name T618
Test name
Test status
Simulation time 290613901 ps
CPU time 27.41 seconds
Started Jul 21 06:09:27 PM PDT 24
Finished Jul 21 06:09:55 PM PDT 24
Peak memory 256472 kb
Host smart-ec44a30e-7c4c-4dca-a37a-01c5be3161b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46011
8242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.460118242
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3869251389
Short name T542
Test name
Test status
Simulation time 157571227150 ps
CPU time 2189.76 seconds
Started Jul 21 06:09:23 PM PDT 24
Finished Jul 21 06:45:53 PM PDT 24
Peak memory 290092 kb
Host smart-5f30aa91-7ae9-4e49-bd0b-07362121f388
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869251389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3869251389
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3744207126
Short name T629
Test name
Test status
Simulation time 67898923854 ps
CPU time 2078.77 seconds
Started Jul 21 06:09:23 PM PDT 24
Finished Jul 21 06:44:02 PM PDT 24
Peak memory 287908 kb
Host smart-382604aa-2900-4e37-a29f-20d2f845d767
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744207126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3744207126
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.2340144294
Short name T323
Test name
Test status
Simulation time 15083510973 ps
CPU time 627.08 seconds
Started Jul 21 06:09:24 PM PDT 24
Finished Jul 21 06:19:51 PM PDT 24
Peak memory 249144 kb
Host smart-b3d380c2-8940-404e-afac-0f3930a2537b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340144294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2340144294
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3980454145
Short name T614
Test name
Test status
Simulation time 933179607 ps
CPU time 51.77 seconds
Started Jul 21 06:09:23 PM PDT 24
Finished Jul 21 06:10:15 PM PDT 24
Peak memory 256484 kb
Host smart-9375af37-ebea-4b93-baf5-ad88c8159900
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39804
54145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3980454145
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.3955803888
Short name T670
Test name
Test status
Simulation time 519965313 ps
CPU time 28.01 seconds
Started Jul 21 06:09:24 PM PDT 24
Finished Jul 21 06:09:52 PM PDT 24
Peak memory 256204 kb
Host smart-f157f5d4-33a7-4ce5-a812-badb38dac0e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39558
03888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.3955803888
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1182984617
Short name T260
Test name
Test status
Simulation time 84484938 ps
CPU time 6.48 seconds
Started Jul 21 06:09:21 PM PDT 24
Finished Jul 21 06:09:28 PM PDT 24
Peak memory 253748 kb
Host smart-d2201505-73c9-4aa5-8e3c-0261bbc83fc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11829
84617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1182984617
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2563468659
Short name T441
Test name
Test status
Simulation time 864740956 ps
CPU time 24.17 seconds
Started Jul 21 06:09:22 PM PDT 24
Finished Jul 21 06:09:46 PM PDT 24
Peak memory 257088 kb
Host smart-50b6dd40-6f97-4e8b-8725-481ecda5cc3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25634
68659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2563468659
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.4215827038
Short name T305
Test name
Test status
Simulation time 32598618208 ps
CPU time 3053.61 seconds
Started Jul 21 06:09:27 PM PDT 24
Finished Jul 21 07:00:22 PM PDT 24
Peak memory 289896 kb
Host smart-2fb37d2e-b8f8-451c-8367-8d05c8da0761
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215827038 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.4215827038
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.2917645102
Short name T491
Test name
Test status
Simulation time 58934150541 ps
CPU time 1057.67 seconds
Started Jul 21 06:09:25 PM PDT 24
Finished Jul 21 06:27:04 PM PDT 24
Peak memory 273196 kb
Host smart-bbda66a7-1e31-434f-8ea2-4bede0e0d02e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917645102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.2917645102
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.865369775
Short name T628
Test name
Test status
Simulation time 498542180 ps
CPU time 14.45 seconds
Started Jul 21 06:09:29 PM PDT 24
Finished Jul 21 06:09:43 PM PDT 24
Peak memory 248528 kb
Host smart-779b1ea1-a677-445f-9ff0-877d8e4b5a2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86536
9775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.865369775
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.26984015
Short name T675
Test name
Test status
Simulation time 5624847436 ps
CPU time 40.33 seconds
Started Jul 21 06:09:28 PM PDT 24
Finished Jul 21 06:10:09 PM PDT 24
Peak memory 257064 kb
Host smart-29272431-f5cb-46bd-8812-545d598fc84a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26984
015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.26984015
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.3574641019
Short name T518
Test name
Test status
Simulation time 59041154544 ps
CPU time 1726.92 seconds
Started Jul 21 06:09:32 PM PDT 24
Finished Jul 21 06:38:19 PM PDT 24
Peak memory 273680 kb
Host smart-46e8e0cc-c9d5-4753-a872-dc545607792b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574641019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3574641019
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.1066451841
Short name T672
Test name
Test status
Simulation time 5995033575 ps
CPU time 600.99 seconds
Started Jul 21 06:09:27 PM PDT 24
Finished Jul 21 06:19:29 PM PDT 24
Peak memory 266544 kb
Host smart-c579711c-a419-4897-b849-0d3c861068a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066451841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.1066451841
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2981470651
Short name T314
Test name
Test status
Simulation time 5237257628 ps
CPU time 127.74 seconds
Started Jul 21 06:09:29 PM PDT 24
Finished Jul 21 06:11:37 PM PDT 24
Peak memory 256340 kb
Host smart-f363d65a-c4d8-4168-9ad0-cdcd827e5616
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981470651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2981470651
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.217663021
Short name T560
Test name
Test status
Simulation time 625909136 ps
CPU time 32.49 seconds
Started Jul 21 06:09:27 PM PDT 24
Finished Jul 21 06:10:00 PM PDT 24
Peak memory 256240 kb
Host smart-b224c6b5-34f9-4ed9-b784-3d8fa36562b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21766
3021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.217663021
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.639746857
Short name T116
Test name
Test status
Simulation time 743813977 ps
CPU time 36.48 seconds
Started Jul 21 06:09:26 PM PDT 24
Finished Jul 21 06:10:03 PM PDT 24
Peak memory 248640 kb
Host smart-abf0bfcb-a565-4649-a11f-6aa8e4d42b36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63974
6857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.639746857
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1562106155
Short name T503
Test name
Test status
Simulation time 96738904 ps
CPU time 4.57 seconds
Started Jul 21 06:09:27 PM PDT 24
Finished Jul 21 06:09:32 PM PDT 24
Peak memory 240128 kb
Host smart-649b00b5-8508-450b-9504-c49c9af09dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15621
06155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1562106155
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2861122688
Short name T382
Test name
Test status
Simulation time 2343891060 ps
CPU time 44.55 seconds
Started Jul 21 06:09:26 PM PDT 24
Finished Jul 21 06:10:11 PM PDT 24
Peak memory 249184 kb
Host smart-a2427f10-66c8-4a96-913a-ccc0bdc9c8cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28611
22688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2861122688
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2597936629
Short name T187
Test name
Test status
Simulation time 65372927263 ps
CPU time 3522.2 seconds
Started Jul 21 06:09:25 PM PDT 24
Finished Jul 21 07:08:08 PM PDT 24
Peak memory 300300 kb
Host smart-0b771f23-25ce-46b1-86f2-77ac32549715
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597936629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2597936629
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.620515685
Short name T506
Test name
Test status
Simulation time 121139838967 ps
CPU time 3175.31 seconds
Started Jul 21 06:09:26 PM PDT 24
Finished Jul 21 07:02:22 PM PDT 24
Peak memory 289848 kb
Host smart-8bced0da-b53e-4123-b554-c768dafd962d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620515685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.620515685
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.1105342301
Short name T617
Test name
Test status
Simulation time 10104495713 ps
CPU time 201.51 seconds
Started Jul 21 06:09:29 PM PDT 24
Finished Jul 21 06:12:51 PM PDT 24
Peak memory 256792 kb
Host smart-8998161d-f6fe-415e-bd1b-f9b415d1ed8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11053
42301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1105342301
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1186599372
Short name T437
Test name
Test status
Simulation time 529532332 ps
CPU time 32.6 seconds
Started Jul 21 06:09:26 PM PDT 24
Finished Jul 21 06:09:59 PM PDT 24
Peak memory 248884 kb
Host smart-725670b7-3a3f-4cdd-baca-5f3fc58935c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11865
99372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1186599372
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3186507212
Short name T355
Test name
Test status
Simulation time 441243195810 ps
CPU time 3087.52 seconds
Started Jul 21 06:09:30 PM PDT 24
Finished Jul 21 07:00:58 PM PDT 24
Peak memory 290000 kb
Host smart-6672f2ac-5559-474b-bff8-079fd1f96fbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186507212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3186507212
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.806062023
Short name T591
Test name
Test status
Simulation time 34182370915 ps
CPU time 2127.18 seconds
Started Jul 21 06:09:28 PM PDT 24
Finished Jul 21 06:44:56 PM PDT 24
Peak memory 288260 kb
Host smart-83f373ed-7264-4bbd-a2f8-ab6e15f67dc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806062023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.806062023
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.167194235
Short name T659
Test name
Test status
Simulation time 5176111119 ps
CPU time 101.29 seconds
Started Jul 21 06:09:26 PM PDT 24
Finished Jul 21 06:11:08 PM PDT 24
Peak memory 249088 kb
Host smart-ead12fe3-a979-4aea-a27a-d0a3bad57d2c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167194235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.167194235
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1111123043
Short name T602
Test name
Test status
Simulation time 128719566 ps
CPU time 4.21 seconds
Started Jul 21 06:09:25 PM PDT 24
Finished Jul 21 06:09:29 PM PDT 24
Peak memory 249028 kb
Host smart-1e9a078d-838f-40f2-a697-fbc56cbfda25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11111
23043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1111123043
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.1586278855
Short name T658
Test name
Test status
Simulation time 882609467 ps
CPU time 18.85 seconds
Started Jul 21 06:09:26 PM PDT 24
Finished Jul 21 06:09:46 PM PDT 24
Peak memory 249000 kb
Host smart-222b494c-97a6-49bc-9542-badbf951e52a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15862
78855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1586278855
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.2557522992
Short name T564
Test name
Test status
Simulation time 2002567927 ps
CPU time 39.82 seconds
Started Jul 21 06:09:26 PM PDT 24
Finished Jul 21 06:10:06 PM PDT 24
Peak memory 256872 kb
Host smart-eb2a2636-3b7f-48b1-be5e-7ebae0b428ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25575
22992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2557522992
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.63055163
Short name T48
Test name
Test status
Simulation time 445162057 ps
CPU time 49.99 seconds
Started Jul 21 06:09:28 PM PDT 24
Finished Jul 21 06:10:18 PM PDT 24
Peak memory 257192 kb
Host smart-e2b8047c-2747-41ec-9425-ff252ab99c30
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63055163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_hand
ler_stress_all.63055163
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.2183874418
Short name T476
Test name
Test status
Simulation time 19837232676 ps
CPU time 1416.2 seconds
Started Jul 21 06:09:25 PM PDT 24
Finished Jul 21 06:33:02 PM PDT 24
Peak memory 284224 kb
Host smart-27b59db7-1aa3-40db-bda2-2d7a1af7084f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183874418 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.2183874418
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2678785923
Short name T90
Test name
Test status
Simulation time 245992625515 ps
CPU time 3507.85 seconds
Started Jul 21 06:09:35 PM PDT 24
Finished Jul 21 07:08:04 PM PDT 24
Peak memory 289768 kb
Host smart-7b1ffb27-099d-4162-8023-6bd354c224b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678785923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2678785923
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1390237055
Short name T446
Test name
Test status
Simulation time 7889891320 ps
CPU time 187.85 seconds
Started Jul 21 06:09:32 PM PDT 24
Finished Jul 21 06:12:41 PM PDT 24
Peak memory 256864 kb
Host smart-8b808a26-5a0a-4414-8195-b586601d54f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13902
37055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1390237055
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.1005750039
Short name T88
Test name
Test status
Simulation time 93433078 ps
CPU time 8.46 seconds
Started Jul 21 06:09:35 PM PDT 24
Finished Jul 21 06:09:44 PM PDT 24
Peak memory 248512 kb
Host smart-90d7a136-28c9-4b23-bd1d-2aa60dcea824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10057
50039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1005750039
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3460525206
Short name T330
Test name
Test status
Simulation time 13219208919 ps
CPU time 1113.72 seconds
Started Jul 21 06:09:34 PM PDT 24
Finished Jul 21 06:28:09 PM PDT 24
Peak memory 273696 kb
Host smart-2d53f40c-268c-4d98-8d51-6a4991a9978b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460525206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3460525206
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2005051137
Short name T297
Test name
Test status
Simulation time 54227110905 ps
CPU time 1672.13 seconds
Started Jul 21 06:09:32 PM PDT 24
Finished Jul 21 06:37:25 PM PDT 24
Peak memory 265528 kb
Host smart-7ca01f34-4573-4c42-8850-eb92ae41b927
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005051137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2005051137
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1698811372
Short name T326
Test name
Test status
Simulation time 13484218254 ps
CPU time 289.37 seconds
Started Jul 21 06:09:35 PM PDT 24
Finished Jul 21 06:14:25 PM PDT 24
Peak memory 249108 kb
Host smart-f1aa5fd0-72fa-4cbc-9e0f-fdcb95708eb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698811372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1698811372
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1870731057
Short name T515
Test name
Test status
Simulation time 4528448737 ps
CPU time 23.72 seconds
Started Jul 21 06:09:34 PM PDT 24
Finished Jul 21 06:09:58 PM PDT 24
Peak memory 256644 kb
Host smart-9e175d58-d0a1-422b-b46e-2ecb2430aabf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18707
31057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1870731057
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.317191466
Short name T550
Test name
Test status
Simulation time 395098194 ps
CPU time 44.72 seconds
Started Jul 21 06:09:36 PM PDT 24
Finished Jul 21 06:10:21 PM PDT 24
Peak memory 250220 kb
Host smart-821c52df-40c5-4fba-92b4-ad17c2883284
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31719
1466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.317191466
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2486368143
Short name T553
Test name
Test status
Simulation time 844898068 ps
CPU time 18.15 seconds
Started Jul 21 06:09:35 PM PDT 24
Finished Jul 21 06:09:53 PM PDT 24
Peak memory 248956 kb
Host smart-13d711e0-d669-4768-a036-7761d3376a0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24863
68143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2486368143
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2399475237
Short name T573
Test name
Test status
Simulation time 931188582 ps
CPU time 70.46 seconds
Started Jul 21 06:09:33 PM PDT 24
Finished Jul 21 06:10:44 PM PDT 24
Peak memory 257232 kb
Host smart-aec479ec-0734-4d2e-ab3e-68c6a3405e91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23994
75237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2399475237
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.192243098
Short name T646
Test name
Test status
Simulation time 2495221164 ps
CPU time 71.19 seconds
Started Jul 21 06:09:33 PM PDT 24
Finished Jul 21 06:10:45 PM PDT 24
Peak memory 256400 kb
Host smart-fb49023d-0a40-4f76-af66-ddcdddc55e07
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192243098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_han
dler_stress_all.192243098
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2259973374
Short name T552
Test name
Test status
Simulation time 47864172678 ps
CPU time 1234.66 seconds
Started Jul 21 06:09:36 PM PDT 24
Finished Jul 21 06:30:11 PM PDT 24
Peak memory 284052 kb
Host smart-a518e190-9700-4a04-b9f2-c7376cd74936
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2259973374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2259973374
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.2646133951
Short name T406
Test name
Test status
Simulation time 2881114417 ps
CPU time 69.84 seconds
Started Jul 21 06:09:36 PM PDT 24
Finished Jul 21 06:10:46 PM PDT 24
Peak memory 256764 kb
Host smart-3ea276a3-9c52-4800-888d-4695fab31200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26461
33951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2646133951
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3111484905
Short name T235
Test name
Test status
Simulation time 392304275 ps
CPU time 23.82 seconds
Started Jul 21 06:09:31 PM PDT 24
Finished Jul 21 06:09:55 PM PDT 24
Peak memory 249396 kb
Host smart-5960956e-93ea-4c50-8bf9-81faf8b51dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31114
84905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3111484905
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.3300601232
Short name T601
Test name
Test status
Simulation time 239234708159 ps
CPU time 1160.72 seconds
Started Jul 21 06:09:33 PM PDT 24
Finished Jul 21 06:28:55 PM PDT 24
Peak memory 265568 kb
Host smart-a5901b26-9e1b-4398-90a0-217e175202f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300601232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3300601232
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.160500581
Short name T418
Test name
Test status
Simulation time 26555390728 ps
CPU time 1492.91 seconds
Started Jul 21 06:09:35 PM PDT 24
Finished Jul 21 06:34:28 PM PDT 24
Peak memory 273588 kb
Host smart-ed73b8e0-8363-452f-b11b-30fb6dc2abd5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160500581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.160500581
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2713704399
Short name T42
Test name
Test status
Simulation time 2397469782 ps
CPU time 57.16 seconds
Started Jul 21 06:09:36 PM PDT 24
Finished Jul 21 06:10:34 PM PDT 24
Peak memory 256740 kb
Host smart-b52c55ec-d036-425d-8961-e83c6b5c6df5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27137
04399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2713704399
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.1596019289
Short name T474
Test name
Test status
Simulation time 198131668 ps
CPU time 19.63 seconds
Started Jul 21 06:09:33 PM PDT 24
Finished Jul 21 06:09:54 PM PDT 24
Peak memory 248504 kb
Host smart-d673cbae-4809-4117-9e02-6de7bcd6479a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15960
19289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1596019289
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.4131320703
Short name T700
Test name
Test status
Simulation time 921347952 ps
CPU time 28.68 seconds
Started Jul 21 06:09:32 PM PDT 24
Finished Jul 21 06:10:01 PM PDT 24
Peak memory 248980 kb
Host smart-dbad59b5-5225-4299-bca7-a6cea1da6490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41313
20703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.4131320703
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.766647308
Short name T544
Test name
Test status
Simulation time 3613496761 ps
CPU time 47.85 seconds
Started Jul 21 06:09:35 PM PDT 24
Finished Jul 21 06:10:23 PM PDT 24
Peak memory 257208 kb
Host smart-ef35c90a-ec1e-4dac-8de9-fc431b8922e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76664
7308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.766647308
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.3227955042
Short name T483
Test name
Test status
Simulation time 84675967341 ps
CPU time 8052.13 seconds
Started Jul 21 06:09:41 PM PDT 24
Finished Jul 21 08:23:54 PM PDT 24
Peak memory 339288 kb
Host smart-489371dd-a6cd-4515-a51a-c2a4201b28c2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227955042 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.3227955042
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.415612278
Short name T225
Test name
Test status
Simulation time 33810445 ps
CPU time 2.29 seconds
Started Jul 21 06:07:32 PM PDT 24
Finished Jul 21 06:07:35 PM PDT 24
Peak memory 249232 kb
Host smart-b941f149-401c-425b-bd42-e7c00744f9e0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=415612278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.415612278
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.595989379
Short name T293
Test name
Test status
Simulation time 47848653822 ps
CPU time 1190.05 seconds
Started Jul 21 06:07:33 PM PDT 24
Finished Jul 21 06:27:23 PM PDT 24
Peak memory 289032 kb
Host smart-9d4d001a-7b42-4897-83b5-71c16c941246
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595989379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.595989379
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1187098225
Short name T708
Test name
Test status
Simulation time 1200145892 ps
CPU time 48.53 seconds
Started Jul 21 06:07:36 PM PDT 24
Finished Jul 21 06:08:25 PM PDT 24
Peak memory 249112 kb
Host smart-9ac3ffb2-7b8e-4eba-b196-e4d434d57dda
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1187098225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1187098225
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.2183706901
Short name T403
Test name
Test status
Simulation time 7678832574 ps
CPU time 146.99 seconds
Started Jul 21 06:07:33 PM PDT 24
Finished Jul 21 06:10:00 PM PDT 24
Peak memory 256672 kb
Host smart-e312164f-6302-4b3a-abe4-d89f4da7c98e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21837
06901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.2183706901
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2103091051
Short name T707
Test name
Test status
Simulation time 220940370 ps
CPU time 4.76 seconds
Started Jul 21 06:07:34 PM PDT 24
Finished Jul 21 06:07:39 PM PDT 24
Peak memory 240032 kb
Host smart-0ffefd51-6500-4722-bc05-36e46dee5020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21030
91051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2103091051
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.3614235074
Short name T442
Test name
Test status
Simulation time 65785292201 ps
CPU time 1012.97 seconds
Started Jul 21 06:07:33 PM PDT 24
Finished Jul 21 06:24:27 PM PDT 24
Peak memory 273612 kb
Host smart-80dd9325-e155-4b21-bd28-ba8b51413b5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614235074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.3614235074
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.3524638744
Short name T620
Test name
Test status
Simulation time 13538498899 ps
CPU time 59.98 seconds
Started Jul 21 06:07:34 PM PDT 24
Finished Jul 21 06:08:34 PM PDT 24
Peak memory 257156 kb
Host smart-6e5e8d0f-26b1-4611-8e9b-a10e34287d52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35246
38744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.3524638744
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.3157643595
Short name T96
Test name
Test status
Simulation time 3211258802 ps
CPU time 46.14 seconds
Started Jul 21 06:07:31 PM PDT 24
Finished Jul 21 06:08:18 PM PDT 24
Peak memory 256676 kb
Host smart-af9dda7e-763c-45b1-aa13-a29683413a8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31576
43595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.3157643595
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.866463667
Short name T31
Test name
Test status
Simulation time 668245334 ps
CPU time 10.87 seconds
Started Jul 21 06:07:40 PM PDT 24
Finished Jul 21 06:07:52 PM PDT 24
Peak memory 273724 kb
Host smart-1f0dbde7-1779-4ce6-a541-11e179ac113e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=866463667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.866463667
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1329508010
Short name T272
Test name
Test status
Simulation time 4486174707 ps
CPU time 47.43 seconds
Started Jul 21 06:07:34 PM PDT 24
Finished Jul 21 06:08:22 PM PDT 24
Peak memory 256324 kb
Host smart-21de2821-61d9-4ada-9bdb-853715387dfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13295
08010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1329508010
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.4152184692
Short name T17
Test name
Test status
Simulation time 612515957 ps
CPU time 24.04 seconds
Started Jul 21 06:07:33 PM PDT 24
Finished Jul 21 06:07:58 PM PDT 24
Peak memory 256272 kb
Host smart-25d5c0c4-ae29-4f55-929a-b66a74bb1a84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41521
84692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.4152184692
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.1167483593
Short name T52
Test name
Test status
Simulation time 116995583310 ps
CPU time 3503.94 seconds
Started Jul 21 06:07:34 PM PDT 24
Finished Jul 21 07:05:59 PM PDT 24
Peak memory 338876 kb
Host smart-7408abbd-97dc-4de2-a80c-ce2824de4d61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167483593 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.1167483593
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1710701765
Short name T53
Test name
Test status
Simulation time 18041664350 ps
CPU time 624.75 seconds
Started Jul 21 06:09:43 PM PDT 24
Finished Jul 21 06:20:08 PM PDT 24
Peak memory 272668 kb
Host smart-b5239876-46f3-4824-9b6d-9c5ac9440cb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710701765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1710701765
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.2144678873
Short name T408
Test name
Test status
Simulation time 13389300816 ps
CPU time 213.15 seconds
Started Jul 21 06:09:39 PM PDT 24
Finished Jul 21 06:13:13 PM PDT 24
Peak memory 257328 kb
Host smart-188c63e7-9bd3-4cb6-b4d7-9587d8691f0d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21446
78873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.2144678873
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.1098128145
Short name T586
Test name
Test status
Simulation time 395687431 ps
CPU time 31.06 seconds
Started Jul 21 06:09:38 PM PDT 24
Finished Jul 21 06:10:10 PM PDT 24
Peak memory 248944 kb
Host smart-e6e29a73-5f45-4987-bfc9-dd1cb9a44c2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10981
28145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1098128145
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1355118979
Short name T247
Test name
Test status
Simulation time 9091114704 ps
CPU time 936.57 seconds
Started Jul 21 06:09:40 PM PDT 24
Finished Jul 21 06:25:17 PM PDT 24
Peak memory 273672 kb
Host smart-82368005-dc1d-4d7b-a946-f770e4e81950
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355118979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1355118979
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.182387280
Short name T64
Test name
Test status
Simulation time 34676893554 ps
CPU time 1851.76 seconds
Started Jul 21 06:09:40 PM PDT 24
Finished Jul 21 06:40:32 PM PDT 24
Peak memory 273536 kb
Host smart-30bd8150-9c57-4cd7-a7ed-30ef7047c2b8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182387280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.182387280
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.1319456265
Short name T566
Test name
Test status
Simulation time 17810381461 ps
CPU time 364.55 seconds
Started Jul 21 06:09:39 PM PDT 24
Finished Jul 21 06:15:44 PM PDT 24
Peak memory 249148 kb
Host smart-c8f1f3b4-4527-4714-ab07-22b05dab1d61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319456265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.1319456265
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.561581404
Short name T432
Test name
Test status
Simulation time 595414123 ps
CPU time 41.43 seconds
Started Jul 21 06:09:41 PM PDT 24
Finished Jul 21 06:10:23 PM PDT 24
Peak memory 248928 kb
Host smart-3f36b664-9ac7-402a-bd40-275e22572b83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56158
1404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.561581404
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.3451922739
Short name T304
Test name
Test status
Simulation time 218165523 ps
CPU time 23.49 seconds
Started Jul 21 06:09:38 PM PDT 24
Finished Jul 21 06:10:02 PM PDT 24
Peak memory 248620 kb
Host smart-40bf3c19-e48a-43c5-877e-30a8d99c65da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34519
22739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3451922739
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.307823401
Short name T577
Test name
Test status
Simulation time 156813293 ps
CPU time 7.67 seconds
Started Jul 21 06:09:38 PM PDT 24
Finished Jul 21 06:09:46 PM PDT 24
Peak memory 254684 kb
Host smart-e26d914b-581d-47f1-b811-5d2d4d9c23ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30782
3401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.307823401
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.52331157
Short name T584
Test name
Test status
Simulation time 718411308 ps
CPU time 51.75 seconds
Started Jul 21 06:09:40 PM PDT 24
Finished Jul 21 06:10:32 PM PDT 24
Peak memory 257136 kb
Host smart-d0ca924a-d257-4ea7-8d98-2bd9130992ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52331
157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.52331157
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.648171880
Short name T57
Test name
Test status
Simulation time 190986755328 ps
CPU time 834.39 seconds
Started Jul 21 06:09:38 PM PDT 24
Finished Jul 21 06:23:33 PM PDT 24
Peak memory 273716 kb
Host smart-e9d8cc1f-65f9-431a-afa7-da6dce60d2aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648171880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.648171880
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2295633838
Short name T600
Test name
Test status
Simulation time 1312524326 ps
CPU time 120.06 seconds
Started Jul 21 06:09:41 PM PDT 24
Finished Jul 21 06:11:41 PM PDT 24
Peak memory 256752 kb
Host smart-1a8ef056-3c76-47bd-87bb-abd15518aba7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22956
33838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2295633838
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1951296479
Short name T685
Test name
Test status
Simulation time 393520300 ps
CPU time 35 seconds
Started Jul 21 06:09:42 PM PDT 24
Finished Jul 21 06:10:17 PM PDT 24
Peak memory 248860 kb
Host smart-0847fe98-5cd9-472a-86d1-0445d15131d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19512
96479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1951296479
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.2823956431
Short name T238
Test name
Test status
Simulation time 65907220050 ps
CPU time 1599.99 seconds
Started Jul 21 06:09:47 PM PDT 24
Finished Jul 21 06:36:27 PM PDT 24
Peak memory 269596 kb
Host smart-7c8fa3bc-6b21-427d-8a4a-ef1eb9014ac5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823956431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.2823956431
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.483919244
Short name T634
Test name
Test status
Simulation time 13148539392 ps
CPU time 649.86 seconds
Started Jul 21 06:09:46 PM PDT 24
Finished Jul 21 06:20:36 PM PDT 24
Peak memory 273576 kb
Host smart-913d55f3-4637-4d8f-9c4d-f431e56e285a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483919244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.483919244
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3457136842
Short name T421
Test name
Test status
Simulation time 2016820376 ps
CPU time 65.22 seconds
Started Jul 21 06:09:40 PM PDT 24
Finished Jul 21 06:10:46 PM PDT 24
Peak memory 249028 kb
Host smart-10b7a26b-d77e-4722-b989-5db41657dbb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34571
36842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3457136842
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.2423073476
Short name T703
Test name
Test status
Simulation time 206456626 ps
CPU time 25.61 seconds
Started Jul 21 06:09:39 PM PDT 24
Finished Jul 21 06:10:06 PM PDT 24
Peak memory 248456 kb
Host smart-49494d34-6ab6-4d01-b1cd-a14e7c2a2abe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24230
73476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2423073476
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.3970485858
Short name T539
Test name
Test status
Simulation time 86442065 ps
CPU time 10.3 seconds
Started Jul 21 06:09:39 PM PDT 24
Finished Jul 21 06:09:50 PM PDT 24
Peak memory 249028 kb
Host smart-090615f7-4a4e-40b0-b82b-1f6e4a29d49b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39704
85858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3970485858
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.3500899189
Short name T694
Test name
Test status
Simulation time 950902271 ps
CPU time 29.43 seconds
Started Jul 21 06:09:42 PM PDT 24
Finished Jul 21 06:10:12 PM PDT 24
Peak memory 248908 kb
Host smart-9c1152ea-29c5-48bf-91d0-de48e542ff17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35008
99189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3500899189
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.4257679309
Short name T454
Test name
Test status
Simulation time 106654002775 ps
CPU time 3079.91 seconds
Started Jul 21 06:09:47 PM PDT 24
Finished Jul 21 07:01:08 PM PDT 24
Peak memory 290060 kb
Host smart-39a7a63a-d514-4fc0-bcf2-e66b47ab35bc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257679309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.4257679309
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.1103798271
Short name T33
Test name
Test status
Simulation time 33920236700 ps
CPU time 2592.84 seconds
Started Jul 21 06:09:48 PM PDT 24
Finished Jul 21 06:53:01 PM PDT 24
Peak memory 289188 kb
Host smart-4c6642fb-c42c-41ac-b456-ae05b6ce50d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103798271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.1103798271
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.678816358
Short name T487
Test name
Test status
Simulation time 5714943688 ps
CPU time 359.05 seconds
Started Jul 21 06:09:49 PM PDT 24
Finished Jul 21 06:15:48 PM PDT 24
Peak memory 257292 kb
Host smart-efc18825-ced0-4999-9486-976b35ee23cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67881
6358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.678816358
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2904346296
Short name T641
Test name
Test status
Simulation time 261011943 ps
CPU time 28.45 seconds
Started Jul 21 06:09:47 PM PDT 24
Finished Jul 21 06:10:16 PM PDT 24
Peak memory 248712 kb
Host smart-6ed562e1-9d48-4b55-adf1-3466811fa232
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29043
46296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2904346296
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.2530518224
Short name T70
Test name
Test status
Simulation time 23566795726 ps
CPU time 1372.62 seconds
Started Jul 21 06:09:52 PM PDT 24
Finished Jul 21 06:32:45 PM PDT 24
Peak memory 273708 kb
Host smart-b0df9dd5-5578-44d2-9c1d-78b03382a33b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2530518224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2530518224
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.999325606
Short name T449
Test name
Test status
Simulation time 35220012271 ps
CPU time 2040.59 seconds
Started Jul 21 06:09:53 PM PDT 24
Finished Jul 21 06:43:55 PM PDT 24
Peak memory 289980 kb
Host smart-b81b5674-117d-4e14-a90a-15a669d31179
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999325606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.999325606
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.3910685388
Short name T34
Test name
Test status
Simulation time 11093044829 ps
CPU time 447.78 seconds
Started Jul 21 06:09:53 PM PDT 24
Finished Jul 21 06:17:21 PM PDT 24
Peak memory 247944 kb
Host smart-7f1ec28e-6867-40f2-980b-33f94e3aa280
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910685388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.3910685388
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1590063275
Short name T481
Test name
Test status
Simulation time 4701789374 ps
CPU time 33.94 seconds
Started Jul 21 06:09:47 PM PDT 24
Finished Jul 21 06:10:21 PM PDT 24
Peak memory 249100 kb
Host smart-a263562b-80ab-4505-823f-db387d037a16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15900
63275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1590063275
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2793919197
Short name T623
Test name
Test status
Simulation time 265589471 ps
CPU time 23.56 seconds
Started Jul 21 06:09:46 PM PDT 24
Finished Jul 21 06:10:10 PM PDT 24
Peak memory 248504 kb
Host smart-149f8cb3-b46d-4954-8bfe-f00428b37af4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27939
19197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2793919197
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1029621855
Short name T301
Test name
Test status
Simulation time 71179507 ps
CPU time 9.15 seconds
Started Jul 21 06:09:47 PM PDT 24
Finished Jul 21 06:09:56 PM PDT 24
Peak memory 255564 kb
Host smart-0cb7ac2b-299b-4b5e-b717-9214e3750564
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10296
21855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1029621855
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1017854413
Short name T536
Test name
Test status
Simulation time 175192628 ps
CPU time 17.14 seconds
Started Jul 21 06:09:48 PM PDT 24
Finished Jul 21 06:10:05 PM PDT 24
Peak memory 255900 kb
Host smart-c08f9656-fdec-46f1-a6da-4a0b80054463
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10178
54413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1017854413
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2194345625
Short name T111
Test name
Test status
Simulation time 39601027630 ps
CPU time 994.15 seconds
Started Jul 21 06:09:53 PM PDT 24
Finished Jul 21 06:26:28 PM PDT 24
Peak memory 273708 kb
Host smart-ac07b468-3a22-4ece-8280-ced143d3ae62
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194345625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2194345625
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.887633929
Short name T687
Test name
Test status
Simulation time 186907771733 ps
CPU time 5080.54 seconds
Started Jul 21 06:09:57 PM PDT 24
Finished Jul 21 07:34:39 PM PDT 24
Peak memory 330856 kb
Host smart-6325a6d3-a7fa-43ae-8268-dea15d639000
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887633929 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.887633929
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.3598434005
Short name T381
Test name
Test status
Simulation time 281810506233 ps
CPU time 2213.92 seconds
Started Jul 21 06:09:53 PM PDT 24
Finished Jul 21 06:46:47 PM PDT 24
Peak memory 283852 kb
Host smart-f8972d90-a2e9-4a80-b730-9697b623474d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598434005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3598434005
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.70435971
Short name T399
Test name
Test status
Simulation time 176977664 ps
CPU time 18.57 seconds
Started Jul 21 06:09:54 PM PDT 24
Finished Jul 21 06:10:13 PM PDT 24
Peak memory 256560 kb
Host smart-91f6bacd-d9b8-47bb-ba4a-ee5f87c78c23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70435
971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.70435971
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.2901128700
Short name T488
Test name
Test status
Simulation time 305336549 ps
CPU time 4.89 seconds
Started Jul 21 06:09:53 PM PDT 24
Finished Jul 21 06:09:58 PM PDT 24
Peak memory 249572 kb
Host smart-a0f7f5dc-a0e2-484f-be62-e4064db70172
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29011
28700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.2901128700
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3983826928
Short name T334
Test name
Test status
Simulation time 56709094564 ps
CPU time 3461.49 seconds
Started Jul 21 06:09:52 PM PDT 24
Finished Jul 21 07:07:34 PM PDT 24
Peak memory 289888 kb
Host smart-84956f33-a6ac-41c6-a48c-8da1a3b77cc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983826928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3983826928
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3762242877
Short name T571
Test name
Test status
Simulation time 205908967681 ps
CPU time 1865.62 seconds
Started Jul 21 06:09:58 PM PDT 24
Finished Jul 21 06:41:04 PM PDT 24
Peak memory 285400 kb
Host smart-2826f0ba-96f3-442f-b2ac-98c19412ddf6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762242877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3762242877
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.4148364368
Short name T558
Test name
Test status
Simulation time 88183557815 ps
CPU time 298.26 seconds
Started Jul 21 06:09:52 PM PDT 24
Finished Jul 21 06:14:51 PM PDT 24
Peak memory 248864 kb
Host smart-80e71690-d6ae-476e-a368-c05993a77ad0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148364368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.4148364368
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.1855932599
Short name T402
Test name
Test status
Simulation time 871887986 ps
CPU time 29.41 seconds
Started Jul 21 06:09:52 PM PDT 24
Finished Jul 21 06:10:21 PM PDT 24
Peak memory 256428 kb
Host smart-51fa8ac5-fc1c-4de3-8d50-1b4cdd2b3838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18559
32599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.1855932599
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.4119698160
Short name T594
Test name
Test status
Simulation time 281292959 ps
CPU time 6.7 seconds
Started Jul 21 06:09:52 PM PDT 24
Finished Jul 21 06:09:59 PM PDT 24
Peak memory 251568 kb
Host smart-60527c59-5774-4201-a14a-5589296dcdfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41196
98160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.4119698160
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.1662676366
Short name T259
Test name
Test status
Simulation time 985587367 ps
CPU time 38.85 seconds
Started Jul 21 06:09:53 PM PDT 24
Finished Jul 21 06:10:33 PM PDT 24
Peak memory 256680 kb
Host smart-575096ca-a07a-4006-bda0-99a93544e276
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16626
76366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1662676366
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2797017431
Short name T696
Test name
Test status
Simulation time 4589904277 ps
CPU time 70.49 seconds
Started Jul 21 06:09:52 PM PDT 24
Finished Jul 21 06:11:03 PM PDT 24
Peak memory 257292 kb
Host smart-f25812f3-3146-4640-af08-aeac40950d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27970
17431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2797017431
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.1549841551
Short name T287
Test name
Test status
Simulation time 316534821069 ps
CPU time 4250.78 seconds
Started Jul 21 06:09:52 PM PDT 24
Finished Jul 21 07:20:44 PM PDT 24
Peak memory 304748 kb
Host smart-4ad7093b-da38-4af8-aa79-b21a27ad512a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549841551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.1549841551
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.3219556386
Short name T86
Test name
Test status
Simulation time 219953089943 ps
CPU time 1740.24 seconds
Started Jul 21 06:09:54 PM PDT 24
Finished Jul 21 06:38:55 PM PDT 24
Peak memory 290180 kb
Host smart-ec445a1a-3d6a-4768-94f8-24d1c68b4d51
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219556386 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.3219556386
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1822405949
Short name T693
Test name
Test status
Simulation time 27456200735 ps
CPU time 1832.74 seconds
Started Jul 21 06:09:59 PM PDT 24
Finished Jul 21 06:40:32 PM PDT 24
Peak memory 283032 kb
Host smart-2dff9df4-9f06-42fc-81e1-156b150eb029
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822405949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1822405949
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.939207822
Short name T482
Test name
Test status
Simulation time 1165844003 ps
CPU time 107.26 seconds
Started Jul 21 06:09:56 PM PDT 24
Finished Jul 21 06:11:44 PM PDT 24
Peak memory 256588 kb
Host smart-9809b757-93d8-426b-978e-a6ac580df573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93920
7822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.939207822
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1442077125
Short name T82
Test name
Test status
Simulation time 367899034 ps
CPU time 21.53 seconds
Started Jul 21 06:09:58 PM PDT 24
Finished Jul 21 06:10:20 PM PDT 24
Peak memory 257096 kb
Host smart-e75c00ec-7b5d-48ce-99b1-0fa67a3c5155
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14420
77125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1442077125
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1149493772
Short name T331
Test name
Test status
Simulation time 15089359756 ps
CPU time 1363.04 seconds
Started Jul 21 06:09:59 PM PDT 24
Finished Jul 21 06:32:43 PM PDT 24
Peak memory 290120 kb
Host smart-18ddea6b-120a-4e35-bdc0-4d16d1c1ded9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149493772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1149493772
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.4253394391
Short name T626
Test name
Test status
Simulation time 168347645862 ps
CPU time 2648.44 seconds
Started Jul 21 06:09:57 PM PDT 24
Finished Jul 21 06:54:07 PM PDT 24
Peak memory 290108 kb
Host smart-a23ddc34-2276-476f-981f-4a8401f9b9b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253394391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.4253394391
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.1333361611
Short name T533
Test name
Test status
Simulation time 90865458507 ps
CPU time 262.79 seconds
Started Jul 21 06:09:58 PM PDT 24
Finished Jul 21 06:14:22 PM PDT 24
Peak memory 248708 kb
Host smart-f5646216-baf9-4757-a46f-18cbf6d35f9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333361611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.1333361611
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.3428279286
Short name T420
Test name
Test status
Simulation time 203696593 ps
CPU time 12.47 seconds
Started Jul 21 06:09:57 PM PDT 24
Finished Jul 21 06:10:10 PM PDT 24
Peak memory 255448 kb
Host smart-3e6c333c-397c-4236-8ad5-9ed234552314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34282
79286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3428279286
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.142179314
Short name T47
Test name
Test status
Simulation time 786720431 ps
CPU time 20.14 seconds
Started Jul 21 06:09:54 PM PDT 24
Finished Jul 21 06:10:14 PM PDT 24
Peak memory 256256 kb
Host smart-e93980ce-aea2-468e-845d-efef10cc60b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14217
9314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.142179314
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.3974206658
Short name T271
Test name
Test status
Simulation time 1593762249 ps
CPU time 27.12 seconds
Started Jul 21 06:09:58 PM PDT 24
Finished Jul 21 06:10:26 PM PDT 24
Peak memory 248468 kb
Host smart-e17f7438-a7d7-41b1-af18-5aa4113bb7ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39742
06658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.3974206658
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.49586503
Short name T535
Test name
Test status
Simulation time 2606195998 ps
CPU time 41.07 seconds
Started Jul 21 06:09:55 PM PDT 24
Finished Jul 21 06:10:36 PM PDT 24
Peak memory 256372 kb
Host smart-852d5ac9-3b3a-404c-8e03-18f17f4188bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49586
503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.49586503
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.5117779
Short name T39
Test name
Test status
Simulation time 3184544950 ps
CPU time 137.6 seconds
Started Jul 21 06:09:58 PM PDT 24
Finished Jul 21 06:12:16 PM PDT 24
Peak memory 252228 kb
Host smart-5f38ccb6-7f8c-42a9-8d23-e3f54625dd85
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5117779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handl
er_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handl
er_stress_all.5117779
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.3441773843
Short name T119
Test name
Test status
Simulation time 36593496199 ps
CPU time 3445.03 seconds
Started Jul 21 06:09:59 PM PDT 24
Finished Jul 21 07:07:25 PM PDT 24
Peak memory 331012 kb
Host smart-7a4cf63a-afca-45e3-b7f4-89f3893216ff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441773843 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.3441773843
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.3374894955
Short name T549
Test name
Test status
Simulation time 56687551254 ps
CPU time 1490.82 seconds
Started Jul 21 06:10:05 PM PDT 24
Finished Jul 21 06:34:56 PM PDT 24
Peak memory 273332 kb
Host smart-ce078fdb-9933-4fe3-92cc-732604fe1bb3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374894955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.3374894955
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.779823870
Short name T294
Test name
Test status
Simulation time 8467430667 ps
CPU time 140.4 seconds
Started Jul 21 06:10:00 PM PDT 24
Finished Jul 21 06:12:21 PM PDT 24
Peak memory 256472 kb
Host smart-836875a4-5e86-4204-abda-b3f3a2b94e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77982
3870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.779823870
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3954756675
Short name T502
Test name
Test status
Simulation time 2511353524 ps
CPU time 46.2 seconds
Started Jul 21 06:10:00 PM PDT 24
Finished Jul 21 06:10:47 PM PDT 24
Peak memory 248720 kb
Host smart-797d4350-4519-42dc-acc1-eb2bcf536d07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39547
56675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3954756675
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2341979160
Short name T357
Test name
Test status
Simulation time 14755030025 ps
CPU time 1171.22 seconds
Started Jul 21 06:10:04 PM PDT 24
Finished Jul 21 06:29:36 PM PDT 24
Peak memory 273120 kb
Host smart-e52b793b-56bf-486a-a139-152dc230e114
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341979160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2341979160
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1256430852
Short name T439
Test name
Test status
Simulation time 5874370738 ps
CPU time 665.61 seconds
Started Jul 21 06:10:06 PM PDT 24
Finished Jul 21 06:21:12 PM PDT 24
Peak memory 266484 kb
Host smart-1b718efc-27e1-4310-bf10-eed916a2b776
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256430852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1256430852
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.784530224
Short name T611
Test name
Test status
Simulation time 5260155613 ps
CPU time 109.96 seconds
Started Jul 21 06:10:02 PM PDT 24
Finished Jul 21 06:11:52 PM PDT 24
Peak memory 249076 kb
Host smart-cc5581b6-383d-4c48-acb0-5b38e57685b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784530224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.784530224
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.1495774441
Short name T27
Test name
Test status
Simulation time 101869575 ps
CPU time 4.5 seconds
Started Jul 21 06:09:59 PM PDT 24
Finished Jul 21 06:10:04 PM PDT 24
Peak memory 249004 kb
Host smart-1ca806d5-6968-4239-a737-d09b45c04aa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14957
74441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1495774441
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1661704858
Short name T607
Test name
Test status
Simulation time 115909899 ps
CPU time 9.83 seconds
Started Jul 21 06:09:58 PM PDT 24
Finished Jul 21 06:10:08 PM PDT 24
Peak memory 252000 kb
Host smart-b189b501-8a47-4ec4-8b3f-802f47ce0a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16617
04858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1661704858
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3658680647
Short name T525
Test name
Test status
Simulation time 8531822012 ps
CPU time 47 seconds
Started Jul 21 06:09:58 PM PDT 24
Finished Jul 21 06:10:46 PM PDT 24
Peak memory 256768 kb
Host smart-f746de56-c660-4a25-b3af-f97b8c0e6a71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36586
80647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3658680647
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1181076641
Short name T84
Test name
Test status
Simulation time 767562331 ps
CPU time 23.11 seconds
Started Jul 21 06:09:58 PM PDT 24
Finished Jul 21 06:10:21 PM PDT 24
Peak memory 248952 kb
Host smart-a5467fd3-9718-4ecb-b7ba-e0aa141a6a56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11810
76641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1181076641
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2723147316
Short name T236
Test name
Test status
Simulation time 55527711745 ps
CPU time 3181.62 seconds
Started Jul 21 06:10:04 PM PDT 24
Finished Jul 21 07:03:06 PM PDT 24
Peak memory 289640 kb
Host smart-252e0e83-d75c-4498-afb1-38f239ec512e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723147316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2723147316
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3430858204
Short name T295
Test name
Test status
Simulation time 9038292168 ps
CPU time 1088.45 seconds
Started Jul 21 06:10:05 PM PDT 24
Finished Jul 21 06:28:13 PM PDT 24
Peak memory 284160 kb
Host smart-47ff04df-4400-426f-98cb-2da84c673644
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430858204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3430858204
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.4200739017
Short name T300
Test name
Test status
Simulation time 3163946859 ps
CPU time 196.19 seconds
Started Jul 21 06:10:07 PM PDT 24
Finished Jul 21 06:13:23 PM PDT 24
Peak memory 256540 kb
Host smart-87557a2f-3a1e-475e-9b42-82482cc3e523
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42007
39017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.4200739017
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.4046329518
Short name T417
Test name
Test status
Simulation time 179733442 ps
CPU time 14.14 seconds
Started Jul 21 06:10:08 PM PDT 24
Finished Jul 21 06:10:22 PM PDT 24
Peak memory 249028 kb
Host smart-be442ebe-7726-44f4-8377-2b62b3bc401f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40463
29518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.4046329518
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.814465388
Short name T510
Test name
Test status
Simulation time 120278663912 ps
CPU time 1730.78 seconds
Started Jul 21 06:10:04 PM PDT 24
Finished Jul 21 06:38:55 PM PDT 24
Peak memory 273580 kb
Host smart-4bbdeb5e-fd1e-4648-bdcd-9f22b9209b8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814465388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.814465388
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3518271515
Short name T112
Test name
Test status
Simulation time 49145732252 ps
CPU time 1399.03 seconds
Started Jul 21 06:10:06 PM PDT 24
Finished Jul 21 06:33:26 PM PDT 24
Peak memory 283172 kb
Host smart-d4052f34-738d-403e-8ec4-e25c6df71fcc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518271515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3518271515
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.74628540
Short name T321
Test name
Test status
Simulation time 28993056454 ps
CPU time 347.03 seconds
Started Jul 21 06:10:09 PM PDT 24
Finished Jul 21 06:15:56 PM PDT 24
Peak memory 249112 kb
Host smart-3787ab17-2622-47d7-b0d3-8a90b7f39473
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74628540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.74628540
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2836460669
Short name T578
Test name
Test status
Simulation time 371719736 ps
CPU time 30.74 seconds
Started Jul 21 06:10:03 PM PDT 24
Finished Jul 21 06:10:34 PM PDT 24
Peak memory 256516 kb
Host smart-a6039867-91eb-4b68-af4c-b4251edfe1b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28364
60669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2836460669
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3023416403
Short name T245
Test name
Test status
Simulation time 1837401412 ps
CPU time 15.46 seconds
Started Jul 21 06:10:04 PM PDT 24
Finished Jul 21 06:10:20 PM PDT 24
Peak memory 256964 kb
Host smart-8070f599-01d1-4c66-a16c-f5281b48aab7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30234
16403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3023416403
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2573251033
Short name T520
Test name
Test status
Simulation time 757912742 ps
CPU time 12.56 seconds
Started Jul 21 06:10:04 PM PDT 24
Finished Jul 21 06:10:17 PM PDT 24
Peak memory 248356 kb
Host smart-eaa63ab7-4017-4a42-83af-c10b56516ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25732
51033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2573251033
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.4006715057
Short name T422
Test name
Test status
Simulation time 8427976360 ps
CPU time 63.52 seconds
Started Jul 21 06:10:05 PM PDT 24
Finished Jul 21 06:11:09 PM PDT 24
Peak memory 257292 kb
Host smart-07b4f9ea-80fc-4fcc-9ed4-55c2e3e0e250
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40067
15057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.4006715057
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.697147975
Short name T673
Test name
Test status
Simulation time 657053523 ps
CPU time 40.79 seconds
Started Jul 21 06:10:10 PM PDT 24
Finished Jul 21 06:10:52 PM PDT 24
Peak memory 249028 kb
Host smart-fae53b5a-f687-4091-afc2-37c26d563520
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697147975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han
dler_stress_all.697147975
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3804408049
Short name T427
Test name
Test status
Simulation time 33048310298 ps
CPU time 786.04 seconds
Started Jul 21 06:10:11 PM PDT 24
Finished Jul 21 06:23:17 PM PDT 24
Peak memory 273312 kb
Host smart-6a0909a0-e934-433a-b755-9e222432c057
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804408049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3804408049
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2382415340
Short name T268
Test name
Test status
Simulation time 1696638671 ps
CPU time 98.29 seconds
Started Jul 21 06:10:10 PM PDT 24
Finished Jul 21 06:11:49 PM PDT 24
Peak memory 256752 kb
Host smart-5fe22771-2c73-4253-accd-4f2839ac358b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23824
15340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2382415340
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.2122135557
Short name T389
Test name
Test status
Simulation time 1225060617 ps
CPU time 23.71 seconds
Started Jul 21 06:10:12 PM PDT 24
Finished Jul 21 06:10:36 PM PDT 24
Peak memory 255252 kb
Host smart-28942bd3-b8b3-495a-b009-10136ddf58db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21221
35557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.2122135557
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2375186028
Short name T106
Test name
Test status
Simulation time 49984978680 ps
CPU time 1520.87 seconds
Started Jul 21 06:10:11 PM PDT 24
Finished Jul 21 06:35:33 PM PDT 24
Peak memory 272432 kb
Host smart-283dba88-1157-488d-b2a7-dd8521e5b5c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375186028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2375186028
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.409435714
Short name T479
Test name
Test status
Simulation time 16451682026 ps
CPU time 1354.27 seconds
Started Jul 21 06:10:11 PM PDT 24
Finished Jul 21 06:32:46 PM PDT 24
Peak memory 289516 kb
Host smart-6409afec-f928-45ba-9e3f-41a04cc02136
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409435714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.409435714
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.1121158685
Short name T318
Test name
Test status
Simulation time 13664510137 ps
CPU time 561.47 seconds
Started Jul 21 06:10:14 PM PDT 24
Finished Jul 21 06:19:36 PM PDT 24
Peak memory 248996 kb
Host smart-2ba900c0-0043-427a-934e-3516ab322c4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121158685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1121158685
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.3432056168
Short name T76
Test name
Test status
Simulation time 1115351938 ps
CPU time 16.31 seconds
Started Jul 21 06:10:12 PM PDT 24
Finished Jul 21 06:10:29 PM PDT 24
Peak memory 249024 kb
Host smart-86c78ee1-fc73-424c-99b6-46f6a287d4ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34320
56168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.3432056168
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.3906728316
Short name T377
Test name
Test status
Simulation time 308627130 ps
CPU time 18.73 seconds
Started Jul 21 06:10:12 PM PDT 24
Finished Jul 21 06:10:31 PM PDT 24
Peak memory 248528 kb
Host smart-5f1563f7-e266-45a4-9605-c6237f24fd53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39067
28316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.3906728316
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.2120424305
Short name T504
Test name
Test status
Simulation time 341937200 ps
CPU time 6.82 seconds
Started Jul 21 06:10:10 PM PDT 24
Finished Jul 21 06:10:17 PM PDT 24
Peak memory 252392 kb
Host smart-42433c16-e141-4ec8-83b3-2cd13c97feea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21204
24305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.2120424305
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2487672770
Short name T475
Test name
Test status
Simulation time 674878740 ps
CPU time 18.72 seconds
Started Jul 21 06:10:12 PM PDT 24
Finished Jul 21 06:10:31 PM PDT 24
Peak memory 257144 kb
Host smart-1f071fbf-4c5a-47c5-a7cc-78c83fb401d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24876
72770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2487672770
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.4173331725
Short name T606
Test name
Test status
Simulation time 199589009773 ps
CPU time 2960.05 seconds
Started Jul 21 06:10:19 PM PDT 24
Finished Jul 21 06:59:40 PM PDT 24
Peak memory 289332 kb
Host smart-42cc86ee-e975-429b-ab75-6e13c5c9cfaa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173331725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.4173331725
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2355586080
Short name T596
Test name
Test status
Simulation time 24860074551 ps
CPU time 1244.63 seconds
Started Jul 21 06:10:21 PM PDT 24
Finished Jul 21 06:31:06 PM PDT 24
Peak memory 286936 kb
Host smart-45d4abed-625f-4e42-835e-5ea845dc28ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355586080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2355586080
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3351014962
Short name T674
Test name
Test status
Simulation time 537126742 ps
CPU time 26.84 seconds
Started Jul 21 06:10:19 PM PDT 24
Finished Jul 21 06:10:46 PM PDT 24
Peak memory 257116 kb
Host smart-bc1c6f8a-468c-467c-9513-ab767d28e3cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33510
14962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3351014962
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.1763427139
Short name T511
Test name
Test status
Simulation time 1314302451 ps
CPU time 53.65 seconds
Started Jul 21 06:10:18 PM PDT 24
Finished Jul 21 06:11:12 PM PDT 24
Peak memory 256680 kb
Host smart-26957821-b464-4179-8c3d-ca00ba79a368
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17634
27139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1763427139
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.3817818935
Short name T652
Test name
Test status
Simulation time 22842062466 ps
CPU time 701.22 seconds
Started Jul 21 06:10:25 PM PDT 24
Finished Jul 21 06:22:07 PM PDT 24
Peak memory 272692 kb
Host smart-0deb7489-86cd-4d3d-9a9a-9a3de1e13bde
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817818935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3817818935
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.3609564176
Short name T593
Test name
Test status
Simulation time 339224595969 ps
CPU time 3224.87 seconds
Started Jul 21 06:10:24 PM PDT 24
Finished Jul 21 07:04:10 PM PDT 24
Peak memory 290072 kb
Host smart-97d23cf8-abe9-4b3f-a50e-f3ff135d0e3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609564176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3609564176
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.4075444879
Short name T647
Test name
Test status
Simulation time 34918306021 ps
CPU time 719.37 seconds
Started Jul 21 06:10:24 PM PDT 24
Finished Jul 21 06:22:24 PM PDT 24
Peak memory 257196 kb
Host smart-d9abb888-796f-4883-8fcf-ba8e1d47785b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075444879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.4075444879
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.2334716666
Short name T447
Test name
Test status
Simulation time 457959665 ps
CPU time 28.45 seconds
Started Jul 21 06:10:19 PM PDT 24
Finished Jul 21 06:10:47 PM PDT 24
Peak memory 249008 kb
Host smart-2cc455c1-f81a-4ded-a7e2-319b2e6a8a6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23347
16666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.2334716666
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.4081123402
Short name T412
Test name
Test status
Simulation time 50012460 ps
CPU time 7.81 seconds
Started Jul 21 06:10:23 PM PDT 24
Finished Jul 21 06:10:31 PM PDT 24
Peak memory 249756 kb
Host smart-7e6568fd-62e6-4b39-bd12-ddb78899d3dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40811
23402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.4081123402
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.2372875825
Short name T5
Test name
Test status
Simulation time 193919984 ps
CPU time 28.83 seconds
Started Jul 21 06:10:19 PM PDT 24
Finished Jul 21 06:10:48 PM PDT 24
Peak memory 256660 kb
Host smart-ad186e46-924f-4acc-8cf8-c5d0547c3e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23728
75825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2372875825
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3862214247
Short name T477
Test name
Test status
Simulation time 512664923 ps
CPU time 37.52 seconds
Started Jul 21 06:10:19 PM PDT 24
Finished Jul 21 06:10:57 PM PDT 24
Peak memory 257120 kb
Host smart-39d78792-bfce-42b6-bf53-414603129969
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38622
14247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3862214247
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.3127006734
Short name T281
Test name
Test status
Simulation time 165494541336 ps
CPU time 3014.36 seconds
Started Jul 21 06:10:25 PM PDT 24
Finished Jul 21 07:00:40 PM PDT 24
Peak memory 298128 kb
Host smart-864afcd4-51b6-44bb-8fc5-84fe348ec780
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127006734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.3127006734
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.2097645532
Short name T283
Test name
Test status
Simulation time 59966207303 ps
CPU time 3957.26 seconds
Started Jul 21 06:10:27 PM PDT 24
Finished Jul 21 07:16:25 PM PDT 24
Peak memory 305928 kb
Host smart-39e9af52-2dc2-409d-8487-b463c5da1403
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097645532 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.2097645532
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.3307095362
Short name T411
Test name
Test status
Simulation time 172374669774 ps
CPU time 2393.35 seconds
Started Jul 21 06:10:27 PM PDT 24
Finished Jul 21 06:50:21 PM PDT 24
Peak memory 281228 kb
Host smart-8f274a52-7593-41cf-bca2-d1cf88d930f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307095362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.3307095362
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.30105044
Short name T400
Test name
Test status
Simulation time 1182247185 ps
CPU time 49.21 seconds
Started Jul 21 06:10:26 PM PDT 24
Finished Jul 21 06:11:16 PM PDT 24
Peak memory 256368 kb
Host smart-f8f3ec11-493e-4f37-8bfc-f7f5299ad216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30105
044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.30105044
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.4249458170
Short name T401
Test name
Test status
Simulation time 371625114 ps
CPU time 16.69 seconds
Started Jul 21 06:10:24 PM PDT 24
Finished Jul 21 06:10:41 PM PDT 24
Peak memory 248900 kb
Host smart-8654698e-8dce-42f5-8047-69b1cf67255e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42494
58170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.4249458170
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.1268790903
Short name T350
Test name
Test status
Simulation time 89223239694 ps
CPU time 2063.59 seconds
Started Jul 21 06:10:34 PM PDT 24
Finished Jul 21 06:44:58 PM PDT 24
Peak memory 287652 kb
Host smart-c8c9d22a-6bf0-472e-9c1d-7a1b6304334f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268790903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1268790903
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1652125351
Short name T184
Test name
Test status
Simulation time 18113714856 ps
CPU time 1779.21 seconds
Started Jul 21 06:10:31 PM PDT 24
Finished Jul 21 06:40:11 PM PDT 24
Peak memory 289700 kb
Host smart-db68e8b9-9e1e-4c3d-9d9d-bdbce4c9120f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652125351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1652125351
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.3881300663
Short name T234
Test name
Test status
Simulation time 54729341649 ps
CPU time 544.89 seconds
Started Jul 21 06:10:26 PM PDT 24
Finished Jul 21 06:19:32 PM PDT 24
Peak memory 248896 kb
Host smart-f9d3a7ab-9017-4c51-95c7-06c64c84e55c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881300663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3881300663
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2188410094
Short name T397
Test name
Test status
Simulation time 339673149 ps
CPU time 12.93 seconds
Started Jul 21 06:10:26 PM PDT 24
Finished Jul 21 06:10:39 PM PDT 24
Peak memory 249028 kb
Host smart-354cb592-ac1e-4067-b4b6-b28624804176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21884
10094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2188410094
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1573969675
Short name T37
Test name
Test status
Simulation time 341660894 ps
CPU time 29.55 seconds
Started Jul 21 06:10:26 PM PDT 24
Finished Jul 21 06:10:56 PM PDT 24
Peak memory 249384 kb
Host smart-e19e8b04-be77-4f1c-8cef-5549dc2852c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15739
69675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1573969675
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2722667115
Short name T622
Test name
Test status
Simulation time 205433843 ps
CPU time 24.99 seconds
Started Jul 21 06:10:25 PM PDT 24
Finished Jul 21 06:10:50 PM PDT 24
Peak memory 256404 kb
Host smart-8711dde4-8cd4-4ac1-9982-322a3ea6d62c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27226
67115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2722667115
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3960870185
Short name T308
Test name
Test status
Simulation time 4462541472 ps
CPU time 71.46 seconds
Started Jul 21 06:10:26 PM PDT 24
Finished Jul 21 06:11:38 PM PDT 24
Peak memory 257292 kb
Host smart-698f82e7-62d5-449d-b76e-0393102a9ba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39608
70185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3960870185
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2417422221
Short name T541
Test name
Test status
Simulation time 39372594250 ps
CPU time 2590.72 seconds
Started Jul 21 06:10:31 PM PDT 24
Finished Jul 21 06:53:42 PM PDT 24
Peak memory 289996 kb
Host smart-8aae74c6-728f-4e72-8571-9abfb7b0dae4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417422221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2417422221
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.955013857
Short name T213
Test name
Test status
Simulation time 43054487 ps
CPU time 3.64 seconds
Started Jul 21 06:07:44 PM PDT 24
Finished Jul 21 06:07:48 PM PDT 24
Peak memory 249256 kb
Host smart-8de767e9-8e7e-4c54-bbb3-ce50854cc055
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=955013857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.955013857
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2245587141
Short name T254
Test name
Test status
Simulation time 186661100489 ps
CPU time 2662.49 seconds
Started Jul 21 06:07:40 PM PDT 24
Finished Jul 21 06:52:04 PM PDT 24
Peak memory 281640 kb
Host smart-e0416436-4ea8-45b9-b873-3f010bca5a9d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245587141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2245587141
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.4002643646
Short name T393
Test name
Test status
Simulation time 2257912763 ps
CPU time 26.5 seconds
Started Jul 21 06:07:38 PM PDT 24
Finished Jul 21 06:08:05 PM PDT 24
Peak memory 249072 kb
Host smart-19c3619e-d17d-4fc4-bce2-dff4239e8030
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4002643646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.4002643646
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.920749489
Short name T385
Test name
Test status
Simulation time 4766859405 ps
CPU time 256.13 seconds
Started Jul 21 06:07:37 PM PDT 24
Finished Jul 21 06:11:54 PM PDT 24
Peak memory 252208 kb
Host smart-b9252345-5a05-401c-a927-8e6ae7e9f0f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92074
9489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.920749489
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.2213481226
Short name T83
Test name
Test status
Simulation time 1118935334 ps
CPU time 38.93 seconds
Started Jul 21 06:07:38 PM PDT 24
Finished Jul 21 06:08:17 PM PDT 24
Peak memory 249656 kb
Host smart-81bcfd86-1132-4496-b299-d9ff7ec53e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22134
81226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.2213481226
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.482822333
Short name T683
Test name
Test status
Simulation time 586679245831 ps
CPU time 2228.04 seconds
Started Jul 21 06:07:39 PM PDT 24
Finished Jul 21 06:44:49 PM PDT 24
Peak memory 288712 kb
Host smart-08d53d76-2023-4ea1-822e-28459fbf6f32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482822333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.482822333
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.3124001165
Short name T410
Test name
Test status
Simulation time 149301741702 ps
CPU time 2247.06 seconds
Started Jul 21 06:07:43 PM PDT 24
Finished Jul 21 06:45:10 PM PDT 24
Peak memory 289044 kb
Host smart-1982a255-4139-46bd-9749-2506a903003f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124001165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3124001165
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.1949577989
Short name T572
Test name
Test status
Simulation time 17958016233 ps
CPU time 161.69 seconds
Started Jul 21 06:07:37 PM PDT 24
Finished Jul 21 06:10:19 PM PDT 24
Peak memory 249120 kb
Host smart-d1a482ae-e30b-44e9-aff6-beb8e41b22e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949577989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1949577989
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.2107340920
Short name T680
Test name
Test status
Simulation time 5544852633 ps
CPU time 29.56 seconds
Started Jul 21 06:07:40 PM PDT 24
Finished Jul 21 06:08:10 PM PDT 24
Peak memory 249032 kb
Host smart-540d0d53-94f1-4ac1-bd6e-0bc524b8248f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21073
40920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.2107340920
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.2836459242
Short name T398
Test name
Test status
Simulation time 1710530360 ps
CPU time 49.22 seconds
Started Jul 21 06:07:43 PM PDT 24
Finished Jul 21 06:08:32 PM PDT 24
Peak memory 249428 kb
Host smart-a0a3e87f-5d9f-4ef5-8074-14abcc6f0fa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28364
59242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2836459242
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.2222182591
Short name T203
Test name
Test status
Simulation time 45804573 ps
CPU time 4.44 seconds
Started Jul 21 06:07:37 PM PDT 24
Finished Jul 21 06:07:41 PM PDT 24
Peak memory 240272 kb
Host smart-e5bbf571-424d-4cbd-895a-49e045a49daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22221
82591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2222182591
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1107142225
Short name T625
Test name
Test status
Simulation time 828543730 ps
CPU time 53.04 seconds
Started Jul 21 06:07:37 PM PDT 24
Finished Jul 21 06:08:30 PM PDT 24
Peak memory 256728 kb
Host smart-d18f5885-4382-4e38-92d9-e982b078ae5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11071
42225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1107142225
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2131951459
Short name T97
Test name
Test status
Simulation time 11247581205 ps
CPU time 385.36 seconds
Started Jul 21 06:07:40 PM PDT 24
Finished Jul 21 06:14:06 PM PDT 24
Peak memory 257264 kb
Host smart-0a24ef41-df4c-4797-ac1a-506f2bbd8836
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131951459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2131951459
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.1130495796
Short name T404
Test name
Test status
Simulation time 3830533951 ps
CPU time 146.08 seconds
Started Jul 21 06:10:36 PM PDT 24
Finished Jul 21 06:13:02 PM PDT 24
Peak memory 257384 kb
Host smart-b5219a1a-a83b-45de-8016-1402a327a0db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11304
95796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.1130495796
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1879691812
Short name T375
Test name
Test status
Simulation time 1125462941 ps
CPU time 26.14 seconds
Started Jul 21 06:10:30 PM PDT 24
Finished Jul 21 06:10:57 PM PDT 24
Peak memory 256044 kb
Host smart-ffc1414b-aab0-4b03-bf0c-938de98323cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18796
91812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1879691812
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1753230913
Short name T556
Test name
Test status
Simulation time 39382730813 ps
CPU time 1278.98 seconds
Started Jul 21 06:10:33 PM PDT 24
Finished Jul 21 06:31:53 PM PDT 24
Peak memory 281928 kb
Host smart-5d1d143e-cff7-4374-9007-e0e5a7c6a023
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753230913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1753230913
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.807464
Short name T692
Test name
Test status
Simulation time 125839803352 ps
CPU time 1940.86 seconds
Started Jul 21 06:10:33 PM PDT 24
Finished Jul 21 06:42:54 PM PDT 24
Peak memory 273504 kb
Host smart-15fd7a5a-71ec-4e5d-aec5-5e50d2067a13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.807464
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.2400080423
Short name T627
Test name
Test status
Simulation time 200775066 ps
CPU time 22.46 seconds
Started Jul 21 06:10:30 PM PDT 24
Finished Jul 21 06:10:53 PM PDT 24
Peak memory 256424 kb
Host smart-73435f66-50c0-4e59-9d5e-4a33d7ebb961
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24000
80423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2400080423
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.875072598
Short name T63
Test name
Test status
Simulation time 2066063771 ps
CPU time 45 seconds
Started Jul 21 06:10:35 PM PDT 24
Finished Jul 21 06:11:21 PM PDT 24
Peak memory 249584 kb
Host smart-83a06b04-5aa4-48f8-8238-fbdae099fc28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87507
2598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.875072598
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.1440123465
Short name T462
Test name
Test status
Simulation time 3412507918 ps
CPU time 53.45 seconds
Started Jul 21 06:10:33 PM PDT 24
Finished Jul 21 06:11:27 PM PDT 24
Peak memory 249460 kb
Host smart-c3272578-8eba-4f3c-a26a-eaeb5919c0de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14401
23465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1440123465
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1465174586
Short name T613
Test name
Test status
Simulation time 3498752510 ps
CPU time 48.81 seconds
Started Jul 21 06:10:34 PM PDT 24
Finished Jul 21 06:11:23 PM PDT 24
Peak memory 257280 kb
Host smart-c5e5be37-f47e-4d15-bd8e-6509b9fb6fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14651
74586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1465174586
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2860987043
Short name T705
Test name
Test status
Simulation time 13943340452 ps
CPU time 1228.08 seconds
Started Jul 21 06:10:40 PM PDT 24
Finished Jul 21 06:31:09 PM PDT 24
Peak memory 285624 kb
Host smart-becbf1c4-6389-452d-ad31-b371902e0194
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860987043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2860987043
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3664899227
Short name T298
Test name
Test status
Simulation time 2229523507 ps
CPU time 78.89 seconds
Started Jul 21 06:10:41 PM PDT 24
Finished Jul 21 06:12:00 PM PDT 24
Peak memory 256808 kb
Host smart-6ddf15ce-6846-408a-b84d-f82234bf1cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36648
99227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3664899227
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2939007368
Short name T667
Test name
Test status
Simulation time 194568063 ps
CPU time 26.63 seconds
Started Jul 21 06:10:41 PM PDT 24
Finished Jul 21 06:11:08 PM PDT 24
Peak memory 256724 kb
Host smart-f8adb4f3-a8f4-40e6-8d03-2879b5ddca16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29390
07368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2939007368
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3105503848
Short name T505
Test name
Test status
Simulation time 29317626813 ps
CPU time 1368.77 seconds
Started Jul 21 06:10:40 PM PDT 24
Finished Jul 21 06:33:29 PM PDT 24
Peak memory 289160 kb
Host smart-ad435ef3-3b0f-4436-88f5-670018761596
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105503848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3105503848
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.877811016
Short name T498
Test name
Test status
Simulation time 27661784 ps
CPU time 3.52 seconds
Started Jul 21 06:10:39 PM PDT 24
Finished Jul 21 06:10:43 PM PDT 24
Peak memory 248996 kb
Host smart-afb85a44-3a72-4066-8c23-b7e1720d51ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87781
1016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.877811016
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.3857652145
Short name T74
Test name
Test status
Simulation time 1271643303 ps
CPU time 82.75 seconds
Started Jul 21 06:10:40 PM PDT 24
Finished Jul 21 06:12:03 PM PDT 24
Peak memory 248796 kb
Host smart-27a4860a-1860-4a34-8021-bf95e57703e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38576
52145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3857652145
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.1336326094
Short name T698
Test name
Test status
Simulation time 984207133 ps
CPU time 34.39 seconds
Started Jul 21 06:10:40 PM PDT 24
Finished Jul 21 06:11:15 PM PDT 24
Peak memory 256112 kb
Host smart-fa4c7029-5bdf-4337-99c2-98981980ba4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13363
26094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1336326094
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.923028375
Short name T436
Test name
Test status
Simulation time 633245566 ps
CPU time 39.52 seconds
Started Jul 21 06:10:36 PM PDT 24
Finished Jul 21 06:11:16 PM PDT 24
Peak memory 257200 kb
Host smart-b53f4a48-680e-4539-9371-8d22f2ca7a18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92302
8375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.923028375
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.4137201092
Short name T266
Test name
Test status
Simulation time 7679696350 ps
CPU time 424.54 seconds
Started Jul 21 06:10:39 PM PDT 24
Finished Jul 21 06:17:44 PM PDT 24
Peak memory 257316 kb
Host smart-7b750bd8-2bf5-4c08-9f6a-a614f5cae9d4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137201092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.4137201092
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.2037654725
Short name T49
Test name
Test status
Simulation time 55342826089 ps
CPU time 1296.6 seconds
Started Jul 21 06:10:38 PM PDT 24
Finished Jul 21 06:32:16 PM PDT 24
Peak memory 289056 kb
Host smart-9574a5ed-2e7b-420d-98ca-2dfe29a75aec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037654725 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.2037654725
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3098029657
Short name T228
Test name
Test status
Simulation time 395016693180 ps
CPU time 1989.86 seconds
Started Jul 21 06:10:45 PM PDT 24
Finished Jul 21 06:43:56 PM PDT 24
Peak memory 273384 kb
Host smart-8987a01a-e2c9-45ea-8988-3392fd0bb358
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098029657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3098029657
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2851177162
Short name T662
Test name
Test status
Simulation time 776956007 ps
CPU time 75.75 seconds
Started Jul 21 06:10:46 PM PDT 24
Finished Jul 21 06:12:02 PM PDT 24
Peak memory 256200 kb
Host smart-4bc0578f-1626-4a8e-a0a9-7c7254a22cb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28511
77162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2851177162
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.2947895327
Short name T246
Test name
Test status
Simulation time 640192211 ps
CPU time 44.59 seconds
Started Jul 21 06:10:45 PM PDT 24
Finished Jul 21 06:11:30 PM PDT 24
Peak memory 248932 kb
Host smart-13c640e2-bcfb-42f0-9540-c5362180708c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29478
95327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2947895327
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1771074705
Short name T636
Test name
Test status
Simulation time 42323961370 ps
CPU time 2535.32 seconds
Started Jul 21 06:10:45 PM PDT 24
Finished Jul 21 06:53:01 PM PDT 24
Peak memory 284072 kb
Host smart-655fe050-1503-4a65-aaec-a40636f48eeb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771074705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1771074705
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2303889120
Short name T3
Test name
Test status
Simulation time 17747208217 ps
CPU time 182.66 seconds
Started Jul 21 06:10:46 PM PDT 24
Finished Jul 21 06:13:49 PM PDT 24
Peak memory 249140 kb
Host smart-9ef0a65c-85b5-4c74-b20e-669f04fb1fdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2303889120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2303889120
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3759615382
Short name T517
Test name
Test status
Simulation time 1307026119 ps
CPU time 35.82 seconds
Started Jul 21 06:10:39 PM PDT 24
Finished Jul 21 06:11:16 PM PDT 24
Peak memory 256508 kb
Host smart-dabf79de-6660-4b72-a6a2-18af6d61f94d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37596
15382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3759615382
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2286558762
Short name T405
Test name
Test status
Simulation time 245125760 ps
CPU time 5.52 seconds
Started Jul 21 06:10:39 PM PDT 24
Finished Jul 21 06:10:45 PM PDT 24
Peak memory 240344 kb
Host smart-224e135c-9cd0-4bcc-92a8-19c4699d30f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22865
58762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2286558762
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1050200557
Short name T98
Test name
Test status
Simulation time 50030842 ps
CPU time 5.68 seconds
Started Jul 21 06:10:37 PM PDT 24
Finished Jul 21 06:10:43 PM PDT 24
Peak memory 251388 kb
Host smart-de3a2972-4187-4245-b034-cc3cf4992f23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10502
00557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1050200557
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3218958648
Short name T58
Test name
Test status
Simulation time 39153305163 ps
CPU time 1354.93 seconds
Started Jul 21 06:10:46 PM PDT 24
Finished Jul 21 06:33:22 PM PDT 24
Peak memory 289572 kb
Host smart-7bebcf03-7de9-47a0-b4a1-400e3681f4ff
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218958648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3218958648
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1989056129
Short name T621
Test name
Test status
Simulation time 71227241642 ps
CPU time 1426.28 seconds
Started Jul 21 06:10:52 PM PDT 24
Finished Jul 21 06:34:39 PM PDT 24
Peak memory 289048 kb
Host smart-9c9d28d6-8110-4854-8afa-113a0cce5891
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989056129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1989056129
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.800723640
Short name T191
Test name
Test status
Simulation time 6754007553 ps
CPU time 187.08 seconds
Started Jul 21 06:10:50 PM PDT 24
Finished Jul 21 06:13:57 PM PDT 24
Peak memory 256456 kb
Host smart-772ad0a9-5d4c-4884-92d9-0b47a60ed747
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80072
3640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.800723640
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.832642717
Short name T465
Test name
Test status
Simulation time 3808858060 ps
CPU time 29.98 seconds
Started Jul 21 06:10:51 PM PDT 24
Finished Jul 21 06:11:21 PM PDT 24
Peak memory 256552 kb
Host smart-96c988e8-cc4a-4745-9d39-c785e5ece95f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83264
2717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.832642717
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1681894140
Short name T346
Test name
Test status
Simulation time 48331004059 ps
CPU time 1293.76 seconds
Started Jul 21 06:10:53 PM PDT 24
Finished Jul 21 06:32:27 PM PDT 24
Peak memory 270784 kb
Host smart-1e804e5f-147d-4733-8984-164d59142f9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681894140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1681894140
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.910080733
Short name T509
Test name
Test status
Simulation time 66189145664 ps
CPU time 878.68 seconds
Started Jul 21 06:10:52 PM PDT 24
Finished Jul 21 06:25:31 PM PDT 24
Peak memory 273608 kb
Host smart-32b36656-ffde-4ae3-b4f6-3beb8a7e117b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=910080733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.910080733
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.3081378625
Short name T313
Test name
Test status
Simulation time 5096358586 ps
CPU time 108.54 seconds
Started Jul 21 06:10:50 PM PDT 24
Finished Jul 21 06:12:39 PM PDT 24
Peak memory 249076 kb
Host smart-14b82f6b-3c51-4ae5-bc64-e509c52bf6a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081378625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3081378625
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2339426894
Short name T75
Test name
Test status
Simulation time 1309899892 ps
CPU time 29.67 seconds
Started Jul 21 06:10:50 PM PDT 24
Finished Jul 21 06:11:20 PM PDT 24
Peak memory 256628 kb
Host smart-4ebddf33-69e3-4e9e-8be5-e753750ca0ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23394
26894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2339426894
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.770118398
Short name T472
Test name
Test status
Simulation time 4141315709 ps
CPU time 63.62 seconds
Started Jul 21 06:10:49 PM PDT 24
Finished Jul 21 06:11:53 PM PDT 24
Peak memory 257052 kb
Host smart-585a5790-3560-46a5-b2b4-224dbf9cf499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77011
8398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.770118398
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.2625386820
Short name T546
Test name
Test status
Simulation time 151887409 ps
CPU time 15.55 seconds
Started Jul 21 06:10:50 PM PDT 24
Finished Jul 21 06:11:06 PM PDT 24
Peak memory 255944 kb
Host smart-2de4ccec-9c81-4259-933f-2f6840b48df3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26253
86820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.2625386820
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.1015810412
Short name T661
Test name
Test status
Simulation time 1115070145 ps
CPU time 33.84 seconds
Started Jul 21 06:10:45 PM PDT 24
Finished Jul 21 06:11:19 PM PDT 24
Peak memory 249284 kb
Host smart-c3e8d71c-2700-4efb-a449-266127df36dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10158
10412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.1015810412
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3878853196
Short name T290
Test name
Test status
Simulation time 55757549524 ps
CPU time 3356.53 seconds
Started Jul 21 06:10:52 PM PDT 24
Finished Jul 21 07:06:50 PM PDT 24
Peak memory 297964 kb
Host smart-23c368b8-a8ef-4b39-9633-1fdbc1dd2980
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878853196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3878853196
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.2004201795
Short name T15
Test name
Test status
Simulation time 12511425310 ps
CPU time 760.99 seconds
Started Jul 21 06:10:49 PM PDT 24
Finished Jul 21 06:23:31 PM PDT 24
Peak memory 268568 kb
Host smart-ca5abb30-c59b-4e56-b66e-42635fc54dec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004201795 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.2004201795
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.4041253225
Short name T499
Test name
Test status
Simulation time 220113352701 ps
CPU time 3562.68 seconds
Started Jul 21 06:10:59 PM PDT 24
Finished Jul 21 07:10:22 PM PDT 24
Peak memory 289884 kb
Host smart-9b2ba7a4-5a30-4bdf-9bf1-4042956aa6da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041253225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.4041253225
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1134561548
Short name T291
Test name
Test status
Simulation time 4838500939 ps
CPU time 86.03 seconds
Started Jul 21 06:10:57 PM PDT 24
Finished Jul 21 06:12:25 PM PDT 24
Peak memory 251088 kb
Host smart-bbd1af77-6ce1-414f-be19-069ba7edc2e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11345
61548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1134561548
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1353139215
Short name T642
Test name
Test status
Simulation time 153294232 ps
CPU time 11.19 seconds
Started Jul 21 06:11:01 PM PDT 24
Finished Jul 21 06:11:13 PM PDT 24
Peak memory 248544 kb
Host smart-3833aa38-d656-4919-b45a-958ca545037d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13531
39215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1353139215
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.482042746
Short name T327
Test name
Test status
Simulation time 59950063007 ps
CPU time 1555.5 seconds
Started Jul 21 06:10:58 PM PDT 24
Finished Jul 21 06:36:54 PM PDT 24
Peak memory 273316 kb
Host smart-8107d824-b12c-422a-b1fa-07c938eca60c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482042746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.482042746
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.108417122
Short name T105
Test name
Test status
Simulation time 60310721958 ps
CPU time 3065.61 seconds
Started Jul 21 06:10:58 PM PDT 24
Finished Jul 21 07:02:05 PM PDT 24
Peak memory 290092 kb
Host smart-b83028db-8c87-443a-ba40-f7c95b306042
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108417122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.108417122
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.979606978
Short name T679
Test name
Test status
Simulation time 15361121509 ps
CPU time 174.51 seconds
Started Jul 21 06:10:57 PM PDT 24
Finished Jul 21 06:13:52 PM PDT 24
Peak memory 256880 kb
Host smart-aee88ee3-8c28-4469-820f-7e4115de8ba1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979606978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.979606978
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.678789674
Short name T529
Test name
Test status
Simulation time 2181830798 ps
CPU time 47.18 seconds
Started Jul 21 06:10:56 PM PDT 24
Finished Jul 21 06:11:44 PM PDT 24
Peak memory 256536 kb
Host smart-947b4635-99c1-4990-b9ed-0d8433d98d82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67878
9674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.678789674
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.278367082
Short name T81
Test name
Test status
Simulation time 2063010817 ps
CPU time 46.61 seconds
Started Jul 21 06:10:58 PM PDT 24
Finished Jul 21 06:11:45 PM PDT 24
Peak memory 256540 kb
Host smart-8cc93a31-91b3-42f2-b379-8e1af938c57d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27836
7082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.278367082
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.3529255736
Short name T656
Test name
Test status
Simulation time 4534217840 ps
CPU time 60.6 seconds
Started Jul 21 06:10:57 PM PDT 24
Finished Jul 21 06:11:59 PM PDT 24
Peak memory 250156 kb
Host smart-8821383d-60b9-4753-bdc7-ac879822956a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35292
55736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3529255736
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1172355714
Short name T186
Test name
Test status
Simulation time 156069759 ps
CPU time 11.14 seconds
Started Jul 21 06:10:48 PM PDT 24
Finished Jul 21 06:11:00 PM PDT 24
Peak memory 249528 kb
Host smart-40488302-d167-480c-9937-ac65e9f140dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11723
55714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1172355714
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.2250518087
Short name T20
Test name
Test status
Simulation time 35533325535 ps
CPU time 3532.96 seconds
Started Jul 21 06:10:58 PM PDT 24
Finished Jul 21 07:09:52 PM PDT 24
Peak memory 322552 kb
Host smart-23f7f23f-71b1-48df-bbaf-6311da4b5a41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250518087 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.2250518087
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2848270745
Short name T452
Test name
Test status
Simulation time 56397218182 ps
CPU time 3252.66 seconds
Started Jul 21 06:11:02 PM PDT 24
Finished Jul 21 07:05:15 PM PDT 24
Peak memory 289840 kb
Host smart-bb87f8f2-12a5-4a26-a87b-c33d4e509ce2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848270745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2848270745
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.2967362127
Short name T682
Test name
Test status
Simulation time 5209139544 ps
CPU time 155.16 seconds
Started Jul 21 06:11:04 PM PDT 24
Finished Jul 21 06:13:39 PM PDT 24
Peak memory 256828 kb
Host smart-32953ca1-5320-4844-ab8e-4e0dd54810ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29673
62127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2967362127
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.1722061565
Short name T492
Test name
Test status
Simulation time 52456842 ps
CPU time 6.57 seconds
Started Jul 21 06:11:03 PM PDT 24
Finished Jul 21 06:11:10 PM PDT 24
Peak memory 254684 kb
Host smart-6b5a4d23-1605-4e8b-8140-52e216c35d67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17220
61565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.1722061565
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.2376397809
Short name T615
Test name
Test status
Simulation time 29865074025 ps
CPU time 1615.71 seconds
Started Jul 21 06:11:02 PM PDT 24
Finished Jul 21 06:37:58 PM PDT 24
Peak memory 273668 kb
Host smart-836e4017-3b7f-4bb9-a82d-c7b7e334f47b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376397809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2376397809
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.201193531
Short name T486
Test name
Test status
Simulation time 97573904803 ps
CPU time 1823.05 seconds
Started Jul 21 06:11:04 PM PDT 24
Finished Jul 21 06:41:28 PM PDT 24
Peak memory 289596 kb
Host smart-9b4c6dcd-b50b-492f-9b72-44906d23ad35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201193531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.201193531
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2038141739
Short name T645
Test name
Test status
Simulation time 12544781660 ps
CPU time 533.66 seconds
Started Jul 21 06:11:05 PM PDT 24
Finished Jul 21 06:19:59 PM PDT 24
Peak memory 249284 kb
Host smart-c34fc389-67a4-40dc-8411-33c4cffaa25d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038141739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2038141739
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.236588733
Short name T496
Test name
Test status
Simulation time 205684739 ps
CPU time 18.51 seconds
Started Jul 21 06:10:57 PM PDT 24
Finished Jul 21 06:11:17 PM PDT 24
Peak memory 248948 kb
Host smart-a6691186-0509-4f3b-a35a-5cd770a3c77f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23658
8733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.236588733
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.746555370
Short name T312
Test name
Test status
Simulation time 905527551 ps
CPU time 52.15 seconds
Started Jul 21 06:10:57 PM PDT 24
Finished Jul 21 06:11:51 PM PDT 24
Peak memory 249308 kb
Host smart-ff337212-80d8-4fd4-974d-2d93a8461eee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74655
5370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.746555370
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.3314848602
Short name T102
Test name
Test status
Simulation time 826274535 ps
CPU time 59.03 seconds
Started Jul 21 06:11:03 PM PDT 24
Finished Jul 21 06:12:02 PM PDT 24
Peak memory 256456 kb
Host smart-4045aff7-7275-4641-bb75-6a96c23f1e45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33148
48602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3314848602
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3579620859
Short name T366
Test name
Test status
Simulation time 1088216858 ps
CPU time 68.73 seconds
Started Jul 21 06:10:57 PM PDT 24
Finished Jul 21 06:12:07 PM PDT 24
Peak memory 257076 kb
Host smart-4f660564-6e53-4ebd-ba63-389a6a4b86b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35796
20859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3579620859
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.428696931
Short name T561
Test name
Test status
Simulation time 3017802217 ps
CPU time 247.96 seconds
Started Jul 21 06:11:04 PM PDT 24
Finished Jul 21 06:15:12 PM PDT 24
Peak memory 257244 kb
Host smart-96635aee-6c37-463b-876e-fb735cbffe0d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428696931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_han
dler_stress_all.428696931
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1505357491
Short name T115
Test name
Test status
Simulation time 25613065756 ps
CPU time 1465.49 seconds
Started Jul 21 06:11:09 PM PDT 24
Finished Jul 21 06:35:35 PM PDT 24
Peak memory 289804 kb
Host smart-595052ac-d108-452e-aff5-275515b5c9e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505357491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1505357491
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.4202630917
Short name T567
Test name
Test status
Simulation time 348090675 ps
CPU time 31.32 seconds
Started Jul 21 06:11:08 PM PDT 24
Finished Jul 21 06:11:39 PM PDT 24
Peak memory 257200 kb
Host smart-f4017d46-959b-4485-9969-8ac919f3b00f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42026
30917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.4202630917
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2735972388
Short name T280
Test name
Test status
Simulation time 497004031 ps
CPU time 10.3 seconds
Started Jul 21 06:11:10 PM PDT 24
Finished Jul 21 06:11:20 PM PDT 24
Peak memory 253972 kb
Host smart-1fd033ad-d9b5-4654-9930-e9c2348f2214
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27359
72388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2735972388
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1095552270
Short name T348
Test name
Test status
Simulation time 243167171582 ps
CPU time 1770.77 seconds
Started Jul 21 06:11:09 PM PDT 24
Finished Jul 21 06:40:40 PM PDT 24
Peak memory 273592 kb
Host smart-85c622b1-747d-4f28-8be1-c44ababe113a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095552270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1095552270
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1476856096
Short name T619
Test name
Test status
Simulation time 72508335788 ps
CPU time 2393.67 seconds
Started Jul 21 06:11:15 PM PDT 24
Finished Jul 21 06:51:10 PM PDT 24
Peak memory 288692 kb
Host smart-131e769c-5666-4eb6-9930-735c59ef441d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476856096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1476856096
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.797034729
Short name T339
Test name
Test status
Simulation time 22207114052 ps
CPU time 121.61 seconds
Started Jul 21 06:11:09 PM PDT 24
Finished Jul 21 06:13:12 PM PDT 24
Peak memory 248884 kb
Host smart-91a99113-69ad-4458-b5ba-9ed2b11cd842
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797034729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.797034729
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.259056259
Short name T484
Test name
Test status
Simulation time 697762837 ps
CPU time 12.88 seconds
Started Jul 21 06:11:10 PM PDT 24
Finished Jul 21 06:11:23 PM PDT 24
Peak memory 248892 kb
Host smart-03141ec0-513f-456e-90fe-113ec21d62c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25905
6259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.259056259
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2520896559
Short name T94
Test name
Test status
Simulation time 1845912605 ps
CPU time 25.81 seconds
Started Jul 21 06:11:11 PM PDT 24
Finished Jul 21 06:11:37 PM PDT 24
Peak memory 256952 kb
Host smart-9beacf19-c84b-41fa-abd2-e82b384f18f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25208
96559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2520896559
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3051119889
Short name T633
Test name
Test status
Simulation time 1446149842 ps
CPU time 30.05 seconds
Started Jul 21 06:11:09 PM PDT 24
Finished Jul 21 06:11:39 PM PDT 24
Peak memory 256636 kb
Host smart-715b9008-9135-4fdd-a9af-3f8ad823dad3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30511
19889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3051119889
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2432060994
Short name T653
Test name
Test status
Simulation time 14779973479 ps
CPU time 72.2 seconds
Started Jul 21 06:11:01 PM PDT 24
Finished Jul 21 06:12:14 PM PDT 24
Peak memory 256360 kb
Host smart-3660af9e-02ae-48a5-a08f-0212e50f3323
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24320
60994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2432060994
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.3200785429
Short name T91
Test name
Test status
Simulation time 632721873 ps
CPU time 34.85 seconds
Started Jul 21 06:11:14 PM PDT 24
Finished Jul 21 06:11:49 PM PDT 24
Peak memory 256564 kb
Host smart-060fc201-1193-4a28-86f7-2b47e654ea16
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200785429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.3200785429
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1589171303
Short name T424
Test name
Test status
Simulation time 97969110686 ps
CPU time 982.67 seconds
Started Jul 21 06:11:21 PM PDT 24
Finished Jul 21 06:27:44 PM PDT 24
Peak memory 273748 kb
Host smart-7cd5999e-ebf0-407e-9ef0-5005f3ef2487
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589171303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1589171303
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3293050623
Short name T243
Test name
Test status
Simulation time 1833024601 ps
CPU time 50.63 seconds
Started Jul 21 06:11:14 PM PDT 24
Finished Jul 21 06:12:05 PM PDT 24
Peak memory 256464 kb
Host smart-3f6ce900-c0f9-4716-9e09-36d46dfef023
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32930
50623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3293050623
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1349856313
Short name T383
Test name
Test status
Simulation time 1518979703 ps
CPU time 45.39 seconds
Started Jul 21 06:11:15 PM PDT 24
Finished Jul 21 06:12:00 PM PDT 24
Peak memory 256592 kb
Host smart-de9e1dfa-2b34-47c6-b894-6fe9274ff558
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13498
56313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1349856313
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.4062617894
Short name T585
Test name
Test status
Simulation time 8529609754 ps
CPU time 855.71 seconds
Started Jul 21 06:11:20 PM PDT 24
Finished Jul 21 06:25:37 PM PDT 24
Peak memory 273124 kb
Host smart-61a1747a-82f3-4006-9e38-3e62f9c8e444
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062617894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.4062617894
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.311429786
Short name T451
Test name
Test status
Simulation time 72006723554 ps
CPU time 2037.35 seconds
Started Jul 21 06:11:22 PM PDT 24
Finished Jul 21 06:45:20 PM PDT 24
Peak memory 273784 kb
Host smart-276af8e1-4f7f-49e1-b076-77e852a3545e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311429786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.311429786
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.2873245592
Short name T316
Test name
Test status
Simulation time 4955713949 ps
CPU time 189.24 seconds
Started Jul 21 06:11:23 PM PDT 24
Finished Jul 21 06:14:33 PM PDT 24
Peak memory 248836 kb
Host smart-89ddeb69-40b4-42fe-b9ea-406d8c7bc45f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873245592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.2873245592
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.235505262
Short name T699
Test name
Test status
Simulation time 368887445 ps
CPU time 24.44 seconds
Started Jul 21 06:11:17 PM PDT 24
Finished Jul 21 06:11:42 PM PDT 24
Peak memory 249000 kb
Host smart-a84d0505-c638-4984-9e16-2b6ddf607b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23550
5262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.235505262
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.852491386
Short name T485
Test name
Test status
Simulation time 8033639143 ps
CPU time 49.19 seconds
Started Jul 21 06:11:15 PM PDT 24
Finished Jul 21 06:12:05 PM PDT 24
Peak memory 256096 kb
Host smart-92ab3025-f2d4-4fe9-8ea6-4b19c3f0549c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85249
1386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.852491386
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3537469901
Short name T513
Test name
Test status
Simulation time 177644557 ps
CPU time 9.23 seconds
Started Jul 21 06:11:22 PM PDT 24
Finished Jul 21 06:11:31 PM PDT 24
Peak memory 251812 kb
Host smart-47b7d3a4-d6b1-49ff-8fa9-ff7f379ed9f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35374
69901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3537469901
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.4216362876
Short name T579
Test name
Test status
Simulation time 60763684 ps
CPU time 4.83 seconds
Started Jul 21 06:11:17 PM PDT 24
Finished Jul 21 06:11:22 PM PDT 24
Peak memory 251388 kb
Host smart-e6a7a48f-a3cf-420d-81f0-4c9018d5f923
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42163
62876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.4216362876
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1915628859
Short name T277
Test name
Test status
Simulation time 53595937023 ps
CPU time 1832.53 seconds
Started Jul 21 06:11:20 PM PDT 24
Finished Jul 21 06:41:53 PM PDT 24
Peak memory 300136 kb
Host smart-c421b39f-dc19-4ab2-a04b-26dfff14bee5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915628859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1915628859
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.4148368662
Short name T559
Test name
Test status
Simulation time 56984705033 ps
CPU time 2051.42 seconds
Started Jul 21 06:11:23 PM PDT 24
Finished Jul 21 06:45:35 PM PDT 24
Peak memory 289856 kb
Host smart-0ecc39f9-08cf-4c99-9818-b4896c24e0b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148368662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.4148368662
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.1663989053
Short name T532
Test name
Test status
Simulation time 636720754 ps
CPU time 15.94 seconds
Started Jul 21 06:11:22 PM PDT 24
Finished Jul 21 06:11:38 PM PDT 24
Peak memory 255612 kb
Host smart-013ecc6c-20c2-4ad2-99c0-cc8f0e9036c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16639
89053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.1663989053
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.3143721405
Short name T574
Test name
Test status
Simulation time 1719764268 ps
CPU time 32.29 seconds
Started Jul 21 06:11:22 PM PDT 24
Finished Jul 21 06:11:54 PM PDT 24
Peak memory 255436 kb
Host smart-c0ac791c-fd5c-44da-bf51-41db85ba10cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31437
21405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.3143721405
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3648019418
Short name T35
Test name
Test status
Simulation time 36181458973 ps
CPU time 1051.2 seconds
Started Jul 21 06:11:20 PM PDT 24
Finished Jul 21 06:28:52 PM PDT 24
Peak memory 273592 kb
Host smart-b1b028c1-df29-403e-a5d8-a5888d9370a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648019418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3648019418
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.4198521229
Short name T434
Test name
Test status
Simulation time 22871013370 ps
CPU time 1448.79 seconds
Started Jul 21 06:11:28 PM PDT 24
Finished Jul 21 06:35:37 PM PDT 24
Peak memory 273084 kb
Host smart-f53081e7-7fad-4924-b923-6a0f7c18d9cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198521229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.4198521229
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2350114947
Short name T319
Test name
Test status
Simulation time 44042561694 ps
CPU time 466.91 seconds
Started Jul 21 06:11:24 PM PDT 24
Finished Jul 21 06:19:12 PM PDT 24
Peak memory 249108 kb
Host smart-0710883b-3f2f-4142-8482-3d1a0f3ac50c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350114947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2350114947
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.760519824
Short name T663
Test name
Test status
Simulation time 1750715779 ps
CPU time 34.66 seconds
Started Jul 21 06:11:20 PM PDT 24
Finished Jul 21 06:11:56 PM PDT 24
Peak memory 256552 kb
Host smart-79068590-d534-4fb6-a468-98e43250bc66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76051
9824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.760519824
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2706365572
Short name T467
Test name
Test status
Simulation time 400694483 ps
CPU time 33.16 seconds
Started Jul 21 06:11:20 PM PDT 24
Finished Jul 21 06:11:54 PM PDT 24
Peak memory 248956 kb
Host smart-b3f94481-adac-4408-96a9-de1596846934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27063
65572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2706365572
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.3303052599
Short name T288
Test name
Test status
Simulation time 2627214966 ps
CPU time 38.02 seconds
Started Jul 21 06:11:21 PM PDT 24
Finished Jul 21 06:12:00 PM PDT 24
Peak memory 256564 kb
Host smart-dd5c07e2-43b8-47a2-908c-75d04cfde630
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33030
52599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3303052599
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.3417244723
Short name T396
Test name
Test status
Simulation time 221776062 ps
CPU time 15.97 seconds
Started Jul 21 06:11:21 PM PDT 24
Finished Jul 21 06:11:37 PM PDT 24
Peak memory 255376 kb
Host smart-b8747efa-3403-44da-9738-3806472afcfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34172
44723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.3417244723
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.3175632028
Short name T65
Test name
Test status
Simulation time 160581145 ps
CPU time 14.08 seconds
Started Jul 21 06:11:27 PM PDT 24
Finished Jul 21 06:11:41 PM PDT 24
Peak memory 249012 kb
Host smart-27d5eb5e-7f34-45f5-b2a3-bdacce4321c4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175632028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.3175632028
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.2607347678
Short name T117
Test name
Test status
Simulation time 11728574223 ps
CPU time 652.86 seconds
Started Jul 21 06:11:28 PM PDT 24
Finished Jul 21 06:22:21 PM PDT 24
Peak memory 271568 kb
Host smart-9c13aa19-8eb7-403a-bc5f-1894b9386615
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607347678 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.2607347678
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.3353980508
Short name T72
Test name
Test status
Simulation time 5391620050 ps
CPU time 546.8 seconds
Started Jul 21 06:11:34 PM PDT 24
Finished Jul 21 06:20:41 PM PDT 24
Peak memory 273052 kb
Host smart-6d643699-9dd7-4839-90d8-73898fbaf8a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353980508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.3353980508
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1496468050
Short name T555
Test name
Test status
Simulation time 31545607145 ps
CPU time 271.1 seconds
Started Jul 21 06:11:33 PM PDT 24
Finished Jul 21 06:16:04 PM PDT 24
Peak memory 257356 kb
Host smart-b4433699-cd93-4ba7-909e-131ff6173730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14964
68050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1496468050
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3520032113
Short name T473
Test name
Test status
Simulation time 601702598 ps
CPU time 13.25 seconds
Started Jul 21 06:11:34 PM PDT 24
Finished Jul 21 06:11:47 PM PDT 24
Peak memory 249012 kb
Host smart-34d941f8-5890-4c9a-9024-16f95f50897a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35200
32113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3520032113
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3606372222
Short name T521
Test name
Test status
Simulation time 39464416509 ps
CPU time 2418.25 seconds
Started Jul 21 06:11:34 PM PDT 24
Finished Jul 21 06:51:53 PM PDT 24
Peak memory 273576 kb
Host smart-4a3182ca-c29d-49ec-973b-c61731249c53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606372222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3606372222
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2278653169
Short name T335
Test name
Test status
Simulation time 3785275747 ps
CPU time 160.22 seconds
Started Jul 21 06:11:39 PM PDT 24
Finished Jul 21 06:14:19 PM PDT 24
Peak memory 249056 kb
Host smart-94036a5b-c713-4eda-8189-c1b0dbad62d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278653169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2278653169
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.3275501171
Short name T440
Test name
Test status
Simulation time 5662277538 ps
CPU time 36.42 seconds
Started Jul 21 06:11:27 PM PDT 24
Finished Jul 21 06:12:04 PM PDT 24
Peak memory 257140 kb
Host smart-7cd4ac45-10fc-41af-8a6f-0f133fc5c3cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32755
01171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3275501171
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.3685376389
Short name T309
Test name
Test status
Simulation time 694636588 ps
CPU time 9.64 seconds
Started Jul 21 06:11:28 PM PDT 24
Finished Jul 21 06:11:38 PM PDT 24
Peak memory 252828 kb
Host smart-c7d452f6-3a41-443d-ad0e-3d996acc2212
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36853
76389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.3685376389
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1298286662
Short name T210
Test name
Test status
Simulation time 31164615 ps
CPU time 3.47 seconds
Started Jul 21 06:07:45 PM PDT 24
Finished Jul 21 06:07:48 PM PDT 24
Peak memory 249240 kb
Host smart-7da49b0a-f9ec-403a-8d5e-b2bf5acf22bb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1298286662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1298286662
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3300779034
Short name T570
Test name
Test status
Simulation time 54361749796 ps
CPU time 3085.77 seconds
Started Jul 21 06:07:46 PM PDT 24
Finished Jul 21 06:59:12 PM PDT 24
Peak memory 289332 kb
Host smart-c6fd18e5-c7e3-417a-a42e-e2822c113846
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300779034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3300779034
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.609386554
Short name T461
Test name
Test status
Simulation time 85269952 ps
CPU time 6.26 seconds
Started Jul 21 06:07:47 PM PDT 24
Finished Jul 21 06:07:53 PM PDT 24
Peak memory 248920 kb
Host smart-821ffab6-3bee-43bd-996e-bcadf43b2c62
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=609386554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.609386554
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3019077023
Short name T657
Test name
Test status
Simulation time 7867295573 ps
CPU time 83.53 seconds
Started Jul 21 06:07:43 PM PDT 24
Finished Jul 21 06:09:07 PM PDT 24
Peak memory 257212 kb
Host smart-bb4e10c6-eb8b-4de2-8d74-9742ba733e10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30190
77023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3019077023
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.1676450450
Short name T664
Test name
Test status
Simulation time 156186837 ps
CPU time 4.54 seconds
Started Jul 21 06:07:43 PM PDT 24
Finished Jul 21 06:07:48 PM PDT 24
Peak memory 240352 kb
Host smart-c9368ee5-d8a5-4705-a91d-6cd0a9de5fc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16764
50450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1676450450
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.3434585257
Short name T557
Test name
Test status
Simulation time 46685747914 ps
CPU time 2402.58 seconds
Started Jul 21 06:07:46 PM PDT 24
Finished Jul 21 06:47:49 PM PDT 24
Peak memory 283584 kb
Host smart-7823d6a9-848a-4410-bb52-c1b3385e3fca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434585257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.3434585257
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.3786939499
Short name T688
Test name
Test status
Simulation time 5990082757 ps
CPU time 760 seconds
Started Jul 21 06:07:42 PM PDT 24
Finished Jul 21 06:20:22 PM PDT 24
Peak memory 273632 kb
Host smart-0054616c-0a2e-48ca-9c31-9e27df6dea61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786939499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3786939499
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1122721005
Short name T395
Test name
Test status
Simulation time 1062330356 ps
CPU time 33.06 seconds
Started Jul 21 06:07:46 PM PDT 24
Finished Jul 21 06:08:19 PM PDT 24
Peak memory 248948 kb
Host smart-91b91de0-7e22-401d-8e3c-03886a415b47
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11227
21005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1122721005
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3640381758
Short name T188
Test name
Test status
Simulation time 54118364 ps
CPU time 4.77 seconds
Started Jul 21 06:07:44 PM PDT 24
Finished Jul 21 06:07:50 PM PDT 24
Peak memory 239916 kb
Host smart-b3784702-cd9f-4b44-acc5-d7f5ee280e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36403
81758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3640381758
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2248699337
Short name T524
Test name
Test status
Simulation time 1390751049 ps
CPU time 47.04 seconds
Started Jul 21 06:07:46 PM PDT 24
Finished Jul 21 06:08:33 PM PDT 24
Peak memory 257052 kb
Host smart-8d70685e-e8e4-4714-baac-ba66fdc629b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22486
99337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2248699337
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.426354562
Short name T202
Test name
Test status
Simulation time 212443332 ps
CPU time 20.96 seconds
Started Jul 21 06:07:43 PM PDT 24
Finished Jul 21 06:08:05 PM PDT 24
Peak memory 256184 kb
Host smart-720f1e63-26cc-4d70-9b22-ac1cd94e87d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42635
4562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.426354562
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.401250500
Short name T61
Test name
Test status
Simulation time 121610256527 ps
CPU time 2948.19 seconds
Started Jul 21 06:07:48 PM PDT 24
Finished Jul 21 06:56:57 PM PDT 24
Peak memory 322900 kb
Host smart-c80e150a-0ce5-475b-9b0d-30faa63f97d5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401250500 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.401250500
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2814319715
Short name T214
Test name
Test status
Simulation time 160678086 ps
CPU time 3.53 seconds
Started Jul 21 06:07:49 PM PDT 24
Finished Jul 21 06:07:53 PM PDT 24
Peak memory 249192 kb
Host smart-0460517f-7b6d-4e34-8278-b0fda207b3c7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2814319715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2814319715
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.4202686234
Short name T79
Test name
Test status
Simulation time 198087900911 ps
CPU time 2796.66 seconds
Started Jul 21 06:07:51 PM PDT 24
Finished Jul 21 06:54:28 PM PDT 24
Peak memory 289088 kb
Host smart-8336f55c-6198-459d-9963-1390b3099cc3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4202686234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.4202686234
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2789461328
Short name T189
Test name
Test status
Simulation time 734763892 ps
CPU time 32.46 seconds
Started Jul 21 06:07:52 PM PDT 24
Finished Jul 21 06:08:25 PM PDT 24
Peak memory 248920 kb
Host smart-04ae4531-fe0d-44af-a09e-f463fa7b0a7d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2789461328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2789461328
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.4018063827
Short name T443
Test name
Test status
Simulation time 1201377092 ps
CPU time 55.96 seconds
Started Jul 21 06:07:50 PM PDT 24
Finished Jul 21 06:08:46 PM PDT 24
Peak memory 257136 kb
Host smart-f41657ac-f4b3-4508-9c96-881ad60f470b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40180
63827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.4018063827
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1766231162
Short name T121
Test name
Test status
Simulation time 3353357175 ps
CPU time 23.36 seconds
Started Jul 21 06:07:49 PM PDT 24
Finished Jul 21 06:08:12 PM PDT 24
Peak memory 256300 kb
Host smart-fc1707be-4c8f-4293-962e-5fdcf5139d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17662
31162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1766231162
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.2138737664
Short name T507
Test name
Test status
Simulation time 19000962310 ps
CPU time 1114.79 seconds
Started Jul 21 06:07:51 PM PDT 24
Finished Jul 21 06:26:26 PM PDT 24
Peak memory 265448 kb
Host smart-b51117d1-6904-4a34-901a-32af9366020c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2138737664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.2138737664
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.2976791235
Short name T14
Test name
Test status
Simulation time 77066698429 ps
CPU time 2897.54 seconds
Started Jul 21 06:07:48 PM PDT 24
Finished Jul 21 06:56:06 PM PDT 24
Peak memory 289720 kb
Host smart-f709d195-a465-44e0-bc1b-416e7a69dba7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976791235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2976791235
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.3584734483
Short name T333
Test name
Test status
Simulation time 2371227971 ps
CPU time 101.45 seconds
Started Jul 21 06:07:51 PM PDT 24
Finished Jul 21 06:09:33 PM PDT 24
Peak memory 249040 kb
Host smart-aab28c1f-2843-4e07-8500-2d4f222da684
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584734483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.3584734483
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2913857825
Short name T370
Test name
Test status
Simulation time 634827251 ps
CPU time 13.36 seconds
Started Jul 21 06:07:50 PM PDT 24
Finished Jul 21 06:08:04 PM PDT 24
Peak memory 249024 kb
Host smart-ba9d558c-648d-45e1-9b09-631929ef5624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29138
57825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2913857825
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.4020499118
Short name T369
Test name
Test status
Simulation time 2005020667 ps
CPU time 45.56 seconds
Started Jul 21 06:07:50 PM PDT 24
Finished Jul 21 06:08:36 PM PDT 24
Peak memory 248356 kb
Host smart-6e7842b5-5383-46e6-8021-aa117d3d8ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40204
99118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.4020499118
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.2274733696
Short name T415
Test name
Test status
Simulation time 106492830 ps
CPU time 7.38 seconds
Started Jul 21 06:07:48 PM PDT 24
Finished Jul 21 06:07:56 PM PDT 24
Peak memory 248328 kb
Host smart-aa39c37a-3df1-4a72-a13f-e696fda3ff88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22747
33696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2274733696
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1979635547
Short name T372
Test name
Test status
Simulation time 897394254 ps
CPU time 21.45 seconds
Started Jul 21 06:07:47 PM PDT 24
Finished Jul 21 06:08:09 PM PDT 24
Peak memory 257080 kb
Host smart-4733476b-9b45-4692-b3f7-15e0599bd979
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19796
35547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1979635547
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2674748059
Short name T563
Test name
Test status
Simulation time 45960861606 ps
CPU time 1375.06 seconds
Started Jul 21 06:07:51 PM PDT 24
Finished Jul 21 06:30:47 PM PDT 24
Peak memory 289680 kb
Host smart-cef7e2a6-c1d0-440a-90f2-654fead556dd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674748059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2674748059
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.4184746578
Short name T185
Test name
Test status
Simulation time 55562311116 ps
CPU time 1784.85 seconds
Started Jul 21 06:07:48 PM PDT 24
Finished Jul 21 06:37:33 PM PDT 24
Peak memory 290184 kb
Host smart-1a14e503-b807-4fb4-a068-6e7526920b5f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184746578 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.4184746578
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.2590966352
Short name T208
Test name
Test status
Simulation time 17995533 ps
CPU time 2.71 seconds
Started Jul 21 06:07:56 PM PDT 24
Finished Jul 21 06:07:59 PM PDT 24
Peak memory 249320 kb
Host smart-3c256986-7c15-436a-a602-4ea705b74803
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2590966352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2590966352
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3200162948
Short name T587
Test name
Test status
Simulation time 16874412169 ps
CPU time 1461.3 seconds
Started Jul 21 06:07:55 PM PDT 24
Finished Jul 21 06:32:17 PM PDT 24
Peak memory 286488 kb
Host smart-4e6523b3-423a-4a31-8780-338889ae13b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200162948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3200162948
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2520728688
Short name T531
Test name
Test status
Simulation time 1654187093 ps
CPU time 6.25 seconds
Started Jul 21 06:07:55 PM PDT 24
Finished Jul 21 06:08:02 PM PDT 24
Peak memory 248936 kb
Host smart-38e3e403-96b1-40bb-befd-e8d66d067bd8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2520728688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2520728688
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.520692022
Short name T666
Test name
Test status
Simulation time 5468356218 ps
CPU time 197.26 seconds
Started Jul 21 06:07:57 PM PDT 24
Finished Jul 21 06:11:14 PM PDT 24
Peak memory 251000 kb
Host smart-c6e26af8-2466-43d4-93fa-d863bf7c98be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52069
2022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.520692022
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.554303254
Short name T242
Test name
Test status
Simulation time 2648483308 ps
CPU time 44.41 seconds
Started Jul 21 06:07:57 PM PDT 24
Finished Jul 21 06:08:42 PM PDT 24
Peak memory 249016 kb
Host smart-1b275533-453f-4672-aa34-24005be5ada1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55430
3254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.554303254
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1746666719
Short name T347
Test name
Test status
Simulation time 103023088924 ps
CPU time 1927.67 seconds
Started Jul 21 06:07:55 PM PDT 24
Finished Jul 21 06:40:04 PM PDT 24
Peak memory 273516 kb
Host smart-c796b83a-5267-4e25-8dd7-0e38bd9566ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746666719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1746666719
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.3769884053
Short name T543
Test name
Test status
Simulation time 8897869009 ps
CPU time 756.15 seconds
Started Jul 21 06:07:55 PM PDT 24
Finished Jul 21 06:20:31 PM PDT 24
Peak memory 273532 kb
Host smart-3f257fa3-7a71-4f73-b2df-ffe9b4504dd1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769884053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3769884053
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2931010069
Short name T251
Test name
Test status
Simulation time 45100493872 ps
CPU time 478.22 seconds
Started Jul 21 06:07:58 PM PDT 24
Finished Jul 21 06:15:57 PM PDT 24
Peak memory 249088 kb
Host smart-08d260f3-b66f-4748-a55b-ed5ae8bf3b6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931010069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2931010069
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.1611902566
Short name T230
Test name
Test status
Simulation time 147477818 ps
CPU time 10.87 seconds
Started Jul 21 06:07:58 PM PDT 24
Finished Jul 21 06:08:09 PM PDT 24
Peak memory 249016 kb
Host smart-e50cbd3a-f091-48f3-a4d9-27eff12a427b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16119
02566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.1611902566
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.4251884575
Short name T459
Test name
Test status
Simulation time 1697632058 ps
CPU time 44.46 seconds
Started Jul 21 06:07:57 PM PDT 24
Finished Jul 21 06:08:42 PM PDT 24
Peak memory 256700 kb
Host smart-06d9d0d2-df5a-4159-a83a-3c83264f303e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42518
84575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.4251884575
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.3416137454
Short name T450
Test name
Test status
Simulation time 1848543009 ps
CPU time 35.56 seconds
Started Jul 21 06:07:55 PM PDT 24
Finished Jul 21 06:08:30 PM PDT 24
Peak memory 248956 kb
Host smart-a6ca11b0-377c-4e6f-82b8-42a3dc9503b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34161
37454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3416137454
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2042187254
Short name T18
Test name
Test status
Simulation time 1298011888 ps
CPU time 43.21 seconds
Started Jul 21 06:07:50 PM PDT 24
Finished Jul 21 06:08:33 PM PDT 24
Peak memory 257204 kb
Host smart-b58fd2ae-00fa-4140-804b-a435617facda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20421
87254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2042187254
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1530676747
Short name T95
Test name
Test status
Simulation time 24376058590 ps
CPU time 2262.24 seconds
Started Jul 21 06:07:57 PM PDT 24
Finished Jul 21 06:45:39 PM PDT 24
Peak memory 306152 kb
Host smart-1d0275d1-0ebb-4ae1-90e4-6c68ab894451
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530676747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1530676747
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.4210685699
Short name T638
Test name
Test status
Simulation time 802021912110 ps
CPU time 8332.6 seconds
Started Jul 21 06:07:56 PM PDT 24
Finished Jul 21 08:26:50 PM PDT 24
Peak memory 333876 kb
Host smart-aba81fb6-05e9-45db-9541-333f2cacc4ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210685699 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.4210685699
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.1478444564
Short name T220
Test name
Test status
Simulation time 124363847 ps
CPU time 4.76 seconds
Started Jul 21 06:08:04 PM PDT 24
Finished Jul 21 06:08:09 PM PDT 24
Peak memory 249168 kb
Host smart-b26f7127-d435-47ac-8a13-4f889923c060
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1478444564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.1478444564
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.3292080229
Short name T428
Test name
Test status
Simulation time 57367959941 ps
CPU time 1096.22 seconds
Started Jul 21 06:07:56 PM PDT 24
Finished Jul 21 06:26:13 PM PDT 24
Peak memory 286604 kb
Host smart-3fb93e7e-49ff-49c9-8270-8a7e2dca0082
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292080229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.3292080229
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1200739269
Short name T668
Test name
Test status
Simulation time 2559877798 ps
CPU time 29.04 seconds
Started Jul 21 06:08:00 PM PDT 24
Finished Jul 21 06:08:29 PM PDT 24
Peak memory 249048 kb
Host smart-c2cf9cd6-5c99-4fa2-a1bc-d4c8b623ae75
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1200739269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1200739269
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.946046040
Short name T460
Test name
Test status
Simulation time 111948245 ps
CPU time 17.03 seconds
Started Jul 21 06:07:55 PM PDT 24
Finished Jul 21 06:08:12 PM PDT 24
Peak memory 256500 kb
Host smart-25fdcab3-6ab2-40c9-b861-3096f5b41457
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94604
6040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.946046040
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3366352753
Short name T2
Test name
Test status
Simulation time 1016213614 ps
CPU time 24.63 seconds
Started Jul 21 06:07:58 PM PDT 24
Finished Jul 21 06:08:23 PM PDT 24
Peak memory 249520 kb
Host smart-715b66e7-4feb-4be8-ae50-6ff4b7df6bc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33663
52753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3366352753
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.3005683685
Short name T343
Test name
Test status
Simulation time 64585927951 ps
CPU time 2096.99 seconds
Started Jul 21 06:08:02 PM PDT 24
Finished Jul 21 06:42:59 PM PDT 24
Peak memory 283480 kb
Host smart-2eb768c6-8369-4f4f-86a9-a3878bcf7e28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005683685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3005683685
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2676520266
Short name T4
Test name
Test status
Simulation time 17738266286 ps
CPU time 1387.36 seconds
Started Jul 21 06:08:00 PM PDT 24
Finished Jul 21 06:31:08 PM PDT 24
Peak memory 289704 kb
Host smart-cc3244d7-96a6-4953-8466-c1d904913b3d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676520266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2676520266
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3686483173
Short name T341
Test name
Test status
Simulation time 3336744494 ps
CPU time 131.81 seconds
Started Jul 21 06:07:58 PM PDT 24
Finished Jul 21 06:10:10 PM PDT 24
Peak memory 249056 kb
Host smart-911dc773-2e5e-43e5-8d08-9bb29a6f8551
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686483173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3686483173
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.2993125798
Short name T678
Test name
Test status
Simulation time 1202063709 ps
CPU time 25.59 seconds
Started Jul 21 06:07:56 PM PDT 24
Finished Jul 21 06:08:22 PM PDT 24
Peak memory 256556 kb
Host smart-f0c4f815-21cd-416a-94b8-2b49c200e74c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29931
25798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2993125798
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3661500333
Short name T569
Test name
Test status
Simulation time 7423211971 ps
CPU time 69.09 seconds
Started Jul 21 06:07:55 PM PDT 24
Finished Jul 21 06:09:05 PM PDT 24
Peak memory 249112 kb
Host smart-3bf9d41c-1713-4c3a-b64d-9b7c44210464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36615
00333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3661500333
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.4108946200
Short name T284
Test name
Test status
Simulation time 1232840969 ps
CPU time 41.97 seconds
Started Jul 21 06:07:56 PM PDT 24
Finished Jul 21 06:08:38 PM PDT 24
Peak memory 256264 kb
Host smart-1adbb76d-7abe-4b84-b5da-42122a5e5d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41089
46200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.4108946200
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.721662987
Short name T478
Test name
Test status
Simulation time 187466787 ps
CPU time 9.25 seconds
Started Jul 21 06:07:57 PM PDT 24
Finished Jul 21 06:08:06 PM PDT 24
Peak memory 255812 kb
Host smart-491b8909-3538-4cc3-bd04-b8f0e034e2ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72166
2987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.721662987
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.386422188
Short name T282
Test name
Test status
Simulation time 56677676352 ps
CPU time 1408.86 seconds
Started Jul 21 06:08:00 PM PDT 24
Finished Jul 21 06:31:29 PM PDT 24
Peak memory 289600 kb
Host smart-83878040-ecb3-437f-8df9-4a4cfce88532
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386422188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.386422188
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1686878655
Short name T209
Test name
Test status
Simulation time 288175833 ps
CPU time 3.75 seconds
Started Jul 21 06:08:07 PM PDT 24
Finished Jul 21 06:08:11 PM PDT 24
Peak memory 249276 kb
Host smart-6d2c17d6-019c-4149-a6fc-65eaa15c4343
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1686878655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1686878655
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1144944441
Short name T655
Test name
Test status
Simulation time 106320489821 ps
CPU time 2705.38 seconds
Started Jul 21 06:08:06 PM PDT 24
Finished Jul 21 06:53:12 PM PDT 24
Peak memory 289848 kb
Host smart-a93a7a01-05e9-4cb4-927b-687a16b59c33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144944441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1144944441
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.2220962776
Short name T603
Test name
Test status
Simulation time 2428919750 ps
CPU time 27.85 seconds
Started Jul 21 06:08:07 PM PDT 24
Finished Jul 21 06:08:35 PM PDT 24
Peak memory 249048 kb
Host smart-3f7c1373-9e34-4bf2-ab81-3dd66f2fa585
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2220962776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2220962776
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3669114199
Short name T409
Test name
Test status
Simulation time 5367277377 ps
CPU time 168.79 seconds
Started Jul 21 06:08:00 PM PDT 24
Finished Jul 21 06:10:49 PM PDT 24
Peak memory 256788 kb
Host smart-51ef746b-fbfb-4969-991e-bf62826a49ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36691
14199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3669114199
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2541242016
Short name T643
Test name
Test status
Simulation time 3619865995 ps
CPU time 53.6 seconds
Started Jul 21 06:08:02 PM PDT 24
Finished Jul 21 06:08:56 PM PDT 24
Peak memory 249048 kb
Host smart-4ed7c1d1-6a95-417f-b774-529bb5246dc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25412
42016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2541242016
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2892038884
Short name T632
Test name
Test status
Simulation time 18035009866 ps
CPU time 1404.8 seconds
Started Jul 21 06:08:07 PM PDT 24
Finished Jul 21 06:31:32 PM PDT 24
Peak memory 289936 kb
Host smart-1aa2ad3a-702e-4072-876f-96b8cccd28dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892038884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2892038884
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3042867038
Short name T340
Test name
Test status
Simulation time 13245660206 ps
CPU time 562.25 seconds
Started Jul 21 06:08:06 PM PDT 24
Finished Jul 21 06:17:29 PM PDT 24
Peak memory 248924 kb
Host smart-7f2d99e3-fd20-4508-a246-1c0e63e66b54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042867038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3042867038
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.991732429
Short name T41
Test name
Test status
Simulation time 1146945000 ps
CPU time 37.61 seconds
Started Jul 21 06:08:02 PM PDT 24
Finished Jul 21 06:08:40 PM PDT 24
Peak memory 249016 kb
Host smart-c9a49d2f-95aa-46a9-914a-820637247316
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99173
2429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.991732429
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1486684704
Short name T650
Test name
Test status
Simulation time 2664980864 ps
CPU time 58.05 seconds
Started Jul 21 06:08:01 PM PDT 24
Finished Jul 21 06:08:59 PM PDT 24
Peak memory 248688 kb
Host smart-43542809-9901-4945-9188-d0574044bc44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14866
84704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1486684704
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.3124672959
Short name T631
Test name
Test status
Simulation time 536257848 ps
CPU time 14.45 seconds
Started Jul 21 06:08:07 PM PDT 24
Finished Jul 21 06:08:22 PM PDT 24
Peak memory 248508 kb
Host smart-83b1e83d-57b3-4511-8858-8027b8d69d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31246
72959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.3124672959
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.1121257697
Short name T635
Test name
Test status
Simulation time 1019335803 ps
CPU time 61.77 seconds
Started Jul 21 06:08:04 PM PDT 24
Finished Jul 21 06:09:06 PM PDT 24
Peak memory 256884 kb
Host smart-5c333464-6ff9-4ce7-9cf2-0acc11cc26be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11212
57697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1121257697
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2984539014
Short name T66
Test name
Test status
Simulation time 8683472247 ps
CPU time 241.45 seconds
Started Jul 21 06:08:06 PM PDT 24
Finished Jul 21 06:12:07 PM PDT 24
Peak memory 257220 kb
Host smart-1010db02-188c-4659-86a4-88f69e1c2564
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984539014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2984539014
Directory /workspace/9.alert_handler_stress_all/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%