Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T19
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T48,T218,T219
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14041	0	0
DisabledNoTrigBkwd_A	2147483647	813878	0	0
DisabledNoTrigFwd_A	2147483647	1610159605	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14041	0	0
T17	344499	0	0	0
T18	113568	0	0	0
T23	591683	0	0	0
T48	2440	222	0	0
T49	11268	0	0	0
T50	38998	0	0	0
T51	60565	0	0	0
T58	330608	0	0	0
T86	176970	0	0	0
T87	75404	0	0	0
T88	48728	0	0	0
T91	92722	0	0	0
T124	2484	272	0	0
T125	146323	0	0	0
T218	5774	768	0	0
T219	1247	424	0	0
T220	0	961	0	0
T221	0	600	0	0
T222	0	575	0	0
T223	0	833	0	0
T224	0	1624	0	0
T225	0	672	0	0
T226	0	582	0	0
T227	0	956	0	0
T228	0	336	0	0
T229	0	399	0	0
T230	0	238	0	0
T231	0	293	0	0
T232	0	1917	0	0
T233	0	718	0	0
T234	0	746	0	0
T235	0	905	0	0
T236	20981	0	0	0
T237	344109	0	0	0
T238	42565	0	0	0
T239	253371	0	0	0
T240	815555	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	813878	0	0
T2	357412	192	0	0
T3	1548741	2934	0	0
T4	1159830	1939	0	0
T5	1142916	331	0	0
T6	0	1	0	0
T13	2310280	5798	0	0
T14	387075	2166	0	0
T15	868527	1488	0	0
T16	0	17392	0	0
T19	24048	0	0	0
T20	212688	8	0	0
T21	242368	74	0	0
T22	111112	0	0	0
T23	0	186	0	0
T25	109850	77	0	0
T46	258774	90	0	0
T47	0	56	0	0
T49	0	3	0	0
T50	0	10	0	0
T51	0	24	0	0
T52	203496	0	0	0
T53	34057	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1610159605	0	0
T1	153868	8893	0	0
T2	1429648	1053959	0	0
T3	2064988	1716737	0	0
T4	1546440	1162379	0	0
T5	1142916	864154	0	0
T13	2310280	1725555	0	0
T19	32064	31808	0	0
T20	283584	218098	0	0
T21	242368	57172	0	0
T22	111112	83662	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T19,T4
1	1	Covered	T2,T3,T20

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T48,T223,T225
1	1	Covered	T2,T3,T20

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T20

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	733097492	2364	0	0
DisabledNoTrigBkwd_A	733097492	264165	0	0
DisabledNoTrigFwd_A	733097492	373851918	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	2364	0	0
T17	344499	0	0	0
T23	591683	0	0	0
T48	2440	222	0	0
T49	11268	0	0	0
T50	38998	0	0	0
T51	60565	0	0	0
T86	176970	0	0	0
T87	75404	0	0	0
T88	48728	0	0	0
T218	2887	0	0	0
T223	0	833	0	0
T225	0	672	0	0
T229	0	399	0	0
T230	0	238	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	264165	0	0
T2	357412	192	0	0
T3	516247	2177	0	0
T4	386610	0	0	0
T5	285729	0	0	0
T13	577570	5	0	0
T14	0	31	0	0
T15	0	2	0	0
T16	0	14503	0	0
T19	8016	0	0	0
T20	70896	8	0	0
T21	60592	26	0	0
T22	27778	0	0	0
T25	0	12	0	0
T47	0	56	0	0
T52	50874	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	373851918	0	0
T1	38467	2202	0	0
T2	357412	2796	0	0
T3	516247	501799	0	0
T4	386610	386601	0	0
T5	285729	285724	0	0
T13	577570	575144	0	0
T19	8016	7952	0	0
T20	70896	5692	0	0
T21	60592	2135	0	0
T22	27778	583	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T21
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T219,T224,T226
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	733097492	5386	0	0
DisabledNoTrigBkwd_A	733097492	191474	0	0
DisabledNoTrigFwd_A	733097492	395310833	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	5386	0	0
T58	330608	0	0	0
T91	92722	0	0	0
T124	2484	0	0	0
T125	146323	0	0	0
T219	1247	424	0	0
T224	0	1624	0	0
T226	0	582	0	0
T227	0	956	0	0
T228	0	336	0	0
T233	0	718	0	0
T234	0	746	0	0
T236	20981	0	0	0
T237	344109	0	0	0
T238	42565	0	0	0
T239	253371	0	0	0
T240	815555	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	191474	0	0
T3	516247	371	0	0
T4	386610	1939	0	0
T5	285729	3	0	0
T13	577570	4	0	0
T14	0	4	0	0
T16	0	2874	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	22	0	0
T22	27778	0	0	0
T23	0	64	0	0
T46	86258	0	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	50874	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	395310833	0	0
T1	38467	2217	0	0
T2	357412	336495	0	0
T3	516247	349490	0	0
T4	386610	2576	0	0
T5	285729	283534	0	0
T13	577570	575681	0	0
T19	8016	7952	0	0
T20	70896	70802	0	0
T21	60592	41695	0	0
T22	27778	27693	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T21
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T21,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T218,T231,T232
1	1	Covered	T3,T21,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T21,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T21,T5,T13

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	733097492	2978	0	0
DisabledNoTrigBkwd_A	733097492	195872	0	0
DisabledNoTrigFwd_A	733097492	391249974	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	2978	0	0
T18	113568	0	0	0
T26	156296	0	0	0
T27	468846	0	0	0
T28	14930	0	0	0
T71	359734	0	0	0
T72	122837	0	0	0
T73	82249	0	0	0
T90	20450	0	0	0
T218	2887	768	0	0
T231	0	293	0	0
T232	0	1917	0	0
T241	36372	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	195872	0	0
T5	285729	1	0	0
T6	0	1	0	0
T13	577570	5762	0	0
T14	387075	2106	0	0
T15	868527	1486	0	0
T21	60592	8	0	0
T22	27778	0	0	0
T23	0	122	0	0
T25	109850	0	0	0
T46	86258	45	0	0
T50	0	1	0	0
T51	0	23	0	0
T52	50874	0	0	0
T53	34057	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	391249974	0	0
T1	38467	2232	0	0
T2	357412	357334	0	0
T3	516247	397924	0	0
T4	386610	386601	0	0
T5	285729	284376	0	0
T13	577570	3847	0	0
T19	8016	7952	0	0
T20	70896	70802	0	0
T21	60592	2168	0	0
T22	27778	27693	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T21
1	0	Covered	T2,T3,T4
1	1	Covered	T3,T21,T5

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T124,T220,T221
1	1	Covered	T3,T21,T5

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T21,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T21,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	733097492	3313	0	0
DisabledNoTrigBkwd_A	733097492	162367	0	0
DisabledNoTrigFwd_A	733097492	449746880	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	3313	0	0
T124	2484	272	0	0
T125	146323	0	0	0
T126	4278	0	0	0
T127	318211	0	0	0
T128	150583	0	0	0
T129	28373	0	0	0
T130	686161	0	0	0
T131	35070	0	0	0
T132	107236	0	0	0
T220	0	961	0	0
T221	0	600	0	0
T222	0	575	0	0
T235	0	905	0	0
T242	315969	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	162367	0	0
T3	516247	386	0	0
T4	386610	0	0	0
T5	285729	327	0	0
T13	577570	27	0	0
T14	0	25	0	0
T16	0	15	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	18	0	0
T22	27778	0	0	0
T25	0	65	0	0
T46	86258	45	0	0
T49	0	3	0	0
T50	0	7	0	0
T52	50874	0	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	449746880	0	0
T1	38467	2242	0	0
T2	357412	357334	0	0
T3	516247	467524	0	0
T4	386610	386601	0	0
T5	285729	10520	0	0
T13	577570	570883	0	0
T19	8016	7952	0	0
T20	70896	70802	0	0
T21	60592	11174	0	0
T22	27778	27693	0	0