Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T24
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T20,T21
1	0	1	Covered	T2,T3,T13
1	1	0	Covered	T3,T19,T21
1	1	1	Covered	T3,T21,T13

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T21,T13
0	1	Covered	T3,T25,T14
1	0	Covered	T26,T27,T28

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T21,T13
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T26,T27,T28

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T21,T13
1	0	Not Covered
1	1	Covered	T3,T25,T14

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T25,T14

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T20
1	Covered	T2,T3,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T4,T20

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T21,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T4,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T4,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T4

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T4
Phase1St	198	Covered	T2,T3,T4
Phase2St	215	Covered	T2,T3,T4
Phase3St	233	Covered	T2,T3,T4
TerminalSt	249	Covered	T2,T3,T4
TimeoutSt	159	Covered	T3,T21,T13

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T2,T3,T4
IdleSt->TimeoutSt	159	Covered	T3,T21,T13
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T17,T29,T30
Phase0St->Phase1St	198	Covered	T2,T3,T4
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T23,T17,T26
Phase1St->Phase2St	215	Covered	T2,T3,T4
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T23,T31,T32
Phase2St->Phase3St	233	Covered	T2,T3,T4
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T17,T32,T33
Phase3St->TerminalSt	249	Covered	T2,T3,T4
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T3,T4,T20
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T3,T21,T13
TimeoutSt->Phase0St	172	Covered	T3,T25,T14

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T25,T14
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T13
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T29,T30,T34
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T23,T17,T26
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T23,T31,T32
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T17,T32,T33
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T4,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	999	0	0
CheckAccumTrig0_A	2147483647	2520	0	0
CheckAccumTrig1_A	2147483647	129	0	0
CheckClr_A	2147483647	1221	0	0
CheckEn_A	2147483647	1259775089	0	0
CheckPhase0_A	2147483647	2867	0	0
CheckPhase1_A	2147483647	2812	0	0
CheckPhase2_A	2147483647	2750	0	0
CheckPhase3_A	2147483647	2693	0	0
CheckTimeout0_A	2147483647	4575	0	0
CheckTimeoutSt1_A	2147483647	470105	0	0
CheckTimeoutSt2_A	2147483647	4169	0	0
CheckTimeoutStTrig_A	2147483647	268	0	0
ErrorStAllEscAsserted_A	2147483647	5181	0	0
ErrorStIsTerminal_A	2147483647	4341	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	999	0	0
T10	215788	154	0	0
T11	0	243	0	0
T12	0	132	0	0
T35	0	339	0	0
T36	0	131	0	0
T37	333912	0	0	0
T38	147144	0	0	0
T39	1496072	0	0	0
T40	185348	0	0	0
T41	599932	0	0	0
T42	499512	0	0	0
T43	265540	0	0	0
T44	337944	0	0	0
T45	2579592	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2520	0	0
T2	357412	1	0	0
T3	1548741	9	0	0
T4	1159830	2	0	0
T5	1142916	3	0	0
T6	0	1	0	0
T13	2310280	4	0	0
T14	387075	10	0	0
T15	868527	2	0	0
T16	0	5	0	0
T19	24048	0	0	0
T20	212688	2	0	0
T21	242368	8	0	0
T22	111112	0	0	0
T23	0	8	0	0
T25	109850	4	0	0
T46	258774	3	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	5	0	0
T51	0	2	0	0
T52	203496	0	0	0
T53	34057	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	129	0	0
T7	551278	0	0	0
T26	312592	2	0	0
T27	937692	0	0	0
T28	29860	1	0	0
T33	344553	3	0	0
T34	0	3	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	330608	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	0	1	0	0
T65	0	2	0	0
T66	0	1	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	0	5	0	0
T70	0	1	0	0
T71	719468	0	0	0
T72	245674	0	0	0
T73	164498	0	0	0
T74	114444	0	0	0
T75	641700	0	0	0
T76	13222	0	0	0
T77	24216	0	0	0
T78	29697	0	0	0
T79	453145	0	0	0
T80	889422	0	0	0
T81	4223	0	0	0
T82	24395	0	0	0
T83	217712	0	0	0
T84	65512	0	0	0
T85	79222	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1221	0	0
T3	1548741	6	0	0
T4	1546440	1	0	0
T5	1142916	0	0	0
T6	0	1	0	0
T13	2310280	1	0	0
T14	0	3	0	0
T16	0	2	0	0
T17	0	18	0	0
T19	24048	0	0	0
T20	283584	1	0	0
T21	242368	5	0	0
T22	111112	0	0	0
T23	0	13	0	0
T25	109850	6	0	0
T26	0	11	0	0
T28	0	1	0	0
T46	345032	1	0	0
T49	0	2	0	0
T50	0	6	0	0
T52	203496	0	0	0
T53	34057	0	0	0
T54	0	4	0	0
T55	0	2	0	0
T72	0	1	0	0
T86	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1259775089	0	0
T1	153868	8889	0	0
T2	1429648	1053956	0	0
T3	2064988	1716733	0	0
T4	1546440	1162379	0	0
T5	1142916	326324	0	0
T13	2310280	622096	0	0
T19	32064	31804	0	0
T20	283584	214588	0	0
T21	242368	49522	0	0
T22	111112	83659	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2867	0	0
T2	357412	1	0	0
T3	2064988	11	0	0
T4	1546440	2	0	0
T5	1142916	3	0	0
T6	0	1	0	0
T13	2310280	4	0	0
T14	0	10	0	0
T15	0	2	0	0
T16	0	5	0	0
T19	32064	0	0	0
T20	283584	2	0	0
T21	242368	8	0	0
T22	111112	0	0	0
T25	0	8	0	0
T46	258774	3	0	0
T47	0	1	0	0
T49	0	3	0	0
T50	0	4	0	0
T51	0	1	0	0
T52	203496	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2812	0	0
T2	357412	1	0	0
T3	2064988	11	0	0
T4	1546440	2	0	0
T5	1142916	3	0	0
T6	0	1	0	0
T13	2310280	4	0	0
T14	0	10	0	0
T15	0	2	0	0
T16	0	5	0	0
T19	32064	0	0	0
T20	283584	2	0	0
T21	242368	8	0	0
T22	111112	0	0	0
T25	0	8	0	0
T46	258774	3	0	0
T47	0	1	0	0
T49	0	3	0	0
T50	0	4	0	0
T51	0	1	0	0
T52	203496	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2750	0	0
T2	357412	1	0	0
T3	2064988	11	0	0
T4	1546440	2	0	0
T5	1142916	3	0	0
T6	0	1	0	0
T13	2310280	4	0	0
T14	0	10	0	0
T15	0	2	0	0
T16	0	5	0	0
T19	32064	0	0	0
T20	283584	2	0	0
T21	242368	8	0	0
T22	111112	0	0	0
T25	0	8	0	0
T46	258774	3	0	0
T47	0	1	0	0
T49	0	3	0	0
T50	0	4	0	0
T51	0	1	0	0
T52	203496	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2693	0	0
T2	357412	1	0	0
T3	2064988	11	0	0
T4	1546440	2	0	0
T5	1142916	3	0	0
T6	0	1	0	0
T13	2310280	4	0	0
T14	0	10	0	0
T15	0	2	0	0
T16	0	5	0	0
T19	32064	0	0	0
T20	283584	2	0	0
T21	242368	8	0	0
T22	111112	0	0	0
T25	0	8	0	0
T46	258774	3	0	0
T47	0	1	0	0
T49	0	3	0	0
T50	0	4	0	0
T51	0	1	0	0
T52	203496	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4575	0	0
T3	1548741	500	0	0
T4	1159830	0	0	0
T5	857187	0	0	0
T6	542242	0	0	0
T13	2310280	1	0	0
T14	387075	1	0	0
T15	868527	0	0	0
T16	497603	0	0	0
T17	0	99	0	0
T19	24048	0	0	0
T20	212688	0	0	0
T21	181776	2	0	0
T22	83334	0	0	0
T23	0	62	0	0
T25	109850	7	0	0
T26	0	12	0	0
T28	0	2	0	0
T46	345032	0	0	0
T47	32001	0	0	0
T49	0	4	0	0
T52	203496	7	0	0
T53	34057	9	0	0
T86	0	8	0	0
T87	0	15	0	0
T88	0	1	0	0
T89	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	470105	0	0
T3	1548741	34851	0	0
T4	1159830	0	0	0
T5	857187	0	0	0
T6	542242	0	0	0
T13	2310280	180	0	0
T14	387075	184	0	0
T15	868527	0	0	0
T16	497603	0	0	0
T17	0	6290	0	0
T19	24048	0	0	0
T20	212688	0	0	0
T21	181776	60	0	0
T22	83334	0	0	0
T23	0	10550	0	0
T25	109850	2108	0	0
T26	0	684	0	0
T28	0	776	0	0
T46	345032	0	0	0
T47	32001	0	0	0
T49	0	1757	0	0
T52	203496	1415	0	0
T53	34057	1263	0	0
T86	0	515	0	0
T87	0	2835	0	0
T88	0	26	0	0
T89	0	844	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4169	0	0
T3	1548741	498	0	0
T4	1159830	0	0	0
T5	857187	0	0	0
T6	542242	0	0	0
T13	2310280	1	0	0
T14	387075	0	0	0
T15	868527	0	0	0
T16	497603	0	0	0
T17	0	96	0	0
T19	24048	0	0	0
T20	212688	0	0	0
T21	181776	2	0	0
T22	83334	0	0	0
T23	0	58	0	0
T25	109850	3	0	0
T26	0	20	0	0
T28	0	2	0	0
T31	0	2	0	0
T46	345032	0	0	0
T47	32001	0	0	0
T49	0	1	0	0
T52	203496	7	0	0
T53	34057	9	0	0
T86	0	12	0	0
T87	0	14	0	0
T88	0	1	0	0
T89	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	268	0	0
T3	516247	2	0	0
T4	386610	0	0	0
T5	285729	0	0	0
T6	1626726	0	0	0
T13	577570	0	0	0
T14	1161225	1	0	0
T15	2605581	0	0	0
T16	1492809	0	0	0
T17	0	3	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	0	0	0
T22	27778	0	0	0
T23	0	4	0	0
T25	329550	4	0	0
T26	0	4	0	0
T28	0	2	0	0
T29	0	5	0	0
T32	0	1	0	0
T33	0	2	0	0
T46	86258	0	0	0
T47	96003	0	0	0
T48	7320	0	0	0
T49	33804	3	0	0
T50	116994	0	0	0
T51	181695	0	0	0
T52	50874	0	0	0
T56	0	2	0	0
T58	0	9	0	0
T85	0	2	0	0
T87	0	1	0	0
T89	0	2	0	0
T90	0	1	0	0
T91	0	1	0	0
T92	0	2	0	0
T93	0	1	0	0
T94	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5181	0	0
T10	215788	751	0	0
T11	0	1469	0	0
T12	0	700	0	0
T35	0	1572	0	0
T36	0	689	0	0
T37	333912	0	0	0
T38	147144	0	0	0
T39	1496072	0	0	0
T40	185348	0	0	0
T41	599932	0	0	0
T42	499512	0	0	0
T43	265540	0	0	0
T44	337944	0	0	0
T45	2579592	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4341	0	0
T10	215788	631	0	0
T11	0	1229	0	0
T12	0	580	0	0
T35	0	1332	0	0
T36	0	569	0	0
T37	333912	0	0	0
T38	147144	0	0	0
T39	1496072	0	0	0
T40	185348	0	0	0
T41	599932	0	0	0
T42	499512	0	0	0
T43	265540	0	0	0
T44	337944	0	0	0
T45	2579592	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	153868	153200	0	0
T2	1429648	1429336	0	0
T3	2064988	2064936	0	0
T4	1546440	1546404	0	0
T5	1142916	1142896	0	0
T13	2310280	2310252	0	0
T19	32064	31808	0	0
T20	283584	283208	0	0
T21	242368	241988	0	0
T22	111112	110772	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	153868	153200	0	0
T2	1429648	1429336	0	0
T3	2064988	2064936	0	0
T4	1546440	1546404	0	0
T5	1142916	1142896	0	0
T13	2310280	2310252	0	0
T19	32064	31808	0	0
T20	283584	283208	0	0
T21	242368	241988	0	0
T22	111112	110772	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T21
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T21,T52
1	0	1	Covered	T2,T3,T13
1	1	0	Covered	T21,T13,T52
1	1	1	Covered	T3,T21,T52

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T21,T52
0	1	Covered	T25,T17,T26
1	0	Covered	T26,T27,T56

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T21,T52
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T26,T27,T56

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T21,T52
1	0	Not Covered
1	1	Covered	T25,T17,T26

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T21
1	Covered	T16,T50,T23

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T4,T21,T13

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T21,T13
1	Covered	T3,T4,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T21
1	Covered	T25,T14,T16

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T4,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T4,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T4,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T4,T25,T14

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T4,T21
Phase1St	198	Covered	T3,T4,T21
Phase2St	215	Covered	T3,T4,T21
Phase3St	233	Covered	T3,T4,T21
TerminalSt	249	Covered	T3,T4,T21
TimeoutSt	159	Covered	T3,T21,T52

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T3,T4,T21
IdleSt->TimeoutSt	159	Covered	T3,T21,T52
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T29,T95,T67
Phase0St->Phase1St	198	Covered	T3,T4,T21
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T96,T34,T97
Phase1St->Phase2St	215	Covered	T3,T4,T21
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T31,T98,T99
Phase2St->Phase3St	233	Covered	T3,T4,T21
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T59,T100,T65
Phase3St->TerminalSt	249	Covered	T3,T4,T21
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T4,T21
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T21,T52
TimeoutSt->Phase0St	172	Covered	T25,T17,T26

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T52
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T25,T17,T26
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T52
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T52
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T29,T95,T67
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T4,T21
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T4,T21
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T96,T97,T101
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T4,T21
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T4,T21
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T31,T98,T99
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T4,T21
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T4,T21
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T59,T100,T65
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T4,T21
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T4,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T4,T21,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T4,T21
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	733097492	233	0	0
CheckAccumTrig0_A	733097492	549	0	0
CheckAccumTrig1_A	733097492	22	0	0
CheckClr_A	733097492	264	0	0
CheckEn_A	732914057	321857469	0	0
CheckPhase0_A	733097492	625	0	0
CheckPhase1_A	733097492	614	0	0
CheckPhase2_A	733097492	601	0	0
CheckPhase3_A	733097492	592	0	0
CheckTimeout0_A	733097492	1593	0	0
CheckTimeoutSt1_A	733097492	151675	0	0
CheckTimeoutSt2_A	733097492	1506	0	0
CheckTimeoutStTrig_A	733097492	62	0	0
ErrorStAllEscAsserted_A	733097492	1295	0	0
ErrorStIsTerminal_A	733097492	1085	0	0
EscStateOut_A	732912797	732841571	0	0
u_state_regs_A	733097492	732937064	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	233	0	0
T10	53947	31	0	0
T11	0	47	0	0
T12	0	27	0	0
T35	0	84	0	0
T36	0	44	0	0
T37	83478	0	0	0
T38	36786	0	0	0
T39	374018	0	0	0
T40	46337	0	0	0
T41	149983	0	0	0
T42	124878	0	0	0
T43	66385	0	0	0
T44	84486	0	0	0
T45	644898	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	549	0	0
T3	516247	1	0	0
T4	386610	2	0	0
T5	285729	1	0	0
T13	577570	1	0	0
T14	0	1	0	0
T16	0	2	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	2	0	0
T22	27778	0	0	0
T23	0	3	0	0
T46	86258	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	50874	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	22	0	0
T7	275639	0	0	0
T26	156296	1	0	0
T27	468846	0	0	0
T28	14930	0	0	0
T56	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	2	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	359734	0	0	0
T72	122837	0	0	0
T73	82249	0	0	0
T74	57222	0	0	0
T75	320850	0	0	0
T76	6611	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	264	0	0
T4	386610	1	0	0
T5	285729	0	0	0
T13	577570	1	0	0
T16	0	1	0	0
T17	0	8	0	0
T20	70896	0	0	0
T21	60592	2	0	0
T22	27778	0	0	0
T23	0	1	0	0
T25	109850	1	0	0
T26	0	3	0	0
T46	86258	0	0	0
T50	0	1	0	0
T52	50874	0	0	0
T53	34057	0	0	0
T86	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732914057	321857469	0	0
T1	38467	2216	0	0
T2	357412	336494	0	0
T3	516247	349490	0	0
T4	386610	2576	0	0
T5	285729	10393	0	0
T13	577570	575452	0	0
T19	8016	7951	0	0
T20	70896	70801	0	0
T21	60592	35687	0	0
T22	27778	27692	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	625	0	0
T3	516247	1	0	0
T4	386610	2	0	0
T5	285729	1	0	0
T13	577570	1	0	0
T14	0	1	0	0
T16	0	2	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	2	0	0
T22	27778	0	0	0
T25	0	1	0	0
T46	86258	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	50874	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	614	0	0
T3	516247	1	0	0
T4	386610	2	0	0
T5	285729	1	0	0
T13	577570	1	0	0
T14	0	1	0	0
T16	0	2	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	2	0	0
T22	27778	0	0	0
T25	0	1	0	0
T46	86258	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	50874	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	601	0	0
T3	516247	1	0	0
T4	386610	2	0	0
T5	285729	1	0	0
T13	577570	1	0	0
T14	0	1	0	0
T16	0	2	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	2	0	0
T22	27778	0	0	0
T25	0	1	0	0
T46	86258	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	50874	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	592	0	0
T3	516247	1	0	0
T4	386610	2	0	0
T5	285729	1	0	0
T13	577570	1	0	0
T14	0	1	0	0
T16	0	2	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	2	0	0
T22	27778	0	0	0
T25	0	1	0	0
T46	86258	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	50874	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	1593	0	0
T3	516247	222	0	0
T4	386610	0	0	0
T5	285729	0	0	0
T13	577570	0	0	0
T17	0	62	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	1	0	0
T22	27778	0	0	0
T23	0	1	0	0
T25	0	2	0	0
T26	0	9	0	0
T46	86258	0	0	0
T52	50874	1	0	0
T53	0	3	0	0
T86	0	2	0	0
T87	0	6	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	151675	0	0
T3	516247	15623	0	0
T4	386610	0	0	0
T5	285729	0	0	0
T13	577570	0	0	0
T17	0	4178	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	40	0	0
T22	27778	0	0	0
T23	0	181	0	0
T25	0	1010	0	0
T26	0	412	0	0
T46	86258	0	0	0
T52	50874	184	0	0
T53	0	448	0	0
T86	0	108	0	0
T87	0	1106	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	1506	0	0
T3	516247	222	0	0
T4	386610	0	0	0
T5	285729	0	0	0
T13	577570	0	0	0
T17	0	61	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	1	0	0
T22	27778	0	0	0
T23	0	1	0	0
T25	0	1	0	0
T26	0	7	0	0
T46	86258	0	0	0
T52	50874	1	0	0
T53	0	3	0	0
T86	0	2	0	0
T87	0	6	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	62	0	0
T6	542242	0	0	0
T14	387075	0	0	0
T15	868527	0	0	0
T16	497603	0	0	0
T17	0	1	0	0
T25	109850	1	0	0
T26	0	1	0	0
T29	0	5	0	0
T47	32001	0	0	0
T48	2440	0	0	0
T49	11268	0	0	0
T50	38998	0	0	0
T51	60565	0	0	0
T58	0	1	0	0
T89	0	1	0	0
T91	0	1	0	0
T92	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	1295	0	0
T10	53947	180	0	0
T11	0	378	0	0
T12	0	184	0	0
T35	0	385	0	0
T36	0	168	0	0
T37	83478	0	0	0
T38	36786	0	0	0
T39	374018	0	0	0
T40	46337	0	0	0
T41	149983	0	0	0
T42	124878	0	0	0
T43	66385	0	0	0
T44	84486	0	0	0
T45	644898	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	1085	0	0
T10	53947	150	0	0
T11	0	318	0	0
T12	0	154	0	0
T35	0	325	0	0
T36	0	138	0	0
T37	83478	0	0	0
T38	36786	0	0	0
T39	374018	0	0	0
T40	46337	0	0	0
T41	149983	0	0	0
T42	124878	0	0	0
T43	66385	0	0	0
T44	84486	0	0	0
T45	644898	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732912797	732841571	0	0
T1	38467	38300	0	0
T2	357412	357334	0	0
T3	516247	516234	0	0
T4	386610	386601	0	0
T5	285729	285724	0	0
T13	577570	577563	0	0
T19	8016	7952	0	0
T20	70896	70802	0	0
T21	60592	60497	0	0
T22	27778	27693	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	732937064	0	0
T1	38467	38300	0	0
T2	357412	357334	0	0
T3	516247	516234	0	0
T4	386610	386601	0	0
T5	285729	285724	0	0
T13	577570	577563	0	0
T19	8016	7952	0	0
T20	70896	70802	0	0
T21	60592	60497	0	0
T22	27778	27693	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T21,T5
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T21,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T21,T5

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T21,T5,T13

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T21,T52
1	0	1	Covered	T3,T16,T51
1	1	0	Covered	T46,T53,T25
1	1	1	Covered	T3,T21,T52

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T21,T52
0	1	Covered	T3,T25,T49
1	0	Covered	T54,T33,T57

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T21,T52
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T54,T33,T57

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T21,T52
1	0	Not Covered
1	1	Covered	T3,T25,T49

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T21,T5
1	Covered	T25,T6,T49

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T21,T5,T46
1	Covered	T3,T13,T46

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T21,T5
1	Covered	T46,T14,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T13,T46
1	Covered	T21,T5,T23

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T21,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T5,T25

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T21,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T21,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T21,T5
Phase1St	198	Covered	T3,T21,T5
Phase2St	215	Covered	T3,T21,T5
Phase3St	233	Covered	T3,T21,T5
TerminalSt	249	Covered	T3,T21,T5
TimeoutSt	159	Covered	T3,T21,T52

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T21,T5,T13
IdleSt->TimeoutSt	159	Covered	T3,T21,T52
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T102,T103,T104
Phase0St->Phase1St	198	Covered	T3,T21,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T105,T106,T100
Phase1St->Phase2St	215	Covered	T3,T21,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T23,T107,T69
Phase2St->Phase3St	233	Covered	T3,T21,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T33,T58,T59
Phase3St->TerminalSt	249	Covered	T3,T21,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T21,T46
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T21,T52
TimeoutSt->Phase0St	172	Covered	T3,T25,T49

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T21,T5,T13
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T52
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T25,T49
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T52
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T52
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T102,T103,T108
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T21,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T21,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T105,T106,T100
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T21,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T21,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T23,T107,T69
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T21,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T21,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T33,T58,T59
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T21,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T21,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T21,T46
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T21,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	733097492	273	0	0
CheckAccumTrig0_A	733097492	538	0	0
CheckAccumTrig1_A	733097492	24	0	0
CheckClr_A	733097492	246	0	0
CheckEn_A	732914057	319318780	0	0
CheckPhase0_A	733097492	614	0	0
CheckPhase1_A	733097492	601	0	0
CheckPhase2_A	733097492	591	0	0
CheckPhase3_A	733097492	579	0	0
CheckTimeout0_A	733097492	819	0	0
CheckTimeoutSt1_A	733097492	96917	0	0
CheckTimeoutSt2_A	733097492	732	0	0
CheckTimeoutStTrig_A	733097492	62	0	0
ErrorStAllEscAsserted_A	733097492	1278	0	0
ErrorStIsTerminal_A	733097492	1068	0	0
EscStateOut_A	732912797	732841571	0	0
u_state_regs_A	733097492	732937064	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	273	0	0
T10	53947	46	0	0
T11	0	82	0	0
T12	0	50	0	0
T35	0	72	0	0
T36	0	23	0	0
T37	83478	0	0	0
T38	36786	0	0	0
T39	374018	0	0	0
T40	46337	0	0	0
T41	149983	0	0	0
T42	124878	0	0	0
T43	66385	0	0	0
T44	84486	0	0	0
T45	644898	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	538	0	0
T5	285729	1	0	0
T6	0	1	0	0
T13	577570	1	0	0
T14	387075	2	0	0
T15	868527	1	0	0
T21	60592	2	0	0
T22	27778	0	0	0
T23	0	5	0	0
T25	109850	0	0	0
T46	86258	2	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	50874	0	0	0
T53	34057	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	24	0	0
T33	344553	2	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T67	0	1	0	0
T69	0	4	0	0
T77	24216	0	0	0
T78	29697	0	0	0
T79	453145	0	0	0
T80	889422	0	0	0
T81	4223	0	0	0
T82	24395	0	0	0
T83	217712	0	0	0
T84	65512	0	0	0
T85	79222	0	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	246	0	0
T3	516247	1	0	0
T4	386610	0	0	0
T5	285729	0	0	0
T6	0	1	0	0
T13	577570	0	0	0
T17	0	4	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	1	0	0
T22	27778	0	0	0
T23	0	4	0	0
T25	0	1	0	0
T46	86258	1	0	0
T50	0	1	0	0
T52	50874	0	0	0
T55	0	2	0	0
T72	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732914057	319318780	0	0
T1	38467	2231	0	0
T2	357412	357333	0	0
T3	516247	397923	0	0
T4	386610	386601	0	0
T5	285729	28215	0	0
T13	577570	3847	0	0
T19	8016	7951	0	0
T20	70896	70801	0	0
T21	60592	2168	0	0
T22	27778	27692	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	614	0	0
T3	516247	2	0	0
T4	386610	0	0	0
T5	285729	1	0	0
T6	0	1	0	0
T13	577570	1	0	0
T14	0	2	0	0
T15	0	1	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	2	0	0
T22	27778	0	0	0
T25	0	1	0	0
T46	86258	2	0	0
T49	0	1	0	0
T52	50874	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	601	0	0
T3	516247	2	0	0
T4	386610	0	0	0
T5	285729	1	0	0
T6	0	1	0	0
T13	577570	1	0	0
T14	0	2	0	0
T15	0	1	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	2	0	0
T22	27778	0	0	0
T25	0	1	0	0
T46	86258	2	0	0
T49	0	1	0	0
T52	50874	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	591	0	0
T3	516247	2	0	0
T4	386610	0	0	0
T5	285729	1	0	0
T6	0	1	0	0
T13	577570	1	0	0
T14	0	2	0	0
T15	0	1	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	2	0	0
T22	27778	0	0	0
T25	0	1	0	0
T46	86258	2	0	0
T49	0	1	0	0
T52	50874	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	579	0	0
T3	516247	2	0	0
T4	386610	0	0	0
T5	285729	1	0	0
T6	0	1	0	0
T13	577570	1	0	0
T14	0	2	0	0
T15	0	1	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	2	0	0
T22	27778	0	0	0
T25	0	1	0	0
T46	86258	2	0	0
T49	0	1	0	0
T52	50874	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	819	0	0
T3	516247	3	0	0
T4	386610	0	0	0
T5	285729	0	0	0
T13	577570	0	0	0
T17	0	2	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	1	0	0
T22	27778	0	0	0
T23	0	13	0	0
T25	0	2	0	0
T46	86258	0	0	0
T49	0	1	0	0
T52	50874	4	0	0
T53	0	2	0	0
T86	0	1	0	0
T87	0	7	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	96917	0	0
T3	516247	250	0	0
T4	386610	0	0	0
T5	285729	0	0	0
T13	577570	0	0	0
T17	0	115	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	20	0	0
T22	27778	0	0	0
T23	0	2695	0	0
T25	0	337	0	0
T46	86258	0	0	0
T49	0	476	0	0
T52	50874	871	0	0
T53	0	245	0	0
T86	0	64	0	0
T87	0	1437	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	732	0	0
T3	516247	1	0	0
T4	386610	0	0	0
T5	285729	0	0	0
T13	577570	0	0	0
T17	0	2	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	1	0	0
T22	27778	0	0	0
T23	0	11	0	0
T25	0	1	0	0
T26	0	4	0	0
T46	86258	0	0	0
T52	50874	4	0	0
T53	0	2	0	0
T86	0	1	0	0
T87	0	7	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	62	0	0
T3	516247	2	0	0
T4	386610	0	0	0
T5	285729	0	0	0
T13	577570	0	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	0	0	0
T22	27778	0	0	0
T23	0	2	0	0
T25	0	1	0	0
T26	0	1	0	0
T32	0	1	0	0
T33	0	2	0	0
T46	86258	0	0	0
T49	0	1	0	0
T52	50874	0	0	0
T56	0	1	0	0
T58	0	1	0	0
T85	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	1278	0	0
T10	53947	197	0	0
T11	0	352	0	0
T12	0	168	0	0
T35	0	408	0	0
T36	0	153	0	0
T37	83478	0	0	0
T38	36786	0	0	0
T39	374018	0	0	0
T40	46337	0	0	0
T41	149983	0	0	0
T42	124878	0	0	0
T43	66385	0	0	0
T44	84486	0	0	0
T45	644898	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	1068	0	0
T10	53947	167	0	0
T11	0	292	0	0
T12	0	138	0	0
T35	0	348	0	0
T36	0	123	0	0
T37	83478	0	0	0
T38	36786	0	0	0
T39	374018	0	0	0
T40	46337	0	0	0
T41	149983	0	0	0
T42	124878	0	0	0
T43	66385	0	0	0
T44	84486	0	0	0
T45	644898	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732912797	732841571	0	0
T1	38467	38300	0	0
T2	357412	357334	0	0
T3	516247	516234	0	0
T4	386610	386601	0	0
T5	285729	285724	0	0
T13	577570	577563	0	0
T19	8016	7952	0	0
T20	70896	70802	0	0
T21	60592	60497	0	0
T22	27778	27693	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	732937064	0	0
T1	38467	38300	0	0
T2	357412	357334	0	0
T3	516247	516234	0	0
T4	386610	386601	0	0
T5	285729	285724	0	0
T13	577570	577563	0	0
T19	8016	7952	0	0
T20	70896	70802	0	0
T21	60592	60497	0	0
T22	27778	27693	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T21,T5
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T21,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T21,T5

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T21
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T21,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T21,T13,T52
1	0	1	Covered	T3,T50,T23
1	1	0	Covered	T3,T13,T52
1	1	1	Covered	T13,T53,T25

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T13,T53,T25
0	1	Covered	T25,T49,T87
1	0	Covered	T58,T113,T114

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T13,T53,T25
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T58,T113,T114

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T13,T53,T25
1	0	Not Covered
1	1	Covered	T25,T49,T87

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T21,T5
1	Covered	T25,T14,T50

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T21,T5
1	Covered	T21,T16,T50

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T21,T5
1	Covered	T21,T14,T16

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T21,T25,T14
1	Covered	T3,T5,T13

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T21,T25,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T21,T5,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T21,T14

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T13,T46

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T21,T5
Phase1St	198	Covered	T3,T21,T5
Phase2St	215	Covered	T3,T21,T5
Phase3St	233	Covered	T3,T21,T5
TerminalSt	249	Covered	T3,T21,T5
TimeoutSt	159	Covered	T13,T53,T25

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T3,T21,T5
IdleSt->TimeoutSt	159	Covered	T13,T53,T25
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T14,T54,T115
Phase0St->Phase1St	198	Covered	T3,T21,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T58,T116,T66
Phase1St->Phase2St	215	Covered	T3,T21,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T117,T118,T119
Phase2St->Phase3St	233	Covered	T3,T21,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T89,T120,T121
Phase3St->TerminalSt	249	Covered	T3,T21,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T21,T25
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T13,T53,T25
TimeoutSt->Phase0St	172	Covered	T25,T49,T87

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T21,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T53,T25
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T25,T49,T87
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T13,T53,T25
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T13,T53,T25
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T14,T115,T95
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T21,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T21,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T58,T116,T66
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T21,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T21,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T117,T118,T119
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T21,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T21,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T89,T120,T121
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T21,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T21,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T21,T25
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T21,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	733097492	228	0	0
CheckAccumTrig0_A	733097492	514	0	0
CheckAccumTrig1_A	733097492	30	0	0
CheckClr_A	733097492	242	0	0
CheckEn_A	732914057	336702742	0	0
CheckPhase0_A	733097492	604	0	0
CheckPhase1_A	733097492	594	0	0
CheckPhase2_A	733097492	583	0	0
CheckPhase3_A	733097492	571	0	0
CheckTimeout0_A	733097492	1107	0	0
CheckTimeoutSt1_A	733097492	113078	0	0
CheckTimeoutSt2_A	733097492	1006	0	0
CheckTimeoutStTrig_A	733097492	69	0	0
ErrorStAllEscAsserted_A	733097492	1263	0	0
ErrorStIsTerminal_A	733097492	1053	0	0
EscStateOut_A	732912797	732841571	0	0
u_state_regs_A	733097492	732937064	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	228	0	0
T10	53947	23	0	0
T11	0	44	0	0
T12	0	33	0	0
T35	0	92	0	0
T36	0	36	0	0
T37	83478	0	0	0
T38	36786	0	0	0
T39	374018	0	0	0
T40	46337	0	0	0
T41	149983	0	0	0
T42	124878	0	0	0
T43	66385	0	0	0
T44	84486	0	0	0
T45	644898	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	514	0	0
T3	516247	2	0	0
T4	386610	0	0	0
T5	285729	1	0	0
T13	577570	1	0	0
T14	0	5	0	0
T16	0	2	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	2	0	0
T22	27778	0	0	0
T25	0	4	0	0
T46	86258	1	0	0
T49	0	1	0	0
T50	0	3	0	0
T52	50874	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	30	0	0
T30	0	1	0	0
T58	330608	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T98	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0
T122	0	2	0	0
T123	0	1	0	0
T124	2484	0	0	0
T125	146323	0	0	0
T126	4278	0	0	0
T127	318211	0	0	0
T128	150583	0	0	0
T129	28373	0	0	0
T130	686161	0	0	0
T131	35070	0	0	0
T132	107236	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	242	0	0
T3	516247	1	0	0
T4	386610	0	0	0
T5	285729	0	0	0
T13	577570	0	0	0
T14	0	2	0	0
T16	0	1	0	0
T17	0	3	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	1	0	0
T22	27778	0	0	0
T23	0	2	0	0
T25	0	4	0	0
T26	0	1	0	0
T46	86258	0	0	0
T49	0	2	0	0
T50	0	3	0	0
T52	50874	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732914057	336702742	0	0
T1	38467	2241	0	0
T2	357412	357333	0	0
T3	516247	467524	0	0
T4	386610	386601	0	0
T5	285729	1992	0	0
T13	577570	33015	0	0
T19	8016	7951	0	0
T20	70896	70801	0	0
T21	60592	9532	0	0
T22	27778	27692	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	604	0	0
T3	516247	2	0	0
T4	386610	0	0	0
T5	285729	1	0	0
T13	577570	1	0	0
T14	0	4	0	0
T16	0	2	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	2	0	0
T22	27778	0	0	0
T25	0	5	0	0
T46	86258	1	0	0
T49	0	2	0	0
T50	0	3	0	0
T52	50874	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	594	0	0
T3	516247	2	0	0
T4	386610	0	0	0
T5	285729	1	0	0
T13	577570	1	0	0
T14	0	4	0	0
T16	0	2	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	2	0	0
T22	27778	0	0	0
T25	0	5	0	0
T46	86258	1	0	0
T49	0	2	0	0
T50	0	3	0	0
T52	50874	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	583	0	0
T3	516247	2	0	0
T4	386610	0	0	0
T5	285729	1	0	0
T13	577570	1	0	0
T14	0	4	0	0
T16	0	2	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	2	0	0
T22	27778	0	0	0
T25	0	5	0	0
T46	86258	1	0	0
T49	0	2	0	0
T50	0	3	0	0
T52	50874	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	571	0	0
T3	516247	2	0	0
T4	386610	0	0	0
T5	285729	1	0	0
T13	577570	1	0	0
T14	0	4	0	0
T16	0	2	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	2	0	0
T22	27778	0	0	0
T25	0	5	0	0
T46	86258	1	0	0
T49	0	2	0	0
T50	0	3	0	0
T52	50874	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	1107	0	0
T6	542242	0	0	0
T13	577570	1	0	0
T14	387075	0	0	0
T15	868527	0	0	0
T16	497603	0	0	0
T23	0	34	0	0
T25	109850	2	0	0
T26	0	3	0	0
T28	0	2	0	0
T46	86258	0	0	0
T47	32001	0	0	0
T49	0	2	0	0
T52	50874	0	0	0
T53	34057	1	0	0
T86	0	5	0	0
T87	0	1	0	0
T89	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	113078	0	0
T6	542242	0	0	0
T13	577570	180	0	0
T14	387075	0	0	0
T15	868527	0	0	0
T16	497603	0	0	0
T23	0	4970	0	0
T25	109850	457	0	0
T26	0	272	0	0
T28	0	776	0	0
T46	86258	0	0	0
T47	32001	0	0	0
T49	0	1046	0	0
T52	50874	0	0	0
T53	34057	128	0	0
T86	0	343	0	0
T87	0	78	0	0
T89	0	844	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	1006	0	0
T6	542242	0	0	0
T13	577570	1	0	0
T14	387075	0	0	0
T15	868527	0	0	0
T16	497603	0	0	0
T23	0	33	0	0
T25	109850	1	0	0
T26	0	3	0	0
T28	0	1	0	0
T31	0	2	0	0
T46	86258	0	0	0
T47	32001	0	0	0
T49	0	1	0	0
T52	50874	0	0	0
T53	34057	1	0	0
T86	0	5	0	0
T89	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	69	0	0
T6	542242	0	0	0
T14	387075	0	0	0
T15	868527	0	0	0
T16	497603	0	0	0
T23	0	1	0	0
T25	109850	1	0	0
T28	0	1	0	0
T47	32001	0	0	0
T48	2440	0	0	0
T49	11268	1	0	0
T50	38998	0	0	0
T51	60565	0	0	0
T58	0	4	0	0
T84	0	1	0	0
T85	0	1	0	0
T87	0	1	0	0
T89	0	1	0	0
T92	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	1263	0	0
T10	53947	174	0	0
T11	0	340	0	0
T12	0	181	0	0
T35	0	380	0	0
T36	0	188	0	0
T37	83478	0	0	0
T38	36786	0	0	0
T39	374018	0	0	0
T40	46337	0	0	0
T41	149983	0	0	0
T42	124878	0	0	0
T43	66385	0	0	0
T44	84486	0	0	0
T45	644898	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	1053	0	0
T10	53947	144	0	0
T11	0	280	0	0
T12	0	151	0	0
T35	0	320	0	0
T36	0	158	0	0
T37	83478	0	0	0
T38	36786	0	0	0
T39	374018	0	0	0
T40	46337	0	0	0
T41	149983	0	0	0
T42	124878	0	0	0
T43	66385	0	0	0
T44	84486	0	0	0
T45	644898	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732912797	732841571	0	0
T1	38467	38300	0	0
T2	357412	357334	0	0
T3	516247	516234	0	0
T4	386610	386601	0	0
T5	285729	285724	0	0
T13	577570	577563	0	0
T19	8016	7952	0	0
T20	70896	70802	0	0
T21	60592	60497	0	0
T22	27778	27693	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	732937064	0	0
T1	38467	38300	0	0
T2	357412	357334	0	0
T3	516247	516234	0	0
T4	386610	386601	0	0
T5	285729	285724	0	0
T13	577570	577563	0	0
T19	8016	7952	0	0
T20	70896	70802	0	0
T21	60592	60497	0	0
T22	27778	27693	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T20
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T20
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T20

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T24
1	1	1	Covered	T2,T3,T20

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T20,T21
1	0	1	Covered	T2,T3,T13
1	1	0	Covered	T19,T53,T25
1	1	1	Covered	T3,T52,T53

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T52,T53
0	1	Covered	T25,T14,T49
1	0	Covered	T26,T28,T54

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T52,T53
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T26,T28,T54

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T52,T53
1	0	Not Covered
1	1	Covered	T25,T14,T49

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T20
1	Covered	T3,T25,T14

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T20,T21
1	Covered	T2,T3,T13

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T13
1	Covered	T20,T21,T23

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T20
1	Covered	T3,T14,T16

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T10,T11,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T20,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T3,T21,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T10,T11,T12
1	0	Covered	T2,T3,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T10,T11,T12
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T20
Phase1St	198	Covered	T2,T3,T20
Phase2St	215	Covered	T2,T3,T20
Phase3St	233	Covered	T2,T3,T20
TerminalSt	249	Covered	T2,T3,T20
TimeoutSt	159	Covered	T3,T52,T53

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T10,T11,T12
IdleSt->Phase0St	152	Covered	T2,T3,T20
IdleSt->TimeoutSt	159	Covered	T3,T52,T53
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T17,T30,T34
Phase0St->Phase1St	198	Covered	T2,T3,T20
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T23,T17,T26
Phase1St->Phase2St	215	Covered	T2,T3,T20
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T32,T105,T106
Phase2St->Phase3St	233	Covered	T2,T3,T20
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T17,T32,T133
Phase3St->TerminalSt	249	Covered	T2,T3,T20
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T20,T21
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T52,T53
TimeoutSt->Phase0St	172	Covered	T25,T14,T49

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T20
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T52,T53
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T25,T14,T49
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T52,T53
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T52,T53
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T34,T95
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T20
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T3,T20
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T23,T17,T26
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T20
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T3,T20
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T32,T105,T106
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T20
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T3,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T17,T32,T133
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T20
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T3,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T20,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T20
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T12

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T10,T11,T12
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	733097492	265	0	0
CheckAccumTrig0_A	733097492	919	0	0
CheckAccumTrig1_A	733097492	53	0	0
CheckClr_A	733097492	469	0	0
CheckEn_A	732914057	281896098	0	0
CheckPhase0_A	733097492	1024	0	0
CheckPhase1_A	733097492	1003	0	0
CheckPhase2_A	733097492	975	0	0
CheckPhase3_A	733097492	951	0	0
CheckTimeout0_A	733097492	1056	0	0
CheckTimeoutSt1_A	733097492	108435	0	0
CheckTimeoutSt2_A	733097492	925	0	0
CheckTimeoutStTrig_A	733097492	75	0	0
ErrorStAllEscAsserted_A	733097492	1345	0	0
ErrorStIsTerminal_A	733097492	1135	0	0
EscStateOut_A	732912797	732841571	0	0
u_state_regs_A	733097492	732937064	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	265	0	0
T10	53947	54	0	0
T11	0	70	0	0
T12	0	22	0	0
T35	0	91	0	0
T36	0	28	0	0
T37	83478	0	0	0
T38	36786	0	0	0
T39	374018	0	0	0
T40	46337	0	0	0
T41	149983	0	0	0
T42	124878	0	0	0
T43	66385	0	0	0
T44	84486	0	0	0
T45	644898	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	919	0	0
T2	357412	1	0	0
T3	516247	6	0	0
T4	386610	0	0	0
T5	285729	0	0	0
T13	577570	1	0	0
T14	0	2	0	0
T15	0	1	0	0
T16	0	1	0	0
T19	8016	0	0	0
T20	70896	2	0	0
T21	60592	2	0	0
T22	27778	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T52	50874	0	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	53	0	0
T7	275639	0	0	0
T26	156296	1	0	0
T27	468846	0	0	0
T28	14930	1	0	0
T33	0	1	0	0
T34	0	3	0	0
T54	0	1	0	0
T55	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T71	359734	0	0	0
T72	122837	0	0	0
T73	82249	0	0	0
T74	57222	0	0	0
T75	320850	0	0	0
T76	6611	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	469	0	0
T3	516247	4	0	0
T4	386610	0	0	0
T5	285729	0	0	0
T13	577570	0	0	0
T14	0	1	0	0
T17	0	3	0	0
T19	8016	0	0	0
T20	70896	1	0	0
T21	60592	1	0	0
T22	27778	0	0	0
T23	0	6	0	0
T26	0	7	0	0
T28	0	1	0	0
T46	86258	0	0	0
T50	0	1	0	0
T52	50874	0	0	0
T54	0	4	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732914057	281896098	0	0
T1	38467	2201	0	0
T2	357412	2796	0	0
T3	516247	501796	0	0
T4	386610	386601	0	0
T5	285729	285724	0	0
T13	577570	9782	0	0
T19	8016	7951	0	0
T20	70896	2185	0	0
T21	60592	2135	0	0
T22	27778	583	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	1024	0	0
T2	357412	1	0	0
T3	516247	6	0	0
T4	386610	0	0	0
T5	285729	0	0	0
T13	577570	1	0	0
T14	0	3	0	0
T15	0	1	0	0
T16	0	1	0	0
T19	8016	0	0	0
T20	70896	2	0	0
T21	60592	2	0	0
T22	27778	0	0	0
T25	0	1	0	0
T47	0	1	0	0
T52	50874	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	1003	0	0
T2	357412	1	0	0
T3	516247	6	0	0
T4	386610	0	0	0
T5	285729	0	0	0
T13	577570	1	0	0
T14	0	3	0	0
T15	0	1	0	0
T16	0	1	0	0
T19	8016	0	0	0
T20	70896	2	0	0
T21	60592	2	0	0
T22	27778	0	0	0
T25	0	1	0	0
T47	0	1	0	0
T52	50874	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	975	0	0
T2	357412	1	0	0
T3	516247	6	0	0
T4	386610	0	0	0
T5	285729	0	0	0
T13	577570	1	0	0
T14	0	3	0	0
T15	0	1	0	0
T16	0	1	0	0
T19	8016	0	0	0
T20	70896	2	0	0
T21	60592	2	0	0
T22	27778	0	0	0
T25	0	1	0	0
T47	0	1	0	0
T52	50874	0	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	951	0	0
T2	357412	1	0	0
T3	516247	6	0	0
T4	386610	0	0	0
T5	285729	0	0	0
T13	577570	1	0	0
T14	0	3	0	0
T15	0	1	0	0
T16	0	1	0	0
T19	8016	0	0	0
T20	70896	2	0	0
T21	60592	2	0	0
T22	27778	0	0	0
T25	0	1	0	0
T47	0	1	0	0
T52	50874	0	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	1056	0	0
T3	516247	275	0	0
T4	386610	0	0	0
T5	285729	0	0	0
T13	577570	0	0	0
T14	0	1	0	0
T17	0	35	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	0	0	0
T22	27778	0	0	0
T23	0	14	0	0
T25	0	1	0	0
T46	86258	0	0	0
T49	0	1	0	0
T52	50874	2	0	0
T53	0	3	0	0
T87	0	1	0	0
T88	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	108435	0	0
T3	516247	18978	0	0
T4	386610	0	0	0
T5	285729	0	0	0
T13	577570	0	0	0
T14	0	184	0	0
T17	0	1997	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	0	0	0
T22	27778	0	0	0
T23	0	2704	0	0
T25	0	304	0	0
T46	86258	0	0	0
T49	0	235	0	0
T52	50874	360	0	0
T53	0	442	0	0
T87	0	214	0	0
T88	0	26	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	925	0	0
T3	516247	275	0	0
T4	386610	0	0	0
T5	285729	0	0	0
T13	577570	0	0	0
T17	0	33	0	0
T19	8016	0	0	0
T20	70896	0	0	0
T21	60592	0	0	0
T22	27778	0	0	0
T23	0	13	0	0
T26	0	6	0	0
T28	0	1	0	0
T46	86258	0	0	0
T52	50874	2	0	0
T53	0	3	0	0
T86	0	4	0	0
T87	0	1	0	0
T88	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	75	0	0
T6	542242	0	0	0
T14	387075	1	0	0
T15	868527	0	0	0
T16	497603	0	0	0
T17	0	2	0	0
T23	0	1	0	0
T25	109850	1	0	0
T26	0	2	0	0
T28	0	1	0	0
T47	32001	0	0	0
T48	2440	0	0	0
T49	11268	1	0	0
T50	38998	0	0	0
T51	60565	0	0	0
T56	0	1	0	0
T58	0	3	0	0
T90	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	1345	0	0
T10	53947	200	0	0
T11	0	399	0	0
T12	0	167	0	0
T35	0	399	0	0
T36	0	180	0	0
T37	83478	0	0	0
T38	36786	0	0	0
T39	374018	0	0	0
T40	46337	0	0	0
T41	149983	0	0	0
T42	124878	0	0	0
T43	66385	0	0	0
T44	84486	0	0	0
T45	644898	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	1135	0	0
T10	53947	170	0	0
T11	0	339	0	0
T12	0	137	0	0
T35	0	339	0	0
T36	0	150	0	0
T37	83478	0	0	0
T38	36786	0	0	0
T39	374018	0	0	0
T40	46337	0	0	0
T41	149983	0	0	0
T42	124878	0	0	0
T43	66385	0	0	0
T44	84486	0	0	0
T45	644898	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	732912797	732841571	0	0
T1	38467	38300	0	0
T2	357412	357334	0	0
T3	516247	516234	0	0
T4	386610	386601	0	0
T5	285729	285724	0	0
T13	577570	577563	0	0
T19	8016	7952	0	0
T20	70896	70802	0	0
T21	60592	60497	0	0
T22	27778	27693	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	733097492	732937064	0	0
T1	38467	38300	0	0
T2	357412	357334	0	0
T3	516247	516234	0	0
T4	386610	386601	0	0
T5	285729	285724	0	0
T13	577570	577563	0	0
T19	8016	7952	0	0
T20	70896	70802	0	0
T21	60592	60497	0	0
T22	27778	27693	0	0