Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	90790	1			T6	6		T17	1		T29	45
class_i[0x1]	59758	1			T29	119		T18	1059		T58	6
class_i[0x2]	59360	1			T4	12		T29	766		T18	1551
class_i[0x3]	66853	1			T4	13		T17	7		T18	3303

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	71547	1			T4	5		T6	1		T29	235
alert[0x1]	71093	1			T6	1		T17	1		T29	212
alert[0x2]	65324	1			T4	8		T17	7		T29	210
alert[0x3]	68797	1			T4	12		T6	4		T29	273

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

276491

1

T4

25

T6

6

T17

8

esc_ping_fail

270

1

T9

10

T12

3

T13

7

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	71469	1			T4	5		T6	1		T29	235
esc_integrity_fail	alert[0x1]	71022	1			T6	1		T17	1		T29	212
esc_integrity_fail	alert[0x2]	65258	1			T4	8		T17	7		T29	210
esc_integrity_fail	alert[0x3]	68742	1			T4	12		T6	4		T29	273
esc_ping_fail	alert[0x0]	78	1			T9	3		T12	1		T13	2
esc_ping_fail	alert[0x1]	71	1			T9	1		T12	1		T13	2
esc_ping_fail	alert[0x2]	66	1			T9	4		T13	2		T298	1
esc_ping_fail	alert[0x3]	55	1			T9	2		T12	1		T13	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	90716	1			T6	6		T17	1		T29	45
esc_integrity_fail	class_i[0x1]	59674	1			T29	119		T18	1059		T58	6
esc_integrity_fail	class_i[0x2]	59310	1			T4	12		T29	766		T18	1551
esc_integrity_fail	class_i[0x3]	66791	1			T4	13		T17	7		T18	3303
esc_ping_fail	class_i[0x0]	74	1			T9	10		T298	3		T92	8
esc_ping_fail	class_i[0x1]	84	1			T13	5		T92	1		T107	4
esc_ping_fail	class_i[0x2]	50	1			T12	3		T13	2		T191	3
esc_ping_fail	class_i[0x3]	62	1			T300	6		T301	5		T307	1