Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	711093775	0	0	629
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	711093775	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	711093775	710920382	0	0
tb.dut.CheckAccuCntDw	0	0	629	629	0	0
tb.dut.CheckEscCntDw	0	0	629	629	0	0
tb.dut.CheckNAlerts	0	0	629	629	0	0
tb.dut.CheckNClasses	0	0	629	629	0	0
tb.dut.CheckNEscSev	0	0	629	629	0	0
tb.dut.CrashdumpKnownO_A	0	0	711093775	710920382	0	0
tb.dut.EdnKnownO_A	0	0	711093775	710920382	0	0
tb.dut.EscPKnownO_A	0	0	711093775	710920382	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	711093775	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	711093775	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	711093775	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	711093775	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	711093775	80	0	0
tb.dut.IrqAKnownO_A	0	0	711093775	710920382	0	0
tb.dut.IrqBKnownO_A	0	0	711093775	710920382	0	0
tb.dut.IrqCKnownO_A	0	0	711093775	710920382	0	0
tb.dut.IrqDKnownO_A	0	0	711093775	710920382	0	0
tb.dut.TlAReadyKnownO_A	0	0	711093775	710920382	0	0
tb.dut.TlDValidKnownO_A	0	0	711093775	710920382	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	738247073	3436988	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	738247073	19440	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	738247073	19422	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	738247073	19347	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	738247073	20542	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	738247073	20246	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	738247073	19675	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	738247073	18873	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	738247073	20062	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	738247073	20071	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	738247073	19621	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	738247073	19457	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	738247073	20411	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	738247073	19581	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	738247073	20816	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	738247073	19503	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	738247073	19925	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	738247073	19544	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	738247073	20597	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	738247073	20141	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	738247073	19739	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	738247073	19649	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	738247073	19684	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	738247073	19970	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	738247073	20157	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	738247073	21241	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	738247073	20172	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	738247073	19716	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	738247073	19359	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	738247073	20583	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	738247073	19296	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	738247073	19189	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	738247073	19554	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	738247073	19542	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	738247073	19351	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	738247073	19676	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	738247073	19459	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	738247073	20336	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	738247073	19761	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	738247073	20703	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	738247073	20012	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	738247073	19508	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	738247073	19642	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	738247073	19563	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	738247073	20444	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	738247073	19935	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	738247073	20164	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	738247073	19215	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	738247073	20771	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	738247073	18962	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	738247073	19344	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	738247073	19195	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	738247073	19499	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	738247073	20118	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	738247073	20255	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	738247073	19419	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	738247073	19466	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	738247073	20824	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	738247073	19006	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	738247073	19453	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	738247073	19742	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	738247073	19896	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	738247073	19355	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	738247073	19878	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	738247073	19981	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	738247073	19038	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	738247073	19807	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	738247073	19723	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	738247073	19433	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	738247073	19758	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	738247073	35615	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	738247073	19579	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	738247073	19975	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	738247073	20653	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	738247073	20598	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	738247073	20201	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	738247073	19430	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	738247073	19351	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	738247073	20627	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	711093775	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	711093775	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	711093775	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	711093775	4067	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	711093775	225687	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	711093775	375605876	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	711093775	248	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	711093775	891	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	711093775	46	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	711093775	439	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	710915653	283987348	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	711093775	968	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	711093775	947	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	711093775	928	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	711093775	904	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	711093775	1740	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	711093775	153944	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	711093775	1630	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	711093775	62	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	711093775	1431	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	711093775	1191	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	710914142	710842289	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	629	629	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	711093775	710920382	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	711093775	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	711093775	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	711093775	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	711093775	5655	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	711093775	230138	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	711093775	410649498	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	711093775	276	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	711093775	501	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	711093775	20	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	711093775	213	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	710915653	342781969	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	711093775	575	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	711093775	565	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	711093775	558	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	711093775	548	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	711093775	855	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	711093775	99456	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	711093775	773	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	711093775	62	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	711093775	1460	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	711093775	1220	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	710914142	710842289	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	629	629	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	711093775	710920382	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	711093775	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	711093775	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	711093775	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	711093775	3102	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	711093775	222312	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	711093775	351085568	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	711093775	240	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	711093775	526	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	711093775	28	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	711093775	261	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	710915653	264171781	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	711093775	624	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	711093775	609	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	711093775	594	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	711093775	578	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	711093775	1571	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	711093775	163377	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	711093775	1465	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	711093775	77	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	711093775	1410	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	711093775	1170	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	710914142	710842289	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	629	629	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	711093775	710920382	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	711093775	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	711093775	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	711093775	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	711093775	631	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	711093775	159617	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	711093775	416772530	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	711093775	364	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	711093775	510	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	711093775	23	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	711093775	256	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	710915653	320627481	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	711093775	612	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	711093775	603	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	711093775	592	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	711093775	574	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	711093775	1149	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	711093775	107749	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	711093775	1036	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	711093775	89	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	711093775	1512	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	711093775	1272	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	710914142	710842289	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	629	629	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	711093775	710920382	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	738247073	138461523	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	738247073	737595220	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	738247073	737595220	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	738247073	193865746	0	0
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