Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	3	41	93.18

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	3	41	93.18	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	150	1			T22	1		T29	2		T18	1
index[0x1]	185	1			T6	3		T21	1		T24	1
index[0x2]	201	1			T5	1		T17	2		T29	2
index[0x3]	201	1			T4	3		T6	1		T22	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	250	1			T5	1		T21	1		T22	1
lens_less_than_1000[1]	143	1			T4	3		T22	1		T10	1
lens_less_than_1000[2]	94	1			T6	4		T24	2		T29	1
lens_less_than_1000[3]	74	1			T17	2		T29	1		T64	1
lens_less_than_1000[4]	48	1			T29	1		T39	2		T67	1
lens_less_than_1000[5]	35	1			T228	1		T77	1		T50	1
lens_less_than_1000[6]	53	1			T29	1		T39	2		T86	1
lens_less_than_1000[7]	12	1			T80	2		T254	1		T100	1
lens_less_than_1000[8]	17	1			T247	1		T47	1		T255	1
lens_less_than_1000[9]	2	1			T100	1		T256	1		-	-
len_2	9	1			T257	1		T258	1		T102	2

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	3	41	93.18	3

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x1]]	[lens_less_than_1000[9] , len_2]	--	--	2
[index[0x2]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	49	1			T29	1		T18	1		T19	1
index[0x0]	lens_less_than_1000[1]	29	1			T22	1		T30	1		T70	1
index[0x0]	lens_less_than_1000[2]	16	1			T19	1		T108	1		T259	1
index[0x0]	lens_less_than_1000[3]	18	1			T29	1		T30	1		T32	2
index[0x0]	lens_less_than_1000[4]	11	1			T44	1		T84	1		T54	1
index[0x0]	lens_less_than_1000[5]	9	1			T228	1		T77	1		T102	1
index[0x0]	lens_less_than_1000[6]	8	1			T84	1		T241	1		T260	3
index[0x0]	lens_less_than_1000[7]	1	1			T254	1		-	-		-	-
index[0x0]	lens_less_than_1000[8]	5	1			T255	1		T261	3		T262	1
index[0x0]	lens_less_than_1000[9]	1	1			T256	1		-	-		-	-
index[0x0]	len_2	3	1			T102	2		T263	1		-	-
index[0x1]	lens_less_than_1000[0]	60	1			T21	1		T18	3		T31	1
index[0x1]	lens_less_than_1000[1]	36	1			T38	1		T70	1		T72	1
index[0x1]	lens_less_than_1000[2]	30	1			T6	3		T24	1		T29	1
index[0x1]	lens_less_than_1000[3]	13	1			T42	2		T47	2		T51	1
index[0x1]	lens_less_than_1000[4]	19	1			T30	2		T84	2		T217	1
index[0x1]	lens_less_than_1000[5]	9	1			T264	1		T102	1		T265	1
index[0x1]	lens_less_than_1000[6]	13	1			T39	1		T42	1		T50	1
index[0x1]	lens_less_than_1000[7]	2	1			T266	1		T267	1		-	-
index[0x1]	lens_less_than_1000[8]	3	1			T247	1		T243	1		T268	1
index[0x2]	lens_less_than_1000[0]	71	1			T5	1		T18	1		T66	2
index[0x2]	lens_less_than_1000[1]	37	1			T108	1		T30	2		T269	1
index[0x2]	lens_less_than_1000[2]	20	1			T18	1		T19	1		T50	1
index[0x2]	lens_less_than_1000[3]	21	1			T17	2		T64	1		T270	1
index[0x2]	lens_less_than_1000[4]	9	1			T29	1		T39	2		T42	1
index[0x2]	lens_less_than_1000[5]	9	1			T50	1		T102	2		T89	2
index[0x2]	lens_less_than_1000[6]	21	1			T29	1		T86	1		T42	1
index[0x2]	lens_less_than_1000[7]	4	1			T100	1		T243	1		T271	1
index[0x2]	lens_less_than_1000[8]	5	1			T47	1		T243	1		T272	1
index[0x2]	len_2	4	1			T257	1		T258	1		T273	1
index[0x3]	lens_less_than_1000[0]	70	1			T22	1		T11	1		T66	2
index[0x3]	lens_less_than_1000[1]	41	1			T4	3		T10	1		T62	1
index[0x3]	lens_less_than_1000[2]	28	1			T6	1		T24	1		T39	1
index[0x3]	lens_less_than_1000[3]	22	1			T32	3		T27	1		T248	3
index[0x3]	lens_less_than_1000[4]	9	1			T67	1		T70	1		T78	1
index[0x3]	lens_less_than_1000[5]	8	1			T180	1		T264	1		T274	1
index[0x3]	lens_less_than_1000[6]	11	1			T39	1		T255	1		T103	1
index[0x3]	lens_less_than_1000[7]	5	1			T80	2		T275	3		-	-
index[0x3]	lens_less_than_1000[8]	4	1			T276	1		T243	1		T244	2
index[0x3]	lens_less_than_1000[9]	1	1			T100	1		-	-		-	-
index[0x3]	len_2	2	1			T277	2		-	-		-	-