Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	62	1			T22	1		T18	2		T68	1
class_index[0x1]	62	1			T21	1		T23	2		T29	1
class_index[0x2]	77	1			T18	1		T26	1		T61	1
class_index[0x3]	89	1			T23	5		T24	3		T18	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	117	1			T21	1		T22	1		T23	7
intr_timeout_cnt[1]	68	1			T24	3		T108	1		T61	1
intr_timeout_cnt[2]	36	1			T18	3		T19	1		T26	1
intr_timeout_cnt[3]	12	1			T18	1		T38	1		T42	1
intr_timeout_cnt[4]	14	1			T56	1		T278	1		T279	2
intr_timeout_cnt[5]	14	1			T108	1		T50	1		T54	2
intr_timeout_cnt[6]	8	1			T32	1		T48	1		T278	1
intr_timeout_cnt[7]	11	1			T18	1		T32	1		T52	2
intr_timeout_cnt[8]	4	1			T80	1		T55	1		T280	1
intr_timeout_cnt[9]	6	1			T18	1		T281	1		T99	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x1]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[6]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	29	1			T22	1		T68	1		T27	1
class_index[0x0]	intr_timeout_cnt[1]	13	1			T69	1		T71	1		T42	1
class_index[0x0]	intr_timeout_cnt[2]	6	1			T18	1		T30	1		T72	1
class_index[0x0]	intr_timeout_cnt[3]	2	1			T42	1		T54	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	3	1			T280	3		-	-		-	-
class_index[0x0]	intr_timeout_cnt[5]	3	1			T54	1		T282	1		T277	1
class_index[0x0]	intr_timeout_cnt[6]	1	1			T265	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	2	1			T52	1		T243	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	1	1			T272	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T18	1		T283	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	30	1			T21	1		T23	2		T29	1
class_index[0x1]	intr_timeout_cnt[1]	9	1			T284	1		T285	1		T52	1
class_index[0x1]	intr_timeout_cnt[2]	6	1			T18	1		T54	1		T111	1
class_index[0x1]	intr_timeout_cnt[3]	4	1			T18	1		T243	1		T286	1
class_index[0x1]	intr_timeout_cnt[4]	3	1			T278	1		T279	1		T244	1
class_index[0x1]	intr_timeout_cnt[5]	3	1			T287	1		T279	1		T252	1
class_index[0x1]	intr_timeout_cnt[6]	3	1			T32	1		T48	1		T279	1
class_index[0x1]	intr_timeout_cnt[7]	3	1			T56	1		T264	1		T288	1
class_index[0x1]	intr_timeout_cnt[9]	1	1			T99	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	22	1			T71	1		T46	1		T289	1
class_index[0x2]	intr_timeout_cnt[1]	20	1			T61	1		T32	4		T27	1
class_index[0x2]	intr_timeout_cnt[2]	15	1			T26	1		T290	1		T102	1
class_index[0x2]	intr_timeout_cnt[3]	4	1			T242	1		T291	1		T243	1
class_index[0x2]	intr_timeout_cnt[4]	6	1			T56	1		T243	2		T244	1
class_index[0x2]	intr_timeout_cnt[5]	3	1			T54	1		T102	1		T292	1
class_index[0x2]	intr_timeout_cnt[7]	4	1			T18	1		T52	1		T287	1
class_index[0x2]	intr_timeout_cnt[8]	2	1			T80	1		T55	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T293	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	36	1			T23	5		T42	1		T84	2
class_index[0x3]	intr_timeout_cnt[1]	26	1			T24	3		T108	1		T69	1
class_index[0x3]	intr_timeout_cnt[2]	9	1			T18	1		T19	1		T177	1
class_index[0x3]	intr_timeout_cnt[3]	2	1			T38	1		T272	1		-	-
class_index[0x3]	intr_timeout_cnt[4]	2	1			T279	1		T275	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	5	1			T108	1		T50	1		T243	1
class_index[0x3]	intr_timeout_cnt[6]	4	1			T278	1		T294	1		T293	1
class_index[0x3]	intr_timeout_cnt[7]	2	1			T32	1		T295	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T280	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	2	1			T281	1		T296	1		-	-