Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	363869	1			T1	37		T2	23		T3	37
all_values[1]	363869	1			T1	37		T2	23		T3	37
all_values[2]	363869	1			T1	37		T2	23		T3	37
all_values[3]	363869	1			T1	37		T2	23		T3	37

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

723863

1

T1

79

T2

43

T3

71

auto[1]

731613

1

T1

69

T2

49

T3

77

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

851096

1

T1

76

T2

49

T3

146

auto[1]

604380

1

T1

72

T2

43

T3

2

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	102664	1			T1	10		T2	9		T3	16
all_values[0]	auto[0]	auto[1]	78205	1			T1	9		T2	6		T4	296
all_values[0]	auto[1]	auto[0]	104293	1			T1	9		T2	4		T3	19
all_values[0]	auto[1]	auto[1]	78707	1			T1	9		T2	4		T3	2
all_values[1]	auto[0]	auto[0]	106744	1			T1	12		T2	6		T3	20
all_values[1]	auto[0]	auto[1]	74387	1			T1	11		T2	5		T4	304
all_values[1]	auto[1]	auto[0]	108141	1			T1	7		T2	6		T3	17
all_values[1]	auto[1]	auto[1]	74597	1			T1	7		T2	6		T4	291
all_values[2]	auto[0]	auto[0]	106265	1			T1	9		T2	5		T3	23
all_values[2]	auto[0]	auto[1]	74300	1			T1	9		T2	5		T4	293
all_values[2]	auto[1]	auto[0]	108432	1			T1	10		T2	7		T3	14
all_values[2]	auto[1]	auto[1]	74872	1			T1	9		T2	6		T4	287
all_values[3]	auto[0]	auto[0]	106619	1			T1	10		T2	4		T3	12
all_values[3]	auto[0]	auto[1]	74679	1			T1	9		T2	3		T4	312
all_values[3]	auto[1]	auto[0]	107938	1			T1	9		T2	8		T3	25
all_values[3]	auto[1]	auto[1]	74633	1			T1	9		T2	8		T4	295