Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	363869	1			T1	37		T2	23		T3	37
all_pins[1]	363869	1			T1	37		T2	23		T3	37
all_pins[2]	363869	1			T1	37		T2	23		T3	37
all_pins[3]	363869	1			T1	37		T2	23		T3	37

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1152667	1			T1	114		T2	68		T3	146
values[0x1]	302809	1			T1	34		T2	24		T3	2
transitions[0x0=>0x1]	199686	1			T1	22		T2	14		T3	1
transitions[0x1=>0x0]	199946	1			T1	22		T2	14		T3	2

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	285162	1			T1	28		T2	19		T3	35
all_pins[0]	values[0x1]	78707	1			T1	9		T2	4		T3	2
all_pins[0]	transitions[0x0=>0x1]	78031	1			T1	9		T2	4		T3	1
all_pins[0]	transitions[0x1=>0x0]	74217	1			T1	9		T2	8		T4	295
all_pins[1]	values[0x0]	289272	1			T1	30		T2	17		T3	37
all_pins[1]	values[0x1]	74597	1			T1	7		T2	6		T4	291
all_pins[1]	transitions[0x0=>0x1]	40263	1			T1	3		T2	3		T4	143
all_pins[1]	transitions[0x1=>0x0]	44373	1			T1	5		T2	1		T3	2
all_pins[2]	values[0x0]	288997	1			T1	28		T2	17		T3	37
all_pins[2]	values[0x1]	74872	1			T1	9		T2	6		T4	287
all_pins[2]	transitions[0x0=>0x1]	40703	1			T1	6		T2	3		T4	142
all_pins[2]	transitions[0x1=>0x0]	40428	1			T1	4		T2	3		T4	146
all_pins[3]	values[0x0]	289236	1			T1	28		T2	15		T3	37
all_pins[3]	values[0x1]	74633	1			T1	9		T2	8		T4	295
all_pins[3]	transitions[0x0=>0x1]	40689	1			T1	4		T2	4		T4	161
all_pins[3]	transitions[0x1=>0x0]	40928	1			T1	4		T2	2		T4	153