Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	102782	1			T4	618		T6	1646		T17	37
accum_cnt_1000	250455	1			T4	1061		T5	498		T6	1676
accum_cnt_100	29034	1			T4	59		T5	122		T6	98
accum_cnt_50	67544	1			T1	46		T2	10		T4	50
accum_cnt_10	183279	1			T1	77		T2	41		T3	27
accum_cnt_0	397469	1			T1	21		T2	37		T3	81

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	268881	1			T1	36		T2	22		T3	27
class_index[0x1]	268881	1			T1	36		T2	22		T3	27
class_index[0x2]	268881	1			T1	36		T2	22		T3	27
class_index[0x3]	268881	1			T1	36		T2	22		T3	27

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	25232	1			T8	181		T26	386		T66	616
class_index[0x0]	accum_cnt_1000	64388	1			T29	108		T8	726		T18	1369
class_index[0x0]	accum_cnt_100	9154	1			T29	12		T8	45		T18	131
class_index[0x0]	accum_cnt_50	16681	1			T1	24		T2	10		T20	22
class_index[0x0]	accum_cnt_10	47303	1			T1	9		T2	8		T3	27
class_index[0x0]	accum_cnt_0	93547	1			T1	3		T2	4		T5	795
class_index[0x1]	accum_cnt_2000	24092	1			T4	199		T6	536		T8	390
class_index[0x1]	accum_cnt_1000	61975	1			T4	637		T6	496		T29	19
class_index[0x1]	accum_cnt_100	6695	1			T4	34		T6	30		T29	26
class_index[0x1]	accum_cnt_50	14351	1			T1	14		T4	31		T20	20
class_index[0x1]	accum_cnt_10	42769	1			T1	18		T2	22		T4	9
class_index[0x1]	accum_cnt_0	106395	1			T1	4		T3	27		T4	4
class_index[0x2]	accum_cnt_2000	30491	1			T6	607		T18	446		T19	22
class_index[0x2]	accum_cnt_1000	68610	1			T5	498		T6	731		T29	231
class_index[0x2]	accum_cnt_100	6901	1			T5	122		T6	42		T29	29
class_index[0x2]	accum_cnt_50	18007	1			T5	129		T20	20		T6	36
class_index[0x2]	accum_cnt_10	40873	1			T1	33		T2	9		T4	1
class_index[0x2]	accum_cnt_0	91403	1			T1	3		T2	13		T3	27
class_index[0x3]	accum_cnt_2000	22967	1			T4	419		T6	503		T17	37
class_index[0x3]	accum_cnt_1000	55482	1			T4	424		T6	449		T17	571
class_index[0x3]	accum_cnt_100	6284	1			T4	25		T6	26		T17	36
class_index[0x3]	accum_cnt_50	18505	1			T1	8		T4	19		T6	23
class_index[0x3]	accum_cnt_10	52334	1			T1	17		T2	2		T4	16
class_index[0x3]	accum_cnt_0	106124	1			T1	11		T2	20		T3	27