Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	69	0	69	100.00
Crosses	260	0	260	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_cause_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
alert_cause_cross_class_index	260	0	260	100.00	100	1	1	0

Summary for Variable alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	34433	1			T1	10		T2	4		T4	153
alert[0x1]	28090	1			T1	4		T4	154		T6	240
alert[0x2]	29444	1			T1	6		T2	5		T4	155
alert[0x3]	33184	1			T1	2		T2	2		T4	156
alert[0x4]	30857	1			T1	1		T2	6		T4	153
alert[0x5]	35250	1			T1	10		T4	132		T20	10
alert[0x6]	33451	1			T1	6		T2	2		T4	137
alert[0x7]	34941	1			T1	8		T2	6		T4	160
alert[0x8]	34156	1			T1	1		T2	2		T4	157
alert[0x9]	31113	1			T1	1		T2	3		T4	142
alert[0xa]	38418	1			T1	1		T4	153		T6	227
alert[0xb]	30172	1			T1	5		T4	157		T20	8
alert[0xc]	30689	1			T1	6		T2	1		T4	145
alert[0xd]	31897	1			T1	7		T2	3		T4	147
alert[0xe]	33280	1			T1	5		T2	1		T3	1
alert[0xf]	29432	1			T1	3		T4	137		T20	1
alert[0x10]	33698	1			T2	2		T4	144		T20	1
alert[0x11]	29738	1			T1	7		T4	166		T20	14
alert[0x12]	30322	1			T2	8		T4	178		T20	12
alert[0x13]	39007	1			T2	1		T4	151		T20	10
alert[0x14]	34818	1			T1	9		T2	4		T4	158
alert[0x15]	36443	1			T1	1		T2	5		T4	156
alert[0x16]	38234	1			T1	6		T4	137		T20	1
alert[0x17]	31811	1			T2	7		T4	164		T20	5
alert[0x18]	34257	1			T1	7		T2	6		T3	1
alert[0x19]	31143	1			T1	1		T2	5		T4	156
alert[0x1a]	32405	1			T1	1		T2	3		T4	146
alert[0x1b]	32501	1			T1	3		T2	5		T4	144
alert[0x1c]	37682	1			T1	5		T4	153		T20	6
alert[0x1d]	33867	1			T1	2		T2	1		T4	143
alert[0x1e]	30887	1			T1	4		T4	162		T20	8
alert[0x1f]	34379	1			T2	4		T4	156		T5	1
alert[0x20]	32995	1			T1	6		T2	5		T4	132
alert[0x21]	31688	1			T1	4		T4	160		T20	12
alert[0x22]	38017	1			T2	1		T4	163		T5	263
alert[0x23]	31251	1			T1	2		T2	1		T4	144
alert[0x24]	30583	1			T1	8		T2	5		T4	160
alert[0x25]	29806	1			T1	9		T4	165		T6	237
alert[0x26]	33178	1			T1	9		T4	146		T6	235
alert[0x27]	34578	1			T1	6		T2	5		T4	150
alert[0x28]	35988	1			T1	9		T2	1		T4	143
alert[0x29]	28563	1			T2	3		T4	149		T20	12
alert[0x2a]	34560	1			T1	2		T2	6		T4	142
alert[0x2b]	32643	1			T1	8		T4	154		T5	272
alert[0x2c]	34647	1			T1	1		T2	9		T4	151
alert[0x2d]	30540	1			T1	2		T2	1		T4	142
alert[0x2e]	32978	1			T2	6		T4	151		T20	10
alert[0x2f]	34078	1			T1	8		T4	154		T20	5
alert[0x30]	32210	1			T1	4		T4	163		T20	5
alert[0x31]	31828	1			T1	6		T4	160		T6	215
alert[0x32]	32747	1			T1	2		T2	6		T4	151
alert[0x33]	31401	1			T1	3		T4	157		T20	6
alert[0x34]	34915	1			T1	11		T2	2		T4	152
alert[0x35]	31528	1			T1	2		T2	5		T4	152
alert[0x36]	31989	1			T1	1		T2	9		T4	144
alert[0x37]	31785	1			T1	1		T2	3		T4	154
alert[0x38]	36282	1			T1	10		T4	163		T6	231
alert[0x39]	30157	1			T1	3		T2	3		T4	170
alert[0x3a]	32341	1			T1	7		T2	2		T4	154
alert[0x3b]	32942	1			T1	1		T2	2		T4	164
alert[0x3c]	31786	1			T1	1		T4	162		T20	6
alert[0x3d]	32424	1			T1	2		T2	1		T4	141
alert[0x3e]	32802	1			T1	5		T4	138		T20	9
alert[0x3f]	30809	1			T4	142		T20	1		T6	245
alert[0x40]	32032	1			T1	10		T2	5		T4	160

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	571679	1			T1	66		T2	44		T3	2
class_i[0x1]	528234	1			T1	45		T2	34		T4	1987
class_i[0x2]	526544	1			T1	71		T2	47		T4	1700
class_i[0x3]	509613	1			T1	83		T2	42		T4	4248

---

Summary for Cross alert_cause_cross_class_index

Samples crossed: alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	260	0	260	100.00

Automatically Generated Cross Bins for alert_cause_cross_class_index

Bins

alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	class_i[0x0]	9214	1			T1	1		T20	3		T6	252
alert[0x0]	class_i[0x1]	9663	1			T1	8		T2	2		T24	1
alert[0x0]	class_i[0x2]	9010	1			T1	1		T20	4		T24	1
alert[0x0]	class_i[0x3]	6546	1			T2	2		T4	153		T21	1
alert[0x1]	class_i[0x0]	8505	1			T1	1		T6	240		T21	1
alert[0x1]	class_i[0x1]	6512	1			T22	1		T24	4		T29	11
alert[0x1]	class_i[0x2]	5499	1			T1	2		T21	4		T24	2
alert[0x1]	class_i[0x3]	7574	1			T1	1		T4	154		T22	1
alert[0x2]	class_i[0x0]	6752	1			T2	1		T21	1		T24	1
alert[0x2]	class_i[0x1]	9537	1			T1	2		T21	1		T22	13
alert[0x2]	class_i[0x2]	7701	1			T4	155		T6	260		T21	2
alert[0x2]	class_i[0x3]	5454	1			T1	4		T2	4		T17	117
alert[0x3]	class_i[0x0]	10413	1			T2	1		T4	156		T6	252
alert[0x3]	class_i[0x1]	8240	1			T2	1		T21	1		T24	1
alert[0x3]	class_i[0x2]	8877	1			T20	5		T21	3		T23	10
alert[0x3]	class_i[0x3]	5654	1			T1	2		T24	1		T29	67
alert[0x4]	class_i[0x0]	8297	1			T6	228		T22	1		T29	1
alert[0x4]	class_i[0x1]	6088	1			T1	1		T21	2		T17	127
alert[0x4]	class_i[0x2]	8879	1			T2	6		T23	1		T29	1
alert[0x4]	class_i[0x3]	7593	1			T4	153		T20	7		T24	2
alert[0x5]	class_i[0x0]	9167	1			T1	1		T20	10		T21	4
alert[0x5]	class_i[0x1]	8293	1			T29	1		T18	345		T38	1
alert[0x5]	class_i[0x2]	8426	1			T1	2		T4	132		T6	227
alert[0x5]	class_i[0x3]	9364	1			T1	7		T29	2		T8	354
alert[0x6]	class_i[0x0]	10723	1			T1	3		T2	2		T4	137
alert[0x6]	class_i[0x1]	6769	1			T1	1		T21	1		T22	1
alert[0x6]	class_i[0x2]	8832	1			T1	1		T22	1		T24	2
alert[0x6]	class_i[0x3]	7127	1			T1	1		T24	1		T29	35
alert[0x7]	class_i[0x0]	8189	1			T1	8		T5	2		T21	2
alert[0x7]	class_i[0x1]	9421	1			T5	1		T20	1		T6	237
alert[0x7]	class_i[0x2]	6723	1			T5	2		T20	1		T29	8
alert[0x7]	class_i[0x3]	10608	1			T2	6		T4	160		T21	1
alert[0x8]	class_i[0x0]	8146	1			T2	2		T21	4		T29	1
alert[0x8]	class_i[0x1]	8324	1			T57	1		T33	1		T38	1
alert[0x8]	class_i[0x2]	9464	1			T4	157		T20	1		T17	111
alert[0x8]	class_i[0x3]	8222	1			T1	1		T20	9		T6	231
alert[0x9]	class_i[0x0]	9582	1			T2	1		T29	38		T33	1
alert[0x9]	class_i[0x1]	7602	1			T1	1		T2	2		T4	142
alert[0x9]	class_i[0x2]	6620	1			T22	1		T29	27		T57	1
alert[0x9]	class_i[0x3]	7309	1			T6	226		T21	7		T17	114
alert[0xa]	class_i[0x0]	10590	1			T1	1		T4	153		T24	6
alert[0xa]	class_i[0x1]	7189	1			T6	227		T24	1		T18	54
alert[0xa]	class_i[0x2]	11816	1			T17	119		T29	1		T18	422
alert[0xa]	class_i[0x3]	8823	1			T22	7		T23	5		T29	3
alert[0xb]	class_i[0x0]	7222	1			T1	2		T20	7		T21	3
alert[0xb]	class_i[0x1]	8937	1			T1	1		T4	157		T20	1
alert[0xb]	class_i[0x2]	6728	1			T1	1		T24	2		T17	120
alert[0xb]	class_i[0x3]	7285	1			T1	1		T6	240		T23	1
alert[0xc]	class_i[0x0]	8204	1			T1	1		T2	1		T20	9
alert[0xc]	class_i[0x1]	7023	1			T1	1		T24	1		T29	13
alert[0xc]	class_i[0x2]	8166	1			T22	11		T24	7		T29	34
alert[0xc]	class_i[0x3]	7296	1			T1	4		T4	145		T6	239
alert[0xd]	class_i[0x0]	8935	1			T6	239		T29	32		T37	1
alert[0xd]	class_i[0x1]	9086	1			T2	3		T4	147		T21	1
alert[0xd]	class_i[0x2]	6794	1			T1	2		T20	9		T23	1
alert[0xd]	class_i[0x3]	7082	1			T1	5		T21	1		T22	2
alert[0xe]	class_i[0x0]	9706	1			T1	2		T3	1		T23	1
alert[0xe]	class_i[0x1]	8774	1			T2	1		T21	1		T22	7
alert[0xe]	class_i[0x2]	8348	1			T1	1		T4	160		T6	248
alert[0xe]	class_i[0x3]	6452	1			T1	2		T20	5		T21	1
alert[0xf]	class_i[0x0]	6587	1			T1	1		T29	45		T18	137
alert[0xf]	class_i[0x1]	8075	1			T20	1		T6	238		T29	68
alert[0xf]	class_i[0x2]	6528	1			T1	1		T29	2		T57	5
alert[0xf]	class_i[0x3]	8242	1			T1	1		T4	137		T22	1
alert[0x10]	class_i[0x0]	8744	1			T2	2		T21	1		T29	29
alert[0x10]	class_i[0x1]	8825	1			T6	235		T22	6		T24	6
alert[0x10]	class_i[0x2]	8792	1			T22	1		T17	121		T29	2
alert[0x10]	class_i[0x3]	7337	1			T4	144		T20	1		T21	1
alert[0x11]	class_i[0x0]	10166	1			T6	232		T17	109		T18	188
alert[0x11]	class_i[0x1]	6769	1			T20	14		T24	1		T18	91
alert[0x11]	class_i[0x2]	5517	1			T21	3		T24	7		T29	111
alert[0x11]	class_i[0x3]	7286	1			T1	7		T4	166		T29	1
alert[0x12]	class_i[0x0]	6541	1			T20	12		T24	2		T29	64
alert[0x12]	class_i[0x1]	8676	1			T21	3		T22	6		T23	4
alert[0x12]	class_i[0x2]	7870	1			T2	8		T23	1		T17	112
alert[0x12]	class_i[0x3]	7235	1			T4	178		T6	220		T18	92
alert[0x13]	class_i[0x0]	11090	1			T21	1		T29	2		T18	3
alert[0x13]	class_i[0x1]	10072	1			T2	1		T6	240		T21	1
alert[0x13]	class_i[0x2]	8168	1			T22	1		T24	6		T29	42
alert[0x13]	class_i[0x3]	9677	1			T4	151		T20	10		T22	1
alert[0x14]	class_i[0x0]	8388	1			T20	3		T21	1		T22	6
alert[0x14]	class_i[0x1]	8096	1			T4	158		T5	1		T20	1
alert[0x14]	class_i[0x2]	9004	1			T1	9		T2	3		T6	251
alert[0x14]	class_i[0x3]	9330	1			T2	1		T20	2		T21	1
alert[0x15]	class_i[0x0]	8099	1			T2	4		T21	1		T29	4
alert[0x15]	class_i[0x1]	10074	1			T29	1		T18	47		T33	1
alert[0x15]	class_i[0x2]	10871	1			T1	1		T2	1		T23	7
alert[0x15]	class_i[0x3]	7399	1			T4	156		T20	9		T6	229
alert[0x16]	class_i[0x0]	10533	1			T29	35		T8	1		T18	57
alert[0x16]	class_i[0x1]	7583	1			T1	6		T20	1		T21	2
alert[0x16]	class_i[0x2]	11251	1			T21	1		T29	1		T18	201
alert[0x16]	class_i[0x3]	8867	1			T4	137		T6	230		T24	5
alert[0x17]	class_i[0x0]	7928	1			T20	1		T6	216		T23	4
alert[0x17]	class_i[0x1]	7843	1			T20	3		T24	1		T17	110
alert[0x17]	class_i[0x2]	7073	1			T2	7		T4	164		T57	1
alert[0x17]	class_i[0x3]	8967	1			T20	1		T29	71		T57	2
alert[0x18]	class_i[0x0]	9048	1			T2	6		T3	1		T21	3
alert[0x18]	class_i[0x1]	8244	1			T4	153		T6	225		T21	1
alert[0x18]	class_i[0x2]	7931	1			T1	1		T24	4		T17	116
alert[0x18]	class_i[0x3]	9034	1			T1	6		T21	2		T29	2
alert[0x19]	class_i[0x0]	8338	1			T1	1		T2	5		T21	2
alert[0x19]	class_i[0x1]	7642	1			T20	1		T6	225		T21	1
alert[0x19]	class_i[0x2]	7287	1			T22	8		T24	2		T29	3
alert[0x19]	class_i[0x3]	7876	1			T4	156		T20	2		T17	113
alert[0x1a]	class_i[0x0]	7239	1			T2	2		T4	146		T20	8
alert[0x1a]	class_i[0x1]	8036	1			T2	1		T24	5		T29	5
alert[0x1a]	class_i[0x2]	9886	1			T1	1		T6	241		T23	4
alert[0x1a]	class_i[0x3]	7244	1			T24	1		T17	122		T29	1
alert[0x1b]	class_i[0x0]	10383	1			T4	144		T21	2		T29	1
alert[0x1b]	class_i[0x1]	7866	1			T1	1		T20	2		T22	1
alert[0x1b]	class_i[0x2]	8796	1			T1	1		T2	3		T29	34
alert[0x1b]	class_i[0x3]	5456	1			T1	1		T2	2		T6	232
alert[0x1c]	class_i[0x0]	11333	1			T1	1		T20	2		T21	3
alert[0x1c]	class_i[0x1]	9698	1			T1	2		T20	1		T22	1
alert[0x1c]	class_i[0x2]	7481	1			T1	2		T20	2		T6	250
alert[0x1c]	class_i[0x3]	9170	1			T4	153		T20	1		T23	1
alert[0x1d]	class_i[0x0]	10700	1			T1	1		T22	1		T29	42
alert[0x1d]	class_i[0x1]	7019	1			T2	1		T23	7		T29	2
alert[0x1d]	class_i[0x2]	7921	1			T29	3		T8	331		T18	196
alert[0x1d]	class_i[0x3]	8227	1			T1	1		T4	143		T6	249
alert[0x1e]	class_i[0x0]	8109	1			T21	1		T29	35		T8	326
alert[0x1e]	class_i[0x1]	6723	1			T20	8		T29	1		T18	37
alert[0x1e]	class_i[0x2]	9305	1			T1	4		T4	162		T22	6
alert[0x1e]	class_i[0x3]	6750	1			T6	258		T23	1		T29	62
alert[0x1f]	class_i[0x0]	9677	1			T2	4		T4	156		T21	5
alert[0x1f]	class_i[0x1]	8264	1			T23	5		T24	1		T8	1
alert[0x1f]	class_i[0x2]	6421	1			T22	1		T24	4		T8	1
alert[0x1f]	class_i[0x3]	10017	1			T5	1		T20	8		T6	244
alert[0x20]	class_i[0x0]	11803	1			T1	6		T4	132		T6	228
alert[0x20]	class_i[0x1]	6742	1			T2	3		T18	1		T33	1
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alert[0x20]	class_i[0x3]	9109	1			T2	1		T20	12		T21	1
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alert[0x22]	class_i[0x1]	10662	1			T2	1		T6	254		T24	2
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alert[0x22]	class_i[0x3]	8690	1			T5	1		T22	13		T57	2
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alert[0x23]	class_i[0x2]	8883	1			T1	2		T24	7		T29	74
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alert[0x24]	class_i[0x1]	7510	1			T1	1		T4	160		T6	231
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alert[0x24]	class_i[0x3]	7757	1			T2	5		T29	3		T18	228
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alert[0x25]	class_i[0x1]	10103	1			T4	165		T29	13		T8	313
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alert[0x25]	class_i[0x3]	5131	1			T6	237		T21	4		T22	7
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alert[0x29]	class_i[0x3]	7908	1			T2	1		T4	149		T21	1
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alert[0x3e]	class_i[0x3]	9084	1			T20	1		T22	1		T29	8
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alert[0x3f]	class_i[0x3]	7720	1			T24	2		T29	38		T58	2
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alert[0x40]	class_i[0x3]	7927	1			T2	5		T4	160		T29	62