Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	2228	1			T4	43		T18	313		T32	34
alert[0x1]	12668	1			T108	2		T26	4		T41	321
alert[0x2]	14950	1			T4	101		T17	2		T38	8
alert[0x3]	7669	1			T4	102		T17	5		T18	13
alert[0x4]	6033	1			T17	24		T11	2		T41	2438
alert[0x5]	3058	1			T4	6		T17	665		T18	314
alert[0x6]	9722	1			T18	527		T9	1		T39	3
alert[0x7]	9071	1			T29	1		T18	38		T39	45
alert[0x8]	5553	1			T4	57		T17	18		T29	3
alert[0x9]	8072	1			T9	1		T26	11		T41	407
alert[0xa]	9226	1			T4	1266		T18	160		T9	1
alert[0xb]	3532	1			T4	218		T29	1		T18	91
alert[0xc]	2691	1			T18	96		T9	2		T13	1
alert[0xd]	11219	1			T4	9		T18	68		T9	1
alert[0xe]	7833	1			T18	11		T39	60		T41	31
alert[0xf]	8024	1			T4	358		T29	137		T18	6
alert[0x10]	4744	1			T9	1		T19	18		T12	1
alert[0x11]	7512	1			T4	56		T17	29		T29	1
alert[0x12]	3625	1			T6	8		T38	1		T39	71
alert[0x13]	3545	1			T17	17		T18	12		T39	410
alert[0x14]	4884	1			T4	6		T18	1279		T12	1
alert[0x15]	6332	1			T19	51		T64	3		T41	519
alert[0x16]	9114	1			T4	102		T17	755		T29	5
alert[0x17]	9800	1			T17	10		T29	19		T26	1
alert[0x18]	5754	1			T19	61		T39	30		T41	34
alert[0x19]	6214	1			T30	48		T92	1		T269	1
alert[0x1a]	2905	1			T18	15		T9	1		T12	1
alert[0x1b]	3166	1			T17	2		T18	171		T12	1
alert[0x1c]	8243	1			T6	5		T18	3		T13	1
alert[0x1d]	5920	1			T17	26		T29	1		T108	24
alert[0x1e]	7742	1			T19	23		T13	1		T41	235
alert[0x1f]	4492	1			T4	10		T17	97		T29	13
alert[0x20]	4069	1			T4	35		T19	65		T13	1
alert[0x21]	8720	1			T4	21		T9	1		T108	8
alert[0x22]	12906	1			T4	37		T29	13		T18	5
alert[0x23]	5722	1			T17	4		T9	1		T41	310
alert[0x24]	9312	1			T29	3		T12	1		T13	2
alert[0x25]	9631	1			T4	477		T18	21		T38	9
alert[0x26]	6500	1			T4	1395		T17	7		T29	7
alert[0x27]	7544	1			T18	2		T9	1		T39	162
alert[0x28]	7275	1			T29	3		T18	15		T108	15
alert[0x29]	4922	1			T4	65		T17	21		T18	8
alert[0x2a]	5865	1			T18	398		T26	20		T30	7
alert[0x2b]	13809	1			T6	13		T18	371		T19	26
alert[0x2c]	12000	1			T4	94		T19	230		T41	2724
alert[0x2d]	5161	1			T4	28		T26	28		T90	12
alert[0x2e]	7547	1			T4	16		T29	16		T38	2
alert[0x2f]	18560	1			T17	360		T18	25		T9	1
alert[0x30]	4053	1			T29	1		T18	102		T9	1
alert[0x31]	5742	1			T26	150		T90	99		T32	419
alert[0x32]	7759	1			T17	98		T19	53		T26	8
alert[0x33]	5655	1			T4	16		T29	7		T12	1
alert[0x34]	13212	1			T4	18		T19	2		T70	7
alert[0x35]	8044	1			T4	425		T18	5		T298	1
alert[0x36]	12280	1			T17	100		T18	93		T19	432
alert[0x37]	5944	1			T4	30		T9	1		T12	1
alert[0x38]	4317	1			T17	108		T29	1		T108	2
alert[0x39]	15327	1			T4	5		T17	191		T18	12
alert[0x3a]	8047	1			T17	271		T18	68		T9	1
alert[0x3b]	3679	1			T191	1		T30	10		T90	2
alert[0x3c]	6134	1			T4	1		T17	596		T29	2
alert[0x3d]	4562	1			T17	94		T18	757		T38	1
alert[0x3e]	5721	1			T191	1		T30	503		T92	1
alert[0x3f]	5430	1			T18	35		T64	8		T41	83
alert[0x40]	6221	1			T18	580		T38	2		T26	3

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	92937	1			T4	4997		T29	197		T38	13
class_i[0x1]	166133	1			T6	26		T29	30		T18	1288
class_i[0x2]	116609	1			T17	3478		T18	265		T9	17
class_i[0x3]	101532	1			T17	22		T29	7		T18	4217

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

476531

1

T4

4997

T6

26

T17

3500

alert_ping_fail

680

1

T9

18

T10

1

T11

2

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	2215	1			T4	43		T18	313		T32	34
alert_integrity_fail	alert[0x1]	12654	1			T108	2		T26	4		T41	321
alert_integrity_fail	alert[0x2]	14941	1			T4	101		T17	2		T38	8
alert_integrity_fail	alert[0x3]	7654	1			T4	102		T17	5		T18	13
alert_integrity_fail	alert[0x4]	6023	1			T17	24		T41	2438		T47	14
alert_integrity_fail	alert[0x5]	3042	1			T4	6		T17	665		T18	314
alert_integrity_fail	alert[0x6]	9709	1			T18	527		T39	3		T72	2
alert_integrity_fail	alert[0x7]	9049	1			T29	1		T18	38		T39	45
alert_integrity_fail	alert[0x8]	5545	1			T4	57		T17	18		T29	3
alert_integrity_fail	alert[0x9]	8061	1			T26	11		T41	407		T30	69
alert_integrity_fail	alert[0xa]	9215	1			T4	1266		T18	160		T32	71
alert_integrity_fail	alert[0xb]	3521	1			T4	218		T29	1		T18	91
alert_integrity_fail	alert[0xc]	2682	1			T18	96		T26	12		T41	73
alert_integrity_fail	alert[0xd]	11211	1			T4	9		T18	68		T41	150
alert_integrity_fail	alert[0xe]	7827	1			T18	11		T39	60		T41	31
alert_integrity_fail	alert[0xf]	8019	1			T4	358		T29	137		T18	6
alert_integrity_fail	alert[0x10]	4736	1			T19	18		T26	6		T41	31
alert_integrity_fail	alert[0x11]	7502	1			T4	56		T17	29		T29	1
alert_integrity_fail	alert[0x12]	3619	1			T6	8		T38	1		T39	71
alert_integrity_fail	alert[0x13]	3525	1			T17	17		T18	12		T39	410
alert_integrity_fail	alert[0x14]	4870	1			T4	6		T18	1279		T41	52
alert_integrity_fail	alert[0x15]	6328	1			T19	51		T64	3		T41	519
alert_integrity_fail	alert[0x16]	9097	1			T4	102		T17	755		T29	5
alert_integrity_fail	alert[0x17]	9792	1			T17	10		T29	19		T26	1
alert_integrity_fail	alert[0x18]	5739	1			T19	61		T39	30		T41	34
alert_integrity_fail	alert[0x19]	6210	1			T30	48		T72	2		T75	2
alert_integrity_fail	alert[0x1a]	2892	1			T18	15		T41	298		T284	16
alert_integrity_fail	alert[0x1b]	3147	1			T17	2		T18	171		T26	192
alert_integrity_fail	alert[0x1c]	8234	1			T6	5		T18	3		T41	61
alert_integrity_fail	alert[0x1d]	5913	1			T17	26		T29	1		T108	24
alert_integrity_fail	alert[0x1e]	7731	1			T19	23		T41	235		T72	154
alert_integrity_fail	alert[0x1f]	4474	1			T4	10		T17	97		T29	13
alert_integrity_fail	alert[0x20]	4061	1			T4	35		T19	65		T26	74
alert_integrity_fail	alert[0x21]	8707	1			T4	21		T108	8		T26	98
alert_integrity_fail	alert[0x22]	12896	1			T4	37		T29	13		T18	5
alert_integrity_fail	alert[0x23]	5715	1			T17	4		T41	310		T90	2199
alert_integrity_fail	alert[0x24]	9300	1			T29	3		T26	23		T41	40
alert_integrity_fail	alert[0x25]	9618	1			T4	477		T18	21		T38	9
alert_integrity_fail	alert[0x26]	6486	1			T4	1395		T17	7		T29	7
alert_integrity_fail	alert[0x27]	7534	1			T18	2		T39	162		T32	12
alert_integrity_fail	alert[0x28]	7261	1			T29	3		T18	15		T108	15
alert_integrity_fail	alert[0x29]	4911	1			T4	65		T17	21		T18	8
alert_integrity_fail	alert[0x2a]	5858	1			T18	398		T26	20		T30	7
alert_integrity_fail	alert[0x2b]	13797	1			T6	13		T18	371		T19	26
alert_integrity_fail	alert[0x2c]	11985	1			T4	94		T19	230		T41	2724
alert_integrity_fail	alert[0x2d]	5152	1			T4	28		T26	28		T90	12
alert_integrity_fail	alert[0x2e]	7538	1			T4	16		T29	16		T38	2
alert_integrity_fail	alert[0x2f]	18554	1			T17	360		T18	25		T19	3
alert_integrity_fail	alert[0x30]	4040	1			T29	1		T18	102		T26	11
alert_integrity_fail	alert[0x31]	5736	1			T26	150		T90	99		T32	419
alert_integrity_fail	alert[0x32]	7752	1			T17	98		T19	53		T26	8
alert_integrity_fail	alert[0x33]	5644	1			T4	16		T29	7		T30	64
alert_integrity_fail	alert[0x34]	13205	1			T4	18		T19	2		T70	7
alert_integrity_fail	alert[0x35]	8031	1			T4	425		T18	5		T70	18
alert_integrity_fail	alert[0x36]	12272	1			T17	100		T18	93		T19	432
alert_integrity_fail	alert[0x37]	5933	1			T4	30		T30	7		T90	14
alert_integrity_fail	alert[0x38]	4307	1			T17	108		T29	1		T108	2
alert_integrity_fail	alert[0x39]	15316	1			T4	5		T17	191		T18	12
alert_integrity_fail	alert[0x3a]	8038	1			T17	271		T18	68		T32	18
alert_integrity_fail	alert[0x3b]	3666	1			T30	10		T90	2		T32	401
alert_integrity_fail	alert[0x3c]	6132	1			T4	1		T17	596		T29	2
alert_integrity_fail	alert[0x3d]	4553	1			T17	94		T18	757		T38	1
alert_integrity_fail	alert[0x3e]	5710	1			T30	503		T32	269		T299	1
alert_integrity_fail	alert[0x3f]	5429	1			T18	35		T64	8		T41	83
alert_integrity_fail	alert[0x40]	6217	1			T18	580		T38	2		T26	3
alert_ping_fail	alert[0x0]	13	1			T269	1		T221	4		T109	1
alert_ping_fail	alert[0x1]	14	1			T107	1		T221	3		T109	2
alert_ping_fail	alert[0x2]	9	1			T12	1		T300	1		T221	1
alert_ping_fail	alert[0x3]	15	1			T9	1		T12	1		T300	1
alert_ping_fail	alert[0x4]	10	1			T11	2		T300	1		T109	1
alert_ping_fail	alert[0x5]	16	1			T191	1		T106	1		T107	1
alert_ping_fail	alert[0x6]	13	1			T9	1		T13	1		T270	1
alert_ping_fail	alert[0x7]	22	1			T13	2		T81	3		T92	1
alert_ping_fail	alert[0x8]	8	1			T301	1		T302	1		T109	1
alert_ping_fail	alert[0x9]	11	1			T9	1		T92	1		T303	2
alert_ping_fail	alert[0xa]	11	1			T9	1		T304	1		T305	1
alert_ping_fail	alert[0xb]	11	1			T92	1		T303	1		T221	1
alert_ping_fail	alert[0xc]	9	1			T9	2		T13	1		T306	1
alert_ping_fail	alert[0xd]	8	1			T9	1		T303	1		T307	1
alert_ping_fail	alert[0xe]	6	1			T306	1		T304	1		T308	1
alert_ping_fail	alert[0xf]	5	1			T298	1		T109	1		T309	1
alert_ping_fail	alert[0x10]	8	1			T9	1		T12	1		T310	1
alert_ping_fail	alert[0x11]	10	1			T9	1		T300	2		T301	1
alert_ping_fail	alert[0x12]	6	1			T107	1		T311	1		T302	1
alert_ping_fail	alert[0x13]	20	1			T12	1		T13	1		T312	1
alert_ping_fail	alert[0x14]	14	1			T12	1		T191	1		T301	1
alert_ping_fail	alert[0x15]	4	1			T308	1		T313	1		T314	1
alert_ping_fail	alert[0x16]	17	1			T10	1		T12	2		T13	1
alert_ping_fail	alert[0x17]	8	1			T302	1		T306	1		T305	1
alert_ping_fail	alert[0x18]	15	1			T107	1		T300	1		T221	1
alert_ping_fail	alert[0x19]	4	1			T92	1		T269	1		T306	1
alert_ping_fail	alert[0x1a]	13	1			T9	1		T12	1		T191	1
alert_ping_fail	alert[0x1b]	19	1			T12	1		T269	1		T301	1
alert_ping_fail	alert[0x1c]	9	1			T13	1		T303	1		T300	1
alert_ping_fail	alert[0x1d]	7	1			T315	1		T306	1		T316	1
alert_ping_fail	alert[0x1e]	11	1			T13	1		T191	1		T269	1
alert_ping_fail	alert[0x1f]	18	1			T12	1		T317	2		T315	1
alert_ping_fail	alert[0x20]	8	1			T13	1		T303	1		T301	1
alert_ping_fail	alert[0x21]	13	1			T9	1		T92	1		T82	1
alert_ping_fail	alert[0x22]	10	1			T269	1		T318	1		T221	1
alert_ping_fail	alert[0x23]	7	1			T9	1		T315	1		T302	1
alert_ping_fail	alert[0x24]	12	1			T12	1		T13	2		T269	1
alert_ping_fail	alert[0x25]	13	1			T107	1		T304	1		T305	1
alert_ping_fail	alert[0x26]	14	1			T9	1		T92	1		T303	1
alert_ping_fail	alert[0x27]	10	1			T9	1		T92	1		T107	1
alert_ping_fail	alert[0x28]	14	1			T312	1		T303	1		T319	1
alert_ping_fail	alert[0x29]	11	1			T13	1		T82	1		T318	1
alert_ping_fail	alert[0x2a]	7	1			T109	1		T320	1		T309	2
alert_ping_fail	alert[0x2b]	12	1			T191	1		T192	1		T92	1
alert_ping_fail	alert[0x2c]	15	1			T107	1		T300	1		T317	1
alert_ping_fail	alert[0x2d]	9	1			T92	1		T301	1		T306	1
alert_ping_fail	alert[0x2e]	9	1			T13	1		T191	1		T321	2
alert_ping_fail	alert[0x2f]	6	1			T9	1		T81	1		T315	1
alert_ping_fail	alert[0x30]	13	1			T9	1		T13	1		T92	1
alert_ping_fail	alert[0x31]	6	1			T303	1		T306	1		T182	1
alert_ping_fail	alert[0x32]	7	1			T220	1		T221	1		T306	1
alert_ping_fail	alert[0x33]	11	1			T12	1		T269	1		T300	1
alert_ping_fail	alert[0x34]	7	1			T300	1		T318	1		T315	1
alert_ping_fail	alert[0x35]	13	1			T298	1		T107	1		T82	1
alert_ping_fail	alert[0x36]	8	1			T302	1		T220	2		T320	1
alert_ping_fail	alert[0x37]	11	1			T9	1		T12	1		T191	1
alert_ping_fail	alert[0x38]	10	1			T92	1		T107	1		T305	2
alert_ping_fail	alert[0x39]	11	1			T92	1		T301	1		T182	2
alert_ping_fail	alert[0x3a]	9	1			T9	1		T269	1		T303	1
alert_ping_fail	alert[0x3b]	13	1			T191	1		T269	1		T82	1
alert_ping_fail	alert[0x3c]	2	1			T182	1		T322	1		-	-
alert_ping_fail	alert[0x3d]	9	1			T269	1		T300	1		T220	1
alert_ping_fail	alert[0x3e]	11	1			T191	1		T92	1		T300	1
alert_ping_fail	alert[0x3f]	1	1			T323	1		-	-		-	-
alert_ping_fail	alert[0x40]	4	1			T304	1		T320	1		T309	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	92752	1			T4	4997		T29	197		T38	13
alert_integrity_fail	class_i[0x1]	165995	1			T6	26		T29	30		T18	1288
alert_integrity_fail	class_i[0x2]	116492	1			T17	3478		T18	265		T19	1112
alert_integrity_fail	class_i[0x3]	101292	1			T17	22		T29	7		T18	4217
alert_ping_fail	class_i[0x0]	185	1			T13	1		T192	1		T92	11
alert_ping_fail	class_i[0x1]	138	1			T10	1		T12	13		T13	1
alert_ping_fail	class_i[0x2]	117	1			T9	17		T81	4		T298	1
alert_ping_fail	class_i[0x3]	240	1			T9	1		T11	2		T13	12