Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.68 99.99 98.76 100.00 100.00 100.00 99.38 99.60


Total test records in report: 834
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T170 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.876769697 Jul 23 04:48:35 PM PDT 24 Jul 23 04:48:41 PM PDT 24 36611976 ps
T158 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3422483177 Jul 23 04:48:30 PM PDT 24 Jul 23 04:49:48 PM PDT 24 3578274972 ps
T775 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1015559628 Jul 23 04:49:03 PM PDT 24 Jul 23 04:49:09 PM PDT 24 10130743 ps
T776 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3001587844 Jul 23 04:48:21 PM PDT 24 Jul 23 04:53:00 PM PDT 24 30506272794 ps
T138 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1291330134 Jul 23 04:48:29 PM PDT 24 Jul 23 05:05:19 PM PDT 24 27329038826 ps
T777 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.1879862819 Jul 23 04:49:05 PM PDT 24 Jul 23 04:49:11 PM PDT 24 6466325 ps
T164 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1792685933 Jul 23 04:48:44 PM PDT 24 Jul 23 04:50:06 PM PDT 24 2345048907 ps
T778 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.4075246074 Jul 23 04:49:03 PM PDT 24 Jul 23 04:49:18 PM PDT 24 438244119 ps
T779 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.866716737 Jul 23 04:48:15 PM PDT 24 Jul 23 04:48:23 PM PDT 24 34019282 ps
T780 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2048181616 Jul 23 04:48:37 PM PDT 24 Jul 23 04:48:49 PM PDT 24 61189938 ps
T781 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1151462463 Jul 23 04:48:47 PM PDT 24 Jul 23 04:48:56 PM PDT 24 672211374 ps
T782 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2387293866 Jul 23 04:48:20 PM PDT 24 Jul 23 04:48:33 PM PDT 24 124067864 ps
T783 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.751709196 Jul 23 04:48:55 PM PDT 24 Jul 23 04:48:59 PM PDT 24 10279388 ps
T784 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.6491867 Jul 23 04:49:02 PM PDT 24 Jul 23 04:49:07 PM PDT 24 14789985 ps
T785 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3164330686 Jul 23 04:48:19 PM PDT 24 Jul 23 04:48:33 PM PDT 24 137859473 ps
T786 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.4190779437 Jul 23 04:48:58 PM PDT 24 Jul 23 04:49:04 PM PDT 24 28049970 ps
T169 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3504058736 Jul 23 04:48:53 PM PDT 24 Jul 23 04:48:59 PM PDT 24 113363066 ps
T147 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1772623401 Jul 23 04:48:35 PM PDT 24 Jul 23 04:55:03 PM PDT 24 66303480942 ps
T787 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2377112103 Jul 23 04:48:19 PM PDT 24 Jul 23 04:48:45 PM PDT 24 313071046 ps
T788 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.137428250 Jul 23 04:48:46 PM PDT 24 Jul 23 04:49:09 PM PDT 24 323247743 ps
T789 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2826666418 Jul 23 04:49:02 PM PDT 24 Jul 23 04:49:07 PM PDT 24 8923121 ps
T790 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.427325109 Jul 23 04:48:37 PM PDT 24 Jul 23 04:48:50 PM PDT 24 179801801 ps
T146 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2188437414 Jul 23 04:48:29 PM PDT 24 Jul 23 04:50:55 PM PDT 24 7323517833 ps
T137 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3804113838 Jul 23 04:48:45 PM PDT 24 Jul 23 04:58:36 PM PDT 24 7709151651 ps
T161 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1018803241 Jul 23 04:48:55 PM PDT 24 Jul 23 04:49:35 PM PDT 24 1083016462 ps
T791 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.114182549 Jul 23 04:48:56 PM PDT 24 Jul 23 04:49:07 PM PDT 24 217995227 ps
T792 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.831465515 Jul 23 04:48:54 PM PDT 24 Jul 23 04:49:21 PM PDT 24 186662226 ps
T793 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3885826109 Jul 23 04:48:29 PM PDT 24 Jul 23 04:48:46 PM PDT 24 185954751 ps
T794 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1673327009 Jul 23 04:49:02 PM PDT 24 Jul 23 04:49:17 PM PDT 24 594012036 ps
T795 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2310565644 Jul 23 04:49:03 PM PDT 24 Jul 23 04:49:09 PM PDT 24 14544272 ps
T149 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.771223009 Jul 23 04:48:48 PM PDT 24 Jul 23 04:57:04 PM PDT 24 10972565728 ps
T796 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1164193090 Jul 23 04:49:04 PM PDT 24 Jul 23 04:49:12 PM PDT 24 29455938 ps
T797 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.79001214 Jul 23 04:48:20 PM PDT 24 Jul 23 04:48:33 PM PDT 24 253558060 ps
T798 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1434275524 Jul 23 04:48:36 PM PDT 24 Jul 23 04:48:48 PM PDT 24 499367914 ps
T799 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.811097914 Jul 23 04:49:10 PM PDT 24 Jul 23 04:49:18 PM PDT 24 17908594 ps
T168 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3824890275 Jul 23 04:48:48 PM PDT 24 Jul 23 04:48:53 PM PDT 24 46272351 ps
T800 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3723206371 Jul 23 04:48:26 PM PDT 24 Jul 23 04:48:52 PM PDT 24 1503870454 ps
T801 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2391900141 Jul 23 04:48:14 PM PDT 24 Jul 23 04:51:00 PM PDT 24 1174121238 ps
T165 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2700982777 Jul 23 04:48:57 PM PDT 24 Jul 23 04:49:04 PM PDT 24 52199130 ps
T802 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.784234359 Jul 23 04:49:01 PM PDT 24 Jul 23 04:49:12 PM PDT 24 221384808 ps
T355 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3174243167 Jul 23 04:48:28 PM PDT 24 Jul 23 05:09:48 PM PDT 24 69458724627 ps
T803 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3210230171 Jul 23 04:48:34 PM PDT 24 Jul 23 04:48:41 PM PDT 24 197068289 ps
T139 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.4197927395 Jul 23 04:48:26 PM PDT 24 Jul 23 04:55:51 PM PDT 24 5653189510 ps
T148 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2910962651 Jul 23 04:48:35 PM PDT 24 Jul 23 04:58:42 PM PDT 24 4541587399 ps
T804 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1526540476 Jul 23 04:48:26 PM PDT 24 Jul 23 04:48:35 PM PDT 24 97590974 ps
T160 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.105970724 Jul 23 04:48:27 PM PDT 24 Jul 23 04:48:34 PM PDT 24 103415042 ps
T805 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.125041936 Jul 23 04:48:35 PM PDT 24 Jul 23 04:48:45 PM PDT 24 94719019 ps
T806 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1362116898 Jul 23 04:48:48 PM PDT 24 Jul 23 04:49:40 PM PDT 24 1398072083 ps
T807 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.31340986 Jul 23 04:49:01 PM PDT 24 Jul 23 04:49:15 PM PDT 24 68123569 ps
T808 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1661630256 Jul 23 04:48:25 PM PDT 24 Jul 23 04:49:04 PM PDT 24 4067767917 ps
T140 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1746478339 Jul 23 04:48:19 PM PDT 24 Jul 23 04:49:56 PM PDT 24 806928327 ps
T809 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3546317634 Jul 23 04:48:19 PM PDT 24 Jul 23 04:52:32 PM PDT 24 66750247445 ps
T810 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.270821771 Jul 23 04:48:19 PM PDT 24 Jul 23 04:48:40 PM PDT 24 248908712 ps
T811 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2049971115 Jul 23 04:48:45 PM PDT 24 Jul 23 04:48:53 PM PDT 24 204806686 ps
T812 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.12441267 Jul 23 04:48:20 PM PDT 24 Jul 23 04:48:33 PM PDT 24 568267907 ps
T143 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3851339768 Jul 23 04:48:18 PM PDT 24 Jul 23 04:56:27 PM PDT 24 12155085748 ps
T813 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.507426467 Jul 23 04:48:19 PM PDT 24 Jul 23 04:48:23 PM PDT 24 7338570 ps
T814 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.4113899117 Jul 23 04:48:10 PM PDT 24 Jul 23 04:48:26 PM PDT 24 132818361 ps
T815 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3981716964 Jul 23 04:49:07 PM PDT 24 Jul 23 04:49:14 PM PDT 24 10875375 ps
T816 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1782998239 Jul 23 04:48:54 PM PDT 24 Jul 23 04:49:01 PM PDT 24 319737025 ps
T150 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2036223680 Jul 23 04:48:47 PM PDT 24 Jul 23 04:51:53 PM PDT 24 11973132950 ps
T817 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2960052092 Jul 23 04:48:20 PM PDT 24 Jul 23 04:48:30 PM PDT 24 252414097 ps
T818 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.691452009 Jul 23 04:48:29 PM PDT 24 Jul 23 04:48:38 PM PDT 24 82039083 ps
T354 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.4184857208 Jul 23 04:48:36 PM PDT 24 Jul 23 04:57:21 PM PDT 24 6690941656 ps
T166 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1830894413 Jul 23 04:48:11 PM PDT 24 Jul 23 04:48:22 PM PDT 24 126836298 ps
T819 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.311960993 Jul 23 04:48:17 PM PDT 24 Jul 23 04:48:25 PM PDT 24 98096868 ps
T820 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1613843079 Jul 23 04:48:52 PM PDT 24 Jul 23 04:49:33 PM PDT 24 2739709704 ps
T821 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3427105631 Jul 23 04:48:55 PM PDT 24 Jul 23 04:48:59 PM PDT 24 23958020 ps
T822 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1017256246 Jul 23 04:48:17 PM PDT 24 Jul 23 04:48:22 PM PDT 24 25903151 ps
T162 /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.17253802 Jul 23 04:48:17 PM PDT 24 Jul 23 04:49:26 PM PDT 24 917091786 ps
T142 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1171742090 Jul 23 04:48:53 PM PDT 24 Jul 23 04:54:49 PM PDT 24 4109288809 ps
T823 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3144947743 Jul 23 04:48:26 PM PDT 24 Jul 23 04:48:35 PM PDT 24 54661435 ps
T824 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1195727540 Jul 23 04:49:09 PM PDT 24 Jul 23 04:49:17 PM PDT 24 7636830 ps
T825 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1655557310 Jul 23 04:48:21 PM PDT 24 Jul 23 04:50:31 PM PDT 24 10473186593 ps
T826 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3475793686 Jul 23 04:48:36 PM PDT 24 Jul 23 04:50:17 PM PDT 24 3172481389 ps
T827 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3220097709 Jul 23 04:48:58 PM PDT 24 Jul 23 04:49:10 PM PDT 24 1779686784 ps
T828 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.53265660 Jul 23 04:48:50 PM PDT 24 Jul 23 04:48:54 PM PDT 24 15008997 ps
T829 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2177584510 Jul 23 04:48:30 PM PDT 24 Jul 23 04:48:34 PM PDT 24 22385702 ps
T830 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2073737759 Jul 23 04:48:19 PM PDT 24 Jul 23 04:48:30 PM PDT 24 72646274 ps
T831 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1725010881 Jul 23 04:48:19 PM PDT 24 Jul 23 04:48:29 PM PDT 24 357841231 ps
T144 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2455236633 Jul 23 04:49:02 PM PDT 24 Jul 23 04:52:28 PM PDT 24 15886783982 ps
T832 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2755889148 Jul 23 04:48:09 PM PDT 24 Jul 23 04:48:34 PM PDT 24 271444799 ps
T833 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1840037558 Jul 23 04:48:12 PM PDT 24 Jul 23 04:48:40 PM PDT 24 181531586 ps
T834 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.850077712 Jul 23 04:49:03 PM PDT 24 Jul 23 04:49:09 PM PDT 24 7623657 ps

Test location /workspace/coverage/default/35.alert_handler_entropy.3131785804
Short name T6
Test name
Test status
Simulation time 42201031235 ps
CPU time 2532.89 seconds
Started Jul 23 04:51:36 PM PDT 24
Finished Jul 23 05:33:54 PM PDT 24
Peak memory 288072 kb
Host smart-4d6fc632-5b40-481e-a4c4-c74bd8787480
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131785804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.3131785804
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.248188790
Short name T18
Test name
Test status
Simulation time 97370267788 ps
CPU time 4960.49 seconds
Started Jul 23 04:50:12 PM PDT 24
Finished Jul 23 06:13:00 PM PDT 24
Peak memory 402904 kb
Host smart-44953cfd-a1da-4a69-bd2d-f69183b60e21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248188790 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.248188790
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.2131706603
Short name T15
Test name
Test status
Simulation time 549541379 ps
CPU time 24.73 seconds
Started Jul 23 04:50:11 PM PDT 24
Finished Jul 23 04:50:42 PM PDT 24
Peak memory 271700 kb
Host smart-4d13da51-304f-4aa5-992d-58f4d9979f62
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2131706603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2131706603
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1310994704
Short name T172
Test name
Test status
Simulation time 29598379714 ps
CPU time 405.72 seconds
Started Jul 23 04:48:12 PM PDT 24
Finished Jul 23 04:55:04 PM PDT 24
Peak memory 237208 kb
Host smart-07cdc9e3-5875-4ee6-ab7d-39257ac881e9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1310994704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1310994704
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.182215325
Short name T80
Test name
Test status
Simulation time 6521395602 ps
CPU time 480.36 seconds
Started Jul 23 04:50:32 PM PDT 24
Finished Jul 23 04:58:49 PM PDT 24
Peak memory 256824 kb
Host smart-107de30b-e3de-45fa-996c-e62b442d58a1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=182215325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.182215325
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.949328064
Short name T17
Test name
Test status
Simulation time 55842817386 ps
CPU time 1740.94 seconds
Started Jul 23 04:49:56 PM PDT 24
Finished Jul 23 05:19:01 PM PDT 24
Peak memory 265992 kb
Host smart-88306c00-668d-4bc3-9d11-26a1fb733722
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949328064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.949328064
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.2351280199
Short name T118
Test name
Test status
Simulation time 6534362419 ps
CPU time 215.94 seconds
Started Jul 23 04:48:38 PM PDT 24
Finished Jul 23 04:52:17 PM PDT 24
Peak memory 265928 kb
Host smart-f423c5ba-99a2-4ef5-8071-025e24af0fbf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2351280199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.2351280199
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.3802022465
Short name T81
Test name
Test status
Simulation time 328925781058 ps
CPU time 3376.16 seconds
Started Jul 23 04:50:32 PM PDT 24
Finished Jul 23 05:47:06 PM PDT 24
Peak memory 289616 kb
Host smart-85b51f9b-8ce8-4e93-b454-9b6c83281226
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802022465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3802022465
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.546209043
Short name T19
Test name
Test status
Simulation time 103629817483 ps
CPU time 3588.25 seconds
Started Jul 23 04:51:06 PM PDT 24
Finished Jul 23 05:50:59 PM PDT 24
Peak memory 305580 kb
Host smart-ff254642-1eb5-4ceb-a8a4-23d54eb7484c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546209043 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.546209043
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.3753895986
Short name T22
Test name
Test status
Simulation time 857712867 ps
CPU time 56.01 seconds
Started Jul 23 04:52:07 PM PDT 24
Finished Jul 23 04:53:04 PM PDT 24
Peak memory 256276 kb
Host smart-bc7fa342-2772-4630-97aa-44594694410a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37538
95986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3753895986
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.695924419
Short name T115
Test name
Test status
Simulation time 31949443601 ps
CPU time 1090.79 seconds
Started Jul 23 04:48:12 PM PDT 24
Finished Jul 23 05:06:28 PM PDT 24
Peak memory 266060 kb
Host smart-30c6dda7-2265-45b4-85ef-dade7ed3a7da
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695924419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.695924419
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3914861722
Short name T32
Test name
Test status
Simulation time 219645696507 ps
CPU time 2642.1 seconds
Started Jul 23 04:50:10 PM PDT 24
Finished Jul 23 05:34:17 PM PDT 24
Peak memory 289556 kb
Host smart-b43ae916-0d24-4ff5-a4e1-c6ae9c57a8c6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914861722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3914861722
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2591394581
Short name T122
Test name
Test status
Simulation time 5733046336 ps
CPU time 207.69 seconds
Started Jul 23 04:48:10 PM PDT 24
Finished Jul 23 04:51:44 PM PDT 24
Peak memory 266044 kb
Host smart-57ba0da9-eab9-4968-a754-1528ce206eb7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2591394581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2591394581
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1453958256
Short name T109
Test name
Test status
Simulation time 24623108918 ps
CPU time 257.65 seconds
Started Jul 23 04:51:07 PM PDT 24
Finished Jul 23 04:55:30 PM PDT 24
Peak memory 248656 kb
Host smart-237e3ca4-30b8-485a-b99c-887967a38a0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453958256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1453958256
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.732014629
Short name T131
Test name
Test status
Simulation time 35476911570 ps
CPU time 668.88 seconds
Started Jul 23 04:48:12 PM PDT 24
Finished Jul 23 04:59:27 PM PDT 24
Peak memory 266092 kb
Host smart-66cee5cc-1a78-4118-b64c-5b232d59ee4a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732014629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.732014629
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.2839186370
Short name T312
Test name
Test status
Simulation time 187666241763 ps
CPU time 2556.01 seconds
Started Jul 23 04:50:46 PM PDT 24
Finished Jul 23 05:33:38 PM PDT 24
Peak memory 289544 kb
Host smart-7a54aced-3eb3-43b7-9d28-b2dc79a450e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839186370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2839186370
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3666952707
Short name T151
Test name
Test status
Simulation time 348095532 ps
CPU time 37.75 seconds
Started Jul 23 04:49:02 PM PDT 24
Finished Jul 23 04:49:43 PM PDT 24
Peak memory 241200 kb
Host smart-b5edbbac-15a0-4310-8987-43d346b7b52f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3666952707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.3666952707
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3337327724
Short name T351
Test name
Test status
Simulation time 19250097 ps
CPU time 1.41 seconds
Started Jul 23 04:49:04 PM PDT 24
Finished Jul 23 04:49:10 PM PDT 24
Peak memory 237200 kb
Host smart-8d904d9d-8917-43ab-9fa0-781cdadbc1b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3337327724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3337327724
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1623358222
Short name T9
Test name
Test status
Simulation time 26685207629 ps
CPU time 551.69 seconds
Started Jul 23 04:50:11 PM PDT 24
Finished Jul 23 04:59:30 PM PDT 24
Peak memory 248608 kb
Host smart-bd85a1b9-965e-4ed8-bea4-987d70dfe142
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623358222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1623358222
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3333396287
Short name T126
Test name
Test status
Simulation time 5686970828 ps
CPU time 343.59 seconds
Started Jul 23 04:48:52 PM PDT 24
Finished Jul 23 04:54:38 PM PDT 24
Peak memory 274236 kb
Host smart-12565986-b73d-41a1-88d5-2936c3a4c6f6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3333396287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3333396287
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.3819822171
Short name T44
Test name
Test status
Simulation time 115326076543 ps
CPU time 2218.93 seconds
Started Jul 23 04:51:29 PM PDT 24
Finished Jul 23 05:28:32 PM PDT 24
Peak memory 289088 kb
Host smart-fea32577-3768-4a35-82b5-7956ff5805e1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819822171 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.3819822171
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.3941179074
Short name T42
Test name
Test status
Simulation time 97767891965 ps
CPU time 2084.89 seconds
Started Jul 23 04:50:39 PM PDT 24
Finished Jul 23 05:25:40 PM PDT 24
Peak memory 297744 kb
Host smart-26095c3a-5f5a-45da-977c-c5af3c68ffc1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941179074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.3941179074
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.157286488
Short name T324
Test name
Test status
Simulation time 451913140214 ps
CPU time 2326.77 seconds
Started Jul 23 04:51:40 PM PDT 24
Finished Jul 23 05:30:31 PM PDT 24
Peak memory 288620 kb
Host smart-060e85d0-fcd6-42f3-99ea-95221ee18d36
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157286488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.157286488
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.3856761141
Short name T269
Test name
Test status
Simulation time 16119044166 ps
CPU time 308.43 seconds
Started Jul 23 04:52:13 PM PDT 24
Finished Jul 23 04:57:22 PM PDT 24
Peak memory 248604 kb
Host smart-d04a284f-355b-4175-8134-7af793658724
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856761141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3856761141
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3115261926
Short name T128
Test name
Test status
Simulation time 174280773863 ps
CPU time 1053.57 seconds
Started Jul 23 04:48:19 PM PDT 24
Finished Jul 23 05:05:57 PM PDT 24
Peak memory 265980 kb
Host smart-b5358298-aecf-405d-a1ab-589b7946bcf2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115261926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3115261926
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.3741903964
Short name T306
Test name
Test status
Simulation time 22593031271 ps
CPU time 478.31 seconds
Started Jul 23 04:52:15 PM PDT 24
Finished Jul 23 05:00:15 PM PDT 24
Peak memory 248472 kb
Host smart-95e1460e-8341-406d-86d9-1e8e1f54f50e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741903964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3741903964
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3318725267
Short name T102
Test name
Test status
Simulation time 57105242714 ps
CPU time 3260.41 seconds
Started Jul 23 04:50:39 PM PDT 24
Finished Jul 23 05:45:16 PM PDT 24
Peak memory 305868 kb
Host smart-344d3fbb-ee05-431b-970c-0d69a28547cb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318725267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3318725267
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.854607161
Short name T231
Test name
Test status
Simulation time 103445271681 ps
CPU time 2918.09 seconds
Started Jul 23 04:50:14 PM PDT 24
Finished Jul 23 05:39:01 PM PDT 24
Peak memory 289600 kb
Host smart-3c1b71f3-1fe0-4f7c-a0dc-96c115a04ccd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854607161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.854607161
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.3065977246
Short name T243
Test name
Test status
Simulation time 83897290990 ps
CPU time 4817.29 seconds
Started Jul 23 04:49:57 PM PDT 24
Finished Jul 23 06:10:19 PM PDT 24
Peak memory 297704 kb
Host smart-c2777695-b8f6-4a4c-83fb-b2bff0802f59
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065977246 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.3065977246
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.692927287
Short name T326
Test name
Test status
Simulation time 137460827212 ps
CPU time 2153.1 seconds
Started Jul 23 04:52:33 PM PDT 24
Finished Jul 23 05:28:32 PM PDT 24
Peak memory 285052 kb
Host smart-2a16f928-d13d-4e14-8ca9-6660f24f1824
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692927287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.692927287
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3458442671
Short name T129
Test name
Test status
Simulation time 19871196693 ps
CPU time 353.63 seconds
Started Jul 23 04:48:13 PM PDT 24
Finished Jul 23 04:54:12 PM PDT 24
Peak memory 266100 kb
Host smart-b3c2db7e-9bb1-445c-9f4a-3407ae7064ec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3458442671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3458442671
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.208267134
Short name T120
Test name
Test status
Simulation time 15434258721 ps
CPU time 1279.49 seconds
Started Jul 23 04:48:36 PM PDT 24
Finished Jul 23 05:09:59 PM PDT 24
Peak memory 273152 kb
Host smart-9b5f64c4-8706-4e99-874f-9e1a23aa65aa
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208267134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.208267134
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1550652128
Short name T596
Test name
Test status
Simulation time 80716483570 ps
CPU time 433.05 seconds
Started Jul 23 04:50:29 PM PDT 24
Finished Jul 23 04:57:56 PM PDT 24
Peak memory 248584 kb
Host smart-3855405a-e6b3-4cfc-8334-2d67790f0990
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550652128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1550652128
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3585194976
Short name T30
Test name
Test status
Simulation time 33875087068 ps
CPU time 2109.55 seconds
Started Jul 23 04:50:31 PM PDT 24
Finished Jul 23 05:25:58 PM PDT 24
Peak memory 305088 kb
Host smart-0bb3a74c-b133-467f-8383-f4631a5bb390
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585194976 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3585194976
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2036223680
Short name T150
Test name
Test status
Simulation time 11973132950 ps
CPU time 185.17 seconds
Started Jul 23 04:48:47 PM PDT 24
Finished Jul 23 04:51:53 PM PDT 24
Peak memory 266172 kb
Host smart-e4d2a4fc-188c-415c-a1ab-1108b8a65146
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2036223680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2036223680
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.4188050474
Short name T16
Test name
Test status
Simulation time 432673618 ps
CPU time 24.62 seconds
Started Jul 23 04:49:54 PM PDT 24
Finished Jul 23 04:50:21 PM PDT 24
Peak memory 271244 kb
Host smart-273d9c33-b96d-41ed-872c-5aec338e8f7d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4188050474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.4188050474
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1291330134
Short name T138
Test name
Test status
Simulation time 27329038826 ps
CPU time 1007.31 seconds
Started Jul 23 04:48:29 PM PDT 24
Finished Jul 23 05:05:19 PM PDT 24
Peak memory 266024 kb
Host smart-f06cb3b5-2092-4d7f-bb4d-22dd7d9bf366
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1291330134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.1291330134
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.3008320054
Short name T350
Test name
Test status
Simulation time 8533284 ps
CPU time 1.61 seconds
Started Jul 23 04:49:02 PM PDT 24
Finished Jul 23 04:49:08 PM PDT 24
Peak memory 238140 kb
Host smart-a86dcc73-832f-4e46-89c6-8a9275fd0ca4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3008320054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.3008320054
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.3192470894
Short name T93
Test name
Test status
Simulation time 38484808185 ps
CPU time 907.64 seconds
Started Jul 23 04:50:28 PM PDT 24
Finished Jul 23 05:05:51 PM PDT 24
Peak memory 273188 kb
Host smart-ce36f051-5431-492f-a62a-153c96acfedc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192470894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3192470894
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.2364046943
Short name T265
Test name
Test status
Simulation time 740030654690 ps
CPU time 6507.22 seconds
Started Jul 23 04:50:39 PM PDT 24
Finished Jul 23 06:39:23 PM PDT 24
Peak memory 336568 kb
Host smart-fbea09f7-e171-4ebe-b431-9b48a9784f79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364046943 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.2364046943
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1171742090
Short name T142
Test name
Test status
Simulation time 4109288809 ps
CPU time 354.07 seconds
Started Jul 23 04:48:53 PM PDT 24
Finished Jul 23 04:54:49 PM PDT 24
Peak memory 266068 kb
Host smart-9744c989-5b5e-4bd9-b859-df2c650b343c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171742090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1171742090
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.2577182239
Short name T39
Test name
Test status
Simulation time 27271952693 ps
CPU time 2665.68 seconds
Started Jul 23 04:51:59 PM PDT 24
Finished Jul 23 05:36:26 PM PDT 24
Peak memory 322152 kb
Host smart-cce21d53-a32b-4f93-8702-bb33747808d8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577182239 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.2577182239
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2721624812
Short name T309
Test name
Test status
Simulation time 15077657636 ps
CPU time 614.19 seconds
Started Jul 23 04:50:39 PM PDT 24
Finished Jul 23 05:01:10 PM PDT 24
Peak memory 247484 kb
Host smart-1783affd-3562-408e-946d-700257b03d85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721624812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2721624812
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.2798165698
Short name T279
Test name
Test status
Simulation time 843110444 ps
CPU time 25.94 seconds
Started Jul 23 04:50:48 PM PDT 24
Finished Jul 23 04:51:28 PM PDT 24
Peak memory 248460 kb
Host smart-1c83162d-af80-4cea-b701-e625736a38ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27981
65698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.2798165698
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.4051363872
Short name T256
Test name
Test status
Simulation time 44414234897 ps
CPU time 2740.43 seconds
Started Jul 23 04:50:40 PM PDT 24
Finished Jul 23 05:36:38 PM PDT 24
Peak memory 289652 kb
Host smart-f1b3de8c-dcc4-402f-b270-c03a753a1b12
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051363872 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.4051363872
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.2275691303
Short name T314
Test name
Test status
Simulation time 41845984688 ps
CPU time 1302.4 seconds
Started Jul 23 04:52:15 PM PDT 24
Finished Jul 23 05:13:59 PM PDT 24
Peak memory 272640 kb
Host smart-6c15f561-496a-4159-a15f-d2c2b39b4b5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275691303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2275691303
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2960856114
Short name T336
Test name
Test status
Simulation time 180254257879 ps
CPU time 1676.97 seconds
Started Jul 23 04:50:22 PM PDT 24
Finished Jul 23 05:18:32 PM PDT 24
Peak memory 272776 kb
Host smart-ec05a5dd-f1bc-4260-a531-41f642f45546
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960856114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2960856114
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2700982777
Short name T165
Test name
Test status
Simulation time 52199130 ps
CPU time 4.33 seconds
Started Jul 23 04:48:57 PM PDT 24
Finished Jul 23 04:49:04 PM PDT 24
Peak memory 238264 kb
Host smart-741f5fa4-1ca3-40ec-99bf-e165747c9e3c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2700982777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2700982777
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.660644200
Short name T99
Test name
Test status
Simulation time 18190313543 ps
CPU time 1982.44 seconds
Started Jul 23 04:50:38 PM PDT 24
Finished Jul 23 05:23:58 PM PDT 24
Peak memory 304812 kb
Host smart-3bd4d193-0794-4c7d-8f37-0dc3175caa68
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660644200 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.660644200
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.1330400862
Short name T198
Test name
Test status
Simulation time 24946581 ps
CPU time 2.54 seconds
Started Jul 23 04:49:55 PM PDT 24
Finished Jul 23 04:50:00 PM PDT 24
Peak memory 248892 kb
Host smart-a8f0ede3-78ed-43b9-8044-57e5a1a47481
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1330400862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.1330400862
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1324911849
Short name T212
Test name
Test status
Simulation time 43292840 ps
CPU time 3.61 seconds
Started Jul 23 04:49:58 PM PDT 24
Finished Jul 23 04:50:06 PM PDT 24
Peak memory 248836 kb
Host smart-6190916f-3c07-4168-a414-80381455589e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1324911849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1324911849
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2015655209
Short name T197
Test name
Test status
Simulation time 21057612 ps
CPU time 3.09 seconds
Started Jul 23 04:50:31 PM PDT 24
Finished Jul 23 04:50:51 PM PDT 24
Peak memory 248804 kb
Host smart-2eff4586-366d-4fbe-844d-22357d3aba4b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2015655209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2015655209
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.311002723
Short name T205
Test name
Test status
Simulation time 13709528 ps
CPU time 2.28 seconds
Started Jul 23 04:50:26 PM PDT 24
Finished Jul 23 04:50:42 PM PDT 24
Peak memory 248928 kb
Host smart-9a8af259-864e-41be-ad95-d22b3fa1e774
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=311002723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.311002723
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2910962651
Short name T148
Test name
Test status
Simulation time 4541587399 ps
CPU time 603.25 seconds
Started Jul 23 04:48:35 PM PDT 24
Finished Jul 23 04:58:42 PM PDT 24
Peak memory 265988 kb
Host smart-cfa6477f-b131-4061-a0f0-31d95a8bca63
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910962651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2910962651
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.585164926
Short name T636
Test name
Test status
Simulation time 148018437883 ps
CPU time 497.8 seconds
Started Jul 23 04:50:30 PM PDT 24
Finished Jul 23 04:59:05 PM PDT 24
Peak memory 255772 kb
Host smart-8fe8d89e-ba4e-445b-82f9-263f0e6c021b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585164926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.585164926
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2015378856
Short name T182
Test name
Test status
Simulation time 6836132587 ps
CPU time 239.24 seconds
Started Jul 23 04:50:58 PM PDT 24
Finished Jul 23 04:55:05 PM PDT 24
Peak memory 248628 kb
Host smart-5361aaab-36a1-4479-a44d-9d9acde186f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015378856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2015378856
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.904075377
Short name T288
Test name
Test status
Simulation time 263454857046 ps
CPU time 9612.56 seconds
Started Jul 23 04:51:23 PM PDT 24
Finished Jul 23 07:31:40 PM PDT 24
Peak memory 354592 kb
Host smart-9aae73c6-3635-4132-b98f-6715d550ede2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904075377 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.904075377
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2945990608
Short name T687
Test name
Test status
Simulation time 91189979676 ps
CPU time 2661.99 seconds
Started Jul 23 04:51:30 PM PDT 24
Finished Jul 23 05:35:58 PM PDT 24
Peak memory 289140 kb
Host smart-cfd91101-6b4e-4c3a-8d5b-032fedf12ea6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945990608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2945990608
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.969856566
Short name T272
Test name
Test status
Simulation time 167698869113 ps
CPU time 2728.85 seconds
Started Jul 23 04:51:46 PM PDT 24
Finished Jul 23 05:37:17 PM PDT 24
Peak memory 289500 kb
Host smart-c55dc61c-3cdc-436f-8dc2-988952c76e28
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969856566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.969856566
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.3832338303
Short name T277
Test name
Test status
Simulation time 123167200820 ps
CPU time 2622.09 seconds
Started Jul 23 04:51:51 PM PDT 24
Finished Jul 23 05:35:36 PM PDT 24
Peak memory 314644 kb
Host smart-df9f47d7-b4db-4b4a-98b4-4061ce25ca17
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832338303 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.3832338303
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.2873255558
Short name T280
Test name
Test status
Simulation time 154256584138 ps
CPU time 2693.95 seconds
Started Jul 23 04:50:24 PM PDT 24
Finished Jul 23 05:35:33 PM PDT 24
Peak memory 289604 kb
Host smart-080b30a3-fa57-4fd7-a304-f62b780037de
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873255558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.2873255558
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.771223009
Short name T149
Test name
Test status
Simulation time 10972565728 ps
CPU time 495.28 seconds
Started Jul 23 04:48:48 PM PDT 24
Finished Jul 23 04:57:04 PM PDT 24
Peak memory 266016 kb
Host smart-a6ac7334-0d1d-4007-9238-bf660fa6136f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771223009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.771223009
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3174243167
Short name T355
Test name
Test status
Simulation time 69458724627 ps
CPU time 1275.88 seconds
Started Jul 23 04:48:28 PM PDT 24
Finished Jul 23 05:09:48 PM PDT 24
Peak memory 266004 kb
Host smart-d7297a7e-3621-4dc1-b44f-1e5ad3dafa80
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174243167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3174243167
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.4145927137
Short name T740
Test name
Test status
Simulation time 26212108 ps
CPU time 1.26 seconds
Started Jul 23 04:48:36 PM PDT 24
Finished Jul 23 04:48:40 PM PDT 24
Peak memory 236144 kb
Host smart-fa3d2c23-d172-48cc-910f-43894b3af170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4145927137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.4145927137
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3885179816
Short name T267
Test name
Test status
Simulation time 22309119283 ps
CPU time 1430.77 seconds
Started Jul 23 04:50:29 PM PDT 24
Finished Jul 23 05:14:34 PM PDT 24
Peak memory 289316 kb
Host smart-12605ce8-83c0-446e-bf9a-c067eeecec0b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885179816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3885179816
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.936360162
Short name T100
Test name
Test status
Simulation time 3523315323 ps
CPU time 53.56 seconds
Started Jul 23 04:50:26 PM PDT 24
Finished Jul 23 04:51:34 PM PDT 24
Peak memory 256740 kb
Host smart-4c94827c-b5dc-4b9f-b862-261157652b7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93636
0162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.936360162
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3608310729
Short name T261
Test name
Test status
Simulation time 14437799687 ps
CPU time 1428.89 seconds
Started Jul 23 04:50:39 PM PDT 24
Finished Jul 23 05:14:44 PM PDT 24
Peak memory 287196 kb
Host smart-342213b8-07c1-4844-9641-a5f63b2e3810
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608310729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3608310729
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.1437145742
Short name T254
Test name
Test status
Simulation time 10830321434 ps
CPU time 828.27 seconds
Started Jul 23 04:50:32 PM PDT 24
Finished Jul 23 05:04:38 PM PDT 24
Peak memory 272564 kb
Host smart-a151fc28-5c13-4690-93f9-4b138eec189e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437145742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1437145742
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1942879584
Short name T328
Test name
Test status
Simulation time 232894494162 ps
CPU time 2465.62 seconds
Started Jul 23 04:50:35 PM PDT 24
Finished Jul 23 05:31:57 PM PDT 24
Peak memory 289592 kb
Host smart-f66fb5ba-1960-4a10-b8bd-882feff2a0c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942879584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1942879584
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.3585836641
Short name T537
Test name
Test status
Simulation time 49226080040 ps
CPU time 533.85 seconds
Started Jul 23 04:50:42 PM PDT 24
Finished Jul 23 04:59:53 PM PDT 24
Peak memory 248680 kb
Host smart-f4b04030-ab61-488d-8914-5f6137508bdc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585836641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.3585836641
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.439823306
Short name T323
Test name
Test status
Simulation time 11999436303 ps
CPU time 497.75 seconds
Started Jul 23 04:51:58 PM PDT 24
Finished Jul 23 05:00:17 PM PDT 24
Peak memory 248404 kb
Host smart-3601dca9-4f7b-48b7-9f53-1c926432f6d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439823306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.439823306
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3412883089
Short name T296
Test name
Test status
Simulation time 707231476 ps
CPU time 41.79 seconds
Started Jul 23 04:52:08 PM PDT 24
Finished Jul 23 04:52:51 PM PDT 24
Peak memory 249164 kb
Host smart-c52174f5-cd20-4324-b6fc-396b0c714945
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34128
83089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3412883089
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.3183722958
Short name T293
Test name
Test status
Simulation time 3934947937 ps
CPU time 65.28 seconds
Started Jul 23 04:52:15 PM PDT 24
Finished Jul 23 04:53:21 PM PDT 24
Peak memory 248400 kb
Host smart-5ff95404-5fe4-4e28-9cbb-ffc9be9cf1b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31837
22958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3183722958
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3179236161
Short name T112
Test name
Test status
Simulation time 71960423745 ps
CPU time 2215.24 seconds
Started Jul 23 04:50:39 PM PDT 24
Finished Jul 23 05:27:51 PM PDT 24
Peak memory 289368 kb
Host smart-f67dfe39-72f4-461c-834c-9d71299a1683
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179236161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3179236161
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.2455236633
Short name T144
Test name
Test status
Simulation time 15886783982 ps
CPU time 202.02 seconds
Started Jul 23 04:49:02 PM PDT 24
Finished Jul 23 04:52:28 PM PDT 24
Peak memory 269492 kb
Host smart-b7c2b068-b923-4ba8-9e29-6563c494d99a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2455236633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.2455236633
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1511121252
Short name T159
Test name
Test status
Simulation time 217428943 ps
CPU time 2.13 seconds
Started Jul 23 04:48:17 PM PDT 24
Finished Jul 23 04:48:23 PM PDT 24
Peak memory 239956 kb
Host smart-390db893-8967-4647-ad16-a66eb3be540c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1511121252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1511121252
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.105970724
Short name T160
Test name
Test status
Simulation time 103415042 ps
CPU time 2.98 seconds
Started Jul 23 04:48:27 PM PDT 24
Finished Jul 23 04:48:34 PM PDT 24
Peak memory 238276 kb
Host smart-25356e43-46e5-46c1-91a2-5af0b0ee4938
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=105970724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.105970724
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.1830894413
Short name T166
Test name
Test status
Simulation time 126836298 ps
CPU time 4.47 seconds
Started Jul 23 04:48:11 PM PDT 24
Finished Jul 23 04:48:22 PM PDT 24
Peak memory 238444 kb
Host smart-1383f666-56bd-4ea9-8806-0bc0fb3cda01
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1830894413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.1830894413
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1792685933
Short name T164
Test name
Test status
Simulation time 2345048907 ps
CPU time 81.19 seconds
Started Jul 23 04:48:44 PM PDT 24
Finished Jul 23 04:50:06 PM PDT 24
Peak memory 249244 kb
Host smart-0a0ef7e0-aa61-4391-863a-c3acbc0f04a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1792685933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.1792685933
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3824890275
Short name T168
Test name
Test status
Simulation time 46272351 ps
CPU time 3.17 seconds
Started Jul 23 04:48:48 PM PDT 24
Finished Jul 23 04:48:53 PM PDT 24
Peak memory 237080 kb
Host smart-79a41f25-ff88-4389-af85-10b7f524507b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3824890275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3824890275
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1018803241
Short name T161
Test name
Test status
Simulation time 1083016462 ps
CPU time 37.04 seconds
Started Jul 23 04:48:55 PM PDT 24
Finished Jul 23 04:49:35 PM PDT 24
Peak memory 240936 kb
Host smart-24aff255-8901-4263-923a-b2387c4caf37
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1018803241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1018803241
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.3504058736
Short name T169
Test name
Test status
Simulation time 113363066 ps
CPU time 3.32 seconds
Started Jul 23 04:48:53 PM PDT 24
Finished Jul 23 04:48:59 PM PDT 24
Peak memory 238076 kb
Host smart-630398b6-2ad9-4a26-a015-201263676005
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3504058736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.3504058736
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1248811864
Short name T157
Test name
Test status
Simulation time 345414835 ps
CPU time 42.87 seconds
Started Jul 23 04:48:38 PM PDT 24
Finished Jul 23 04:49:24 PM PDT 24
Peak memory 240948 kb
Host smart-4048f3d6-90a3-4fdc-819c-42fa9c05f1f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1248811864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1248811864
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.876769697
Short name T170
Test name
Test status
Simulation time 36611976 ps
CPU time 3.1 seconds
Started Jul 23 04:48:35 PM PDT 24
Finished Jul 23 04:48:41 PM PDT 24
Peak memory 238008 kb
Host smart-74e0ea38-e707-4415-8138-9b512b7c90fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=876769697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.876769697
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3355884811
Short name T145
Test name
Test status
Simulation time 1990161454 ps
CPU time 96.18 seconds
Started Jul 23 04:48:52 PM PDT 24
Finished Jul 23 04:50:31 PM PDT 24
Peak memory 265976 kb
Host smart-e1aad8a9-43a8-4e29-8b9d-0bf2d1ebcbeb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3355884811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3355884811
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.691130003
Short name T163
Test name
Test status
Simulation time 214268591 ps
CPU time 4.07 seconds
Started Jul 23 04:48:21 PM PDT 24
Finished Jul 23 04:48:29 PM PDT 24
Peak memory 237988 kb
Host smart-77755bb4-56b0-45e6-bba4-aae612d69f48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=691130003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.691130003
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3422483177
Short name T158
Test name
Test status
Simulation time 3578274972 ps
CPU time 75.48 seconds
Started Jul 23 04:48:30 PM PDT 24
Finished Jul 23 04:49:48 PM PDT 24
Peak memory 241084 kb
Host smart-4dc681b8-98ca-42f2-8b75-9a21a90fb880
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3422483177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3422483177
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.17253802
Short name T162
Test name
Test status
Simulation time 917091786 ps
CPU time 64.62 seconds
Started Jul 23 04:48:17 PM PDT 24
Finished Jul 23 04:49:26 PM PDT 24
Peak memory 238232 kb
Host smart-2c3c6aa8-25b7-450d-8125-43e5bae2fb66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=17253802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.17253802
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1012891830
Short name T153
Test name
Test status
Simulation time 47869892 ps
CPU time 3.44 seconds
Started Jul 23 04:48:17 PM PDT 24
Finished Jul 23 04:48:24 PM PDT 24
Peak memory 238416 kb
Host smart-43a0439f-bdb8-4a06-ab91-eee3bb0afffe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1012891830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1012891830
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.854080349
Short name T26
Test name
Test status
Simulation time 59702338793 ps
CPU time 5230.84 seconds
Started Jul 23 04:50:22 PM PDT 24
Finished Jul 23 06:17:47 PM PDT 24
Peak memory 371016 kb
Host smart-d3cd1359-1178-4c55-af4a-1cf9efb49f16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854080349 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.854080349
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1201914664
Short name T28
Test name
Test status
Simulation time 1432663164 ps
CPU time 21.84 seconds
Started Jul 23 04:50:52 PM PDT 24
Finished Jul 23 04:51:25 PM PDT 24
Peak memory 248564 kb
Host smart-ac2a4de2-8482-4b1d-b964-24365ab173c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12019
14664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1201914664
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.4151207214
Short name T25
Test name
Test status
Simulation time 3255201054 ps
CPU time 59.72 seconds
Started Jul 23 04:50:56 PM PDT 24
Finished Jul 23 04:52:05 PM PDT 24
Peak memory 247804 kb
Host smart-2b6670ed-6f5e-42e9-9f02-902562ff03af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41512
07214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.4151207214
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.778731173
Short name T27
Test name
Test status
Simulation time 8114448376 ps
CPU time 487.34 seconds
Started Jul 23 04:51:42 PM PDT 24
Finished Jul 23 04:59:52 PM PDT 24
Peak memory 264916 kb
Host smart-4a75afb4-8734-4a09-a8db-0984f9752776
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778731173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_han
dler_stress_all.778731173
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3003565283
Short name T183
Test name
Test status
Simulation time 15022872006 ps
CPU time 116.14 seconds
Started Jul 23 04:48:10 PM PDT 24
Finished Jul 23 04:50:12 PM PDT 24
Peak memory 241128 kb
Host smart-e09f5c9c-4238-4f34-802a-adcdb84084d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3003565283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3003565283
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3672814171
Short name T715
Test name
Test status
Simulation time 4470998787 ps
CPU time 286.12 seconds
Started Jul 23 04:48:10 PM PDT 24
Finished Jul 23 04:53:02 PM PDT 24
Peak memory 241056 kb
Host smart-7fcc88be-2b36-4ea2-85d1-435cdd43913d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3672814171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3672814171
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.530420318
Short name T772
Test name
Test status
Simulation time 121892239 ps
CPU time 10.09 seconds
Started Jul 23 04:48:09 PM PDT 24
Finished Jul 23 04:48:26 PM PDT 24
Peak memory 249108 kb
Host smart-836b5ebe-c1d2-465c-9690-4f4c042563ed
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=530420318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.530420318
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3084205660
Short name T356
Test name
Test status
Simulation time 310038022 ps
CPU time 6.43 seconds
Started Jul 23 04:48:10 PM PDT 24
Finished Jul 23 04:48:23 PM PDT 24
Peak memory 241136 kb
Host smart-be4a5807-fd53-4b06-af66-b27b53a1582d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084205660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.3084205660
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2446355608
Short name T770
Test name
Test status
Simulation time 205076880 ps
CPU time 8.39 seconds
Started Jul 23 04:48:10 PM PDT 24
Finished Jul 23 04:48:25 PM PDT 24
Peak memory 238036 kb
Host smart-7ad6382f-2ff9-4625-92d6-6b6c5355d01f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2446355608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2446355608
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3923192674
Short name T753
Test name
Test status
Simulation time 26914201 ps
CPU time 1.31 seconds
Started Jul 23 04:48:09 PM PDT 24
Finished Jul 23 04:48:17 PM PDT 24
Peak memory 237196 kb
Host smart-e369094c-35cf-431d-8bfc-4f3c4d3840db
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3923192674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3923192674
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.620893769
Short name T771
Test name
Test status
Simulation time 316952914 ps
CPU time 21.49 seconds
Started Jul 23 04:48:09 PM PDT 24
Finished Jul 23 04:48:37 PM PDT 24
Peak memory 241024 kb
Host smart-252aab43-f04a-4a34-8a2a-9be1163abc79
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=620893769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.620893769
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2755889148
Short name T832
Test name
Test status
Simulation time 271444799 ps
CPU time 18.25 seconds
Started Jul 23 04:48:09 PM PDT 24
Finished Jul 23 04:48:34 PM PDT 24
Peak memory 255712 kb
Host smart-bc925889-3880-48ad-8273-045e0d53ba88
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2755889148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2755889148
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2391900141
Short name T801
Test name
Test status
Simulation time 1174121238 ps
CPU time 161.35 seconds
Started Jul 23 04:48:14 PM PDT 24
Finished Jul 23 04:51:00 PM PDT 24
Peak memory 240944 kb
Host smart-a6dac2a3-9b0f-4be3-b523-0985a2ebf592
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2391900141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2391900141
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.4113899117
Short name T814
Test name
Test status
Simulation time 132818361 ps
CPU time 9.9 seconds
Started Jul 23 04:48:10 PM PDT 24
Finished Jul 23 04:48:26 PM PDT 24
Peak memory 249728 kb
Host smart-8ecad2a4-afad-4b4d-9a92-26493ba8f4af
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4113899117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.4113899117
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1716637149
Short name T357
Test name
Test status
Simulation time 341114711 ps
CPU time 7.94 seconds
Started Jul 23 04:48:12 PM PDT 24
Finished Jul 23 04:48:26 PM PDT 24
Peak memory 257504 kb
Host smart-d4ad3cad-92b4-43d9-96da-8f51e9f6a82c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716637149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1716637149
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.866716737
Short name T779
Test name
Test status
Simulation time 34019282 ps
CPU time 3.69 seconds
Started Jul 23 04:48:15 PM PDT 24
Finished Jul 23 04:48:23 PM PDT 24
Peak memory 238048 kb
Host smart-b7f4fc39-cd44-46f5-ab70-afc46d0a9f2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=866716737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.866716737
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2920695662
Short name T727
Test name
Test status
Simulation time 13103783 ps
CPU time 1.37 seconds
Started Jul 23 04:48:16 PM PDT 24
Finished Jul 23 04:48:21 PM PDT 24
Peak memory 238076 kb
Host smart-a5a47906-5933-48ca-b48e-b0d941f88609
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2920695662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2920695662
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3671350455
Short name T724
Test name
Test status
Simulation time 323279822 ps
CPU time 12.92 seconds
Started Jul 23 04:48:16 PM PDT 24
Finished Jul 23 04:48:33 PM PDT 24
Peak memory 246216 kb
Host smart-0442ae2f-49c2-4353-bd1c-eade00a39427
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3671350455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3671350455
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.3416733925
Short name T728
Test name
Test status
Simulation time 110805337 ps
CPU time 7.52 seconds
Started Jul 23 04:48:11 PM PDT 24
Finished Jul 23 04:48:24 PM PDT 24
Peak memory 249188 kb
Host smart-0d30bcad-be9d-4439-8868-a25b506eab2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3416733925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.3416733925
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1840037558
Short name T833
Test name
Test status
Simulation time 181531586 ps
CPU time 21.56 seconds
Started Jul 23 04:48:12 PM PDT 24
Finished Jul 23 04:48:40 PM PDT 24
Peak memory 240952 kb
Host smart-719cf415-285b-4caf-a7b7-73491c8f023a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1840037558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1840037558
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.427325109
Short name T790
Test name
Test status
Simulation time 179801801 ps
CPU time 10.19 seconds
Started Jul 23 04:48:37 PM PDT 24
Finished Jul 23 04:48:50 PM PDT 24
Peak memory 240836 kb
Host smart-d92d7a50-846a-4257-b26f-2820dc6375e9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427325109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.427325109
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1871062336
Short name T729
Test name
Test status
Simulation time 156815565 ps
CPU time 3.22 seconds
Started Jul 23 04:48:36 PM PDT 24
Finished Jul 23 04:48:42 PM PDT 24
Peak memory 237880 kb
Host smart-2f086684-1a69-43a3-b676-4c856e47a886
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1871062336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1871062336
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.3909556907
Short name T751
Test name
Test status
Simulation time 3981349633 ps
CPU time 26.1 seconds
Started Jul 23 04:48:36 PM PDT 24
Finished Jul 23 04:49:05 PM PDT 24
Peak memory 246332 kb
Host smart-67694f67-f4fc-4893-aea9-75d89c4d2186
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3909556907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.3909556907
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1772623401
Short name T147
Test name
Test status
Simulation time 66303480942 ps
CPU time 386.05 seconds
Started Jul 23 04:48:35 PM PDT 24
Finished Jul 23 04:55:03 PM PDT 24
Peak memory 266128 kb
Host smart-ae6ddeeb-09b9-4eda-866a-ff5d2d713aaa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1772623401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1772623401
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.4184857208
Short name T354
Test name
Test status
Simulation time 6690941656 ps
CPU time 521.89 seconds
Started Jul 23 04:48:36 PM PDT 24
Finished Jul 23 04:57:21 PM PDT 24
Peak memory 266096 kb
Host smart-2baece57-5b60-4687-920e-a0d175a8ed95
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184857208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.4184857208
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2834406207
Short name T713
Test name
Test status
Simulation time 120410268 ps
CPU time 5.03 seconds
Started Jul 23 04:48:36 PM PDT 24
Finished Jul 23 04:48:45 PM PDT 24
Peak memory 253068 kb
Host smart-d9eddd78-399b-4f3a-bae0-de06cdae1072
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2834406207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2834406207
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.462380688
Short name T749
Test name
Test status
Simulation time 28769263 ps
CPU time 4.36 seconds
Started Jul 23 04:48:36 PM PDT 24
Finished Jul 23 04:48:44 PM PDT 24
Peak memory 249200 kb
Host smart-f1660401-73e8-4a56-85f0-e08abc420ebd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=462380688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.alert_handler_csr_mem_rw_with_rand_reset.462380688
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3210230171
Short name T803
Test name
Test status
Simulation time 197068289 ps
CPU time 4.54 seconds
Started Jul 23 04:48:34 PM PDT 24
Finished Jul 23 04:48:41 PM PDT 24
Peak memory 237900 kb
Host smart-28a4c526-c618-4389-b3f6-4d7249be209b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3210230171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.3210230171
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2627533683
Short name T752
Test name
Test status
Simulation time 10964447 ps
CPU time 1.25 seconds
Started Jul 23 04:48:33 PM PDT 24
Finished Jul 23 04:48:37 PM PDT 24
Peak memory 236088 kb
Host smart-deaf1557-74f4-4966-b873-add6d462e307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2627533683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2627533683
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2727790148
Short name T744
Test name
Test status
Simulation time 1059930335 ps
CPU time 20.77 seconds
Started Jul 23 04:48:34 PM PDT 24
Finished Jul 23 04:48:57 PM PDT 24
Peak memory 240980 kb
Host smart-cb68abee-a70f-4afb-a63a-c3bf2fdc9a44
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2727790148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2727790148
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3475793686
Short name T826
Test name
Test status
Simulation time 3172481389 ps
CPU time 98.88 seconds
Started Jul 23 04:48:36 PM PDT 24
Finished Jul 23 04:50:17 PM PDT 24
Peak memory 266048 kb
Host smart-bbb05f06-9a73-484b-9c31-96def381e72c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3475793686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3475793686
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2986164818
Short name T141
Test name
Test status
Simulation time 24176824198 ps
CPU time 553.8 seconds
Started Jul 23 04:48:34 PM PDT 24
Finished Jul 23 04:57:50 PM PDT 24
Peak memory 266068 kb
Host smart-6fbfe1a2-94bc-4ecd-857f-037289ba2ff2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986164818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2986164818
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.592477013
Short name T739
Test name
Test status
Simulation time 201284004 ps
CPU time 5.04 seconds
Started Jul 23 04:48:35 PM PDT 24
Finished Jul 23 04:48:43 PM PDT 24
Peak memory 252076 kb
Host smart-19f22631-e24d-41eb-8495-727a4ef5a6ef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=592477013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.592477013
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3730124386
Short name T171
Test name
Test status
Simulation time 259156900 ps
CPU time 5.52 seconds
Started Jul 23 04:48:46 PM PDT 24
Finished Jul 23 04:48:53 PM PDT 24
Peak memory 240332 kb
Host smart-55752cf2-bdd6-4dc7-9a59-7613c5a19789
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730124386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3730124386
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1820678073
Short name T745
Test name
Test status
Simulation time 145783007 ps
CPU time 4.55 seconds
Started Jul 23 04:48:48 PM PDT 24
Finished Jul 23 04:48:55 PM PDT 24
Peak memory 237120 kb
Host smart-d8fc2156-1ab4-4231-8be1-2b1eba9bf04b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1820678073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1820678073
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.53265660
Short name T828
Test name
Test status
Simulation time 15008997 ps
CPU time 1.44 seconds
Started Jul 23 04:48:50 PM PDT 24
Finished Jul 23 04:48:54 PM PDT 24
Peak memory 238084 kb
Host smart-5c8d4442-30fc-46e1-a755-a1ba21913424
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=53265660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.53265660
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.137428250
Short name T788
Test name
Test status
Simulation time 323247743 ps
CPU time 21.84 seconds
Started Jul 23 04:48:46 PM PDT 24
Finished Jul 23 04:49:09 PM PDT 24
Peak memory 245328 kb
Host smart-1a73bc25-8265-4396-8afb-68e4be87f3be
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=137428250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.137428250
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.731487277
Short name T134
Test name
Test status
Simulation time 25241828352 ps
CPU time 131.1 seconds
Started Jul 23 04:48:36 PM PDT 24
Finished Jul 23 04:50:50 PM PDT 24
Peak memory 266096 kb
Host smart-0f6347d5-3b15-48ad-ae41-23fbf764c38f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=731487277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.731487277
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1434275524
Short name T798
Test name
Test status
Simulation time 499367914 ps
CPU time 9.6 seconds
Started Jul 23 04:48:36 PM PDT 24
Finished Jul 23 04:48:48 PM PDT 24
Peak memory 254520 kb
Host smart-144483c0-1191-4b32-a90a-7e80ae2106e7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1434275524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1434275524
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1812319913
Short name T738
Test name
Test status
Simulation time 1019312034 ps
CPU time 34.54 seconds
Started Jul 23 04:48:36 PM PDT 24
Finished Jul 23 04:49:14 PM PDT 24
Peak memory 249212 kb
Host smart-b02e3ffd-9d6f-457e-bc30-8d3614bce827
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1812319913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1812319913
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.2049971115
Short name T811
Test name
Test status
Simulation time 204806686 ps
CPU time 6.29 seconds
Started Jul 23 04:48:45 PM PDT 24
Finished Jul 23 04:48:53 PM PDT 24
Peak memory 240588 kb
Host smart-f007c726-2d31-44d3-9d5e-3c2d3c1d4d69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049971115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.2049971115
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3263579826
Short name T719
Test name
Test status
Simulation time 19674826 ps
CPU time 2.97 seconds
Started Jul 23 04:48:50 PM PDT 24
Finished Jul 23 04:48:55 PM PDT 24
Peak memory 237084 kb
Host smart-c0d12110-d3c6-4f65-9703-034e8c411a71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3263579826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3263579826
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.610726966
Short name T352
Test name
Test status
Simulation time 16887222 ps
CPU time 1.37 seconds
Started Jul 23 04:48:51 PM PDT 24
Finished Jul 23 04:48:54 PM PDT 24
Peak memory 237148 kb
Host smart-3cb59c85-377d-4aa4-b8fd-b57860d716c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=610726966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.610726966
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1362116898
Short name T806
Test name
Test status
Simulation time 1398072083 ps
CPU time 49.56 seconds
Started Jul 23 04:48:48 PM PDT 24
Finished Jul 23 04:49:40 PM PDT 24
Peak memory 246220 kb
Host smart-5462f516-43f4-4e4d-9933-91f495d025a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1362116898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1362116898
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2804819100
Short name T249
Test name
Test status
Simulation time 1183981235 ps
CPU time 18.46 seconds
Started Jul 23 04:48:51 PM PDT 24
Finished Jul 23 04:49:11 PM PDT 24
Peak memory 255064 kb
Host smart-30b5af2d-492d-4464-a5cd-dc15bb8bb953
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2804819100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2804819100
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.3652406313
Short name T358
Test name
Test status
Simulation time 208439079 ps
CPU time 4.86 seconds
Started Jul 23 04:48:46 PM PDT 24
Finished Jul 23 04:48:52 PM PDT 24
Peak memory 240540 kb
Host smart-e2c68387-8382-410f-82e5-e409746dcf22
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652406313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.3652406313
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1151462463
Short name T781
Test name
Test status
Simulation time 672211374 ps
CPU time 8.17 seconds
Started Jul 23 04:48:47 PM PDT 24
Finished Jul 23 04:48:56 PM PDT 24
Peak memory 240928 kb
Host smart-d2558ff4-e788-429d-8d27-8180c23ea38f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1151462463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1151462463
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.3572169453
Short name T747
Test name
Test status
Simulation time 12622476 ps
CPU time 1.68 seconds
Started Jul 23 04:48:46 PM PDT 24
Finished Jul 23 04:48:49 PM PDT 24
Peak memory 236132 kb
Host smart-4edf34e1-b66d-4642-8773-b629c143a7b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3572169453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.3572169453
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.4250829146
Short name T188
Test name
Test status
Simulation time 88437232 ps
CPU time 10.86 seconds
Started Jul 23 04:48:50 PM PDT 24
Finished Jul 23 04:49:03 PM PDT 24
Peak memory 245248 kb
Host smart-d5079d28-acb6-4d3e-bd33-ae33c7d22352
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4250829146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.4250829146
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.45477201
Short name T114
Test name
Test status
Simulation time 7106168348 ps
CPU time 219.38 seconds
Started Jul 23 04:48:47 PM PDT 24
Finished Jul 23 04:52:28 PM PDT 24
Peak memory 266052 kb
Host smart-576a4ff4-9bf7-4ad4-8a97-2d1f5e396c1a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=45477201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_error
s.45477201
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3804113838
Short name T137
Test name
Test status
Simulation time 7709151651 ps
CPU time 588.99 seconds
Started Jul 23 04:48:45 PM PDT 24
Finished Jul 23 04:58:36 PM PDT 24
Peak memory 268792 kb
Host smart-be6d5cb8-81be-4045-8f9b-1264cf93ef1f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804113838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3804113838
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.981728216
Short name T716
Test name
Test status
Simulation time 250983944 ps
CPU time 9.92 seconds
Started Jul 23 04:48:47 PM PDT 24
Finished Jul 23 04:48:58 PM PDT 24
Peak memory 254152 kb
Host smart-d21fd1b0-4cd3-44d3-95f0-4d32c287657c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=981728216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.981728216
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.1782998239
Short name T816
Test name
Test status
Simulation time 319737025 ps
CPU time 5.4 seconds
Started Jul 23 04:48:54 PM PDT 24
Finished Jul 23 04:49:01 PM PDT 24
Peak memory 239024 kb
Host smart-e6bbc56d-97cb-4ff3-b950-41ddc4b20f4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782998239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.1782998239
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.158083934
Short name T723
Test name
Test status
Simulation time 19877137 ps
CPU time 3.28 seconds
Started Jul 23 04:48:53 PM PDT 24
Finished Jul 23 04:48:59 PM PDT 24
Peak memory 241012 kb
Host smart-873da945-fd0f-437f-a187-ed4526b94df5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=158083934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.158083934
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.1056833634
Short name T349
Test name
Test status
Simulation time 9501735 ps
CPU time 1.52 seconds
Started Jul 23 04:48:55 PM PDT 24
Finished Jul 23 04:48:59 PM PDT 24
Peak memory 237172 kb
Host smart-82ab6f9d-d2aa-49dc-9adb-55c1f2e62ae2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1056833634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.1056833634
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1613843079
Short name T820
Test name
Test status
Simulation time 2739709704 ps
CPU time 38.78 seconds
Started Jul 23 04:48:52 PM PDT 24
Finished Jul 23 04:49:33 PM PDT 24
Peak memory 246368 kb
Host smart-fd421a1c-0319-4766-b053-2f22668d22bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1613843079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1613843079
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2083910670
Short name T117
Test name
Test status
Simulation time 10683452277 ps
CPU time 519.37 seconds
Started Jul 23 04:48:48 PM PDT 24
Finished Jul 23 04:57:29 PM PDT 24
Peak memory 266020 kb
Host smart-5b0ee90d-35fd-48fb-b549-aa4b5ad7c544
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083910670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.2083910670
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3664044723
Short name T755
Test name
Test status
Simulation time 1252264157 ps
CPU time 22.69 seconds
Started Jul 23 04:48:53 PM PDT 24
Finished Jul 23 04:49:17 PM PDT 24
Peak memory 256224 kb
Host smart-850e1c3a-e868-454b-94e0-71c09de3cdd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3664044723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3664044723
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.914011445
Short name T174
Test name
Test status
Simulation time 959063424 ps
CPU time 11.6 seconds
Started Jul 23 04:48:54 PM PDT 24
Finished Jul 23 04:49:08 PM PDT 24
Peak memory 244160 kb
Host smart-14f3c74e-327a-4b16-8776-8942bd42ce36
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914011445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.914011445
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.4190779437
Short name T786
Test name
Test status
Simulation time 28049970 ps
CPU time 3.89 seconds
Started Jul 23 04:48:58 PM PDT 24
Finished Jul 23 04:49:04 PM PDT 24
Peak memory 238260 kb
Host smart-8296d8dc-16dd-479f-9424-8eab6373f00a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4190779437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.4190779437
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.3427105631
Short name T821
Test name
Test status
Simulation time 23958020 ps
CPU time 1.25 seconds
Started Jul 23 04:48:55 PM PDT 24
Finished Jul 23 04:48:59 PM PDT 24
Peak memory 238144 kb
Host smart-d255a9a2-a0ed-4629-adc8-a6eb4c55b895
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3427105631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.3427105631
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.376935640
Short name T767
Test name
Test status
Simulation time 164872954 ps
CPU time 10.28 seconds
Started Jul 23 04:48:53 PM PDT 24
Finished Jul 23 04:49:05 PM PDT 24
Peak memory 245256 kb
Host smart-b3c72b4c-fbb7-450a-a8ad-58f7ff70ce95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=376935640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out
standing.376935640
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2043680962
Short name T119
Test name
Test status
Simulation time 12087224901 ps
CPU time 310.83 seconds
Started Jul 23 04:48:54 PM PDT 24
Finished Jul 23 04:54:07 PM PDT 24
Peak memory 271696 kb
Host smart-b3026b76-79d1-4ee2-bc3d-b60f150fb6ca
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043680962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2043680962
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.2417673464
Short name T756
Test name
Test status
Simulation time 380668441 ps
CPU time 5.8 seconds
Started Jul 23 04:48:53 PM PDT 24
Finished Jul 23 04:49:01 PM PDT 24
Peak memory 247884 kb
Host smart-11d4c510-d198-402b-be9e-80e832cd7790
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2417673464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2417673464
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.114182549
Short name T791
Test name
Test status
Simulation time 217995227 ps
CPU time 8.57 seconds
Started Jul 23 04:48:56 PM PDT 24
Finished Jul 23 04:49:07 PM PDT 24
Peak memory 256688 kb
Host smart-2a0a87da-4dfe-4ce2-8300-60a68d41e270
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114182549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_csr_mem_rw_with_rand_reset.114182549
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1859969593
Short name T735
Test name
Test status
Simulation time 33635011 ps
CPU time 3.49 seconds
Started Jul 23 04:48:53 PM PDT 24
Finished Jul 23 04:48:58 PM PDT 24
Peak memory 238032 kb
Host smart-2b6159c8-0ca3-45cf-87e4-4426a30ebd7c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1859969593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1859969593
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.751709196
Short name T783
Test name
Test status
Simulation time 10279388 ps
CPU time 1.58 seconds
Started Jul 23 04:48:55 PM PDT 24
Finished Jul 23 04:48:59 PM PDT 24
Peak memory 238100 kb
Host smart-e41c3db4-2173-4c02-b4d8-2faf25e9ae8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=751709196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.751709196
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.831465515
Short name T792
Test name
Test status
Simulation time 186662226 ps
CPU time 25.18 seconds
Started Jul 23 04:48:54 PM PDT 24
Finished Jul 23 04:49:21 PM PDT 24
Peak memory 246252 kb
Host smart-913425a9-af54-41c1-932b-f962209d913d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=831465515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out
standing.831465515
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.4135150413
Short name T123
Test name
Test status
Simulation time 48192229655 ps
CPU time 370.22 seconds
Started Jul 23 04:48:55 PM PDT 24
Finished Jul 23 04:55:07 PM PDT 24
Peak memory 266104 kb
Host smart-39ec38e2-3981-4c1b-9dcd-6d20bad8d126
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4135150413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.4135150413
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.223845
Short name T121
Test name
Test status
Simulation time 95711996438 ps
CPU time 530.98 seconds
Started Jul 23 04:48:53 PM PDT 24
Finished Jul 23 04:57:46 PM PDT 24
Peak memory 266148 kb
Host smart-2e7e9eea-9d5e-48ff-af54-f3886ad9e18c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 17.alert_handler_shadow_reg_errors_with_csr_rw.223845
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3220097709
Short name T827
Test name
Test status
Simulation time 1779686784 ps
CPU time 10.13 seconds
Started Jul 23 04:48:58 PM PDT 24
Finished Jul 23 04:49:10 PM PDT 24
Peak memory 255016 kb
Host smart-757abdb3-e2a5-4c92-82f7-2f17a0917edd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3220097709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3220097709
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.784234359
Short name T802
Test name
Test status
Simulation time 221384808 ps
CPU time 7.96 seconds
Started Jul 23 04:49:01 PM PDT 24
Finished Jul 23 04:49:12 PM PDT 24
Peak memory 244984 kb
Host smart-96c10716-8a93-4bf9-84a8-14e14d7ba8e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784234359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 18.alert_handler_csr_mem_rw_with_rand_reset.784234359
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1164193090
Short name T796
Test name
Test status
Simulation time 29455938 ps
CPU time 3.35 seconds
Started Jul 23 04:49:04 PM PDT 24
Finished Jul 23 04:49:12 PM PDT 24
Peak memory 237084 kb
Host smart-3ba46eee-ab01-4a80-a7d3-96b8696aa34b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1164193090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1164193090
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2613102894
Short name T726
Test name
Test status
Simulation time 13283676 ps
CPU time 1.49 seconds
Started Jul 23 04:49:07 PM PDT 24
Finished Jul 23 04:49:14 PM PDT 24
Peak memory 238144 kb
Host smart-9e150241-3169-4cb3-9d04-03e8ac6453f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2613102894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2613102894
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1673327009
Short name T794
Test name
Test status
Simulation time 594012036 ps
CPU time 10.86 seconds
Started Jul 23 04:49:02 PM PDT 24
Finished Jul 23 04:49:17 PM PDT 24
Peak memory 249160 kb
Host smart-7e7502ed-7530-4b15-8c7b-e5f218059e22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1673327009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1673327009
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.4075246074
Short name T778
Test name
Test status
Simulation time 438244119 ps
CPU time 10.25 seconds
Started Jul 23 04:49:03 PM PDT 24
Finished Jul 23 04:49:18 PM PDT 24
Peak memory 255232 kb
Host smart-6fda7e29-21a6-4910-bc59-1e56a3018f14
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4075246074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.4075246074
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.31340986
Short name T807
Test name
Test status
Simulation time 68123569 ps
CPU time 10.66 seconds
Started Jul 23 04:49:01 PM PDT 24
Finished Jul 23 04:49:15 PM PDT 24
Peak memory 257412 kb
Host smart-fc0095c1-6f8b-442f-ac82-b6b3a8f671a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31340986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 19.alert_handler_csr_mem_rw_with_rand_reset.31340986
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2684611828
Short name T732
Test name
Test status
Simulation time 99182732 ps
CPU time 3.07 seconds
Started Jul 23 04:49:03 PM PDT 24
Finished Jul 23 04:49:10 PM PDT 24
Peak memory 238000 kb
Host smart-936ec1a5-f3a3-46d3-b524-1c0041f15126
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2684611828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2684611828
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3853688552
Short name T743
Test name
Test status
Simulation time 10652317 ps
CPU time 1.36 seconds
Started Jul 23 04:49:04 PM PDT 24
Finished Jul 23 04:49:11 PM PDT 24
Peak memory 238144 kb
Host smart-6e31a79d-9c74-4c3e-8516-f49b04812061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3853688552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3853688552
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2560598838
Short name T185
Test name
Test status
Simulation time 508525996 ps
CPU time 19.05 seconds
Started Jul 23 04:49:03 PM PDT 24
Finished Jul 23 04:49:27 PM PDT 24
Peak memory 240928 kb
Host smart-01efb7c8-b9eb-4730-97e5-29f1c6303979
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2560598838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.2560598838
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3643078423
Short name T135
Test name
Test status
Simulation time 15648639139 ps
CPU time 153.37 seconds
Started Jul 23 04:49:04 PM PDT 24
Finished Jul 23 04:51:42 PM PDT 24
Peak memory 266024 kb
Host smart-ade30933-1fd9-4bfd-8f25-649f34084139
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3643078423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3643078423
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3276957795
Short name T127
Test name
Test status
Simulation time 51493770805 ps
CPU time 1040.82 seconds
Started Jul 23 04:49:03 PM PDT 24
Finished Jul 23 05:06:29 PM PDT 24
Peak memory 265992 kb
Host smart-b955f6b0-e0ee-4078-8e98-4f5d6084268b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276957795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.3276957795
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.126467441
Short name T714
Test name
Test status
Simulation time 111885101 ps
CPU time 15.01 seconds
Started Jul 23 04:49:05 PM PDT 24
Finished Jul 23 04:49:25 PM PDT 24
Peak memory 249264 kb
Host smart-2c681089-4a97-482a-9125-756d2d3d39f1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=126467441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.126467441
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.4129598586
Short name T152
Test name
Test status
Simulation time 57560090 ps
CPU time 3.76 seconds
Started Jul 23 04:49:02 PM PDT 24
Finished Jul 23 04:49:09 PM PDT 24
Peak memory 238056 kb
Host smart-51f5c768-236e-487d-aa86-9866d20e73ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4129598586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.4129598586
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.1655557310
Short name T825
Test name
Test status
Simulation time 10473186593 ps
CPU time 125.27 seconds
Started Jul 23 04:48:21 PM PDT 24
Finished Jul 23 04:50:31 PM PDT 24
Peak memory 240940 kb
Host smart-ca8aa7de-8e97-4912-b241-70ce3d50b97d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1655557310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.1655557310
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.3001587844
Short name T776
Test name
Test status
Simulation time 30506272794 ps
CPU time 273.93 seconds
Started Jul 23 04:48:21 PM PDT 24
Finished Jul 23 04:53:00 PM PDT 24
Peak memory 238104 kb
Host smart-307b05f4-fcc2-4c97-99dd-76f8b525a8ff
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3001587844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.3001587844
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2960052092
Short name T817
Test name
Test status
Simulation time 252414097 ps
CPU time 5.41 seconds
Started Jul 23 04:48:20 PM PDT 24
Finished Jul 23 04:48:30 PM PDT 24
Peak memory 249148 kb
Host smart-772cc1cf-2466-4b3d-b712-6bec7d7ff1b3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2960052092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2960052092
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2193326062
Short name T748
Test name
Test status
Simulation time 74601470 ps
CPU time 6.98 seconds
Started Jul 23 04:48:19 PM PDT 24
Finished Jul 23 04:48:29 PM PDT 24
Peak memory 240992 kb
Host smart-12a15ead-4592-41fa-a6b5-695bf06a6a26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193326062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2193326062
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.311960993
Short name T819
Test name
Test status
Simulation time 98096868 ps
CPU time 4.59 seconds
Started Jul 23 04:48:17 PM PDT 24
Finished Jul 23 04:48:25 PM PDT 24
Peak memory 238072 kb
Host smart-38cfe03a-7260-4855-a74e-6e9532cadb45
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=311960993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.311960993
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.507426467
Short name T813
Test name
Test status
Simulation time 7338570 ps
CPU time 1.36 seconds
Started Jul 23 04:48:19 PM PDT 24
Finished Jul 23 04:48:23 PM PDT 24
Peak memory 238136 kb
Host smart-86f25233-1d40-4d8a-93ec-e3a2c895b5aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=507426467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.507426467
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.270821771
Short name T810
Test name
Test status
Simulation time 248908712 ps
CPU time 18.07 seconds
Started Jul 23 04:48:19 PM PDT 24
Finished Jul 23 04:48:40 PM PDT 24
Peak memory 246196 kb
Host smart-69b5026c-47fc-4502-8cc1-440f35e57229
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=270821771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.270821771
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.496048439
Short name T133
Test name
Test status
Simulation time 28777830941 ps
CPU time 162.2 seconds
Started Jul 23 04:48:16 PM PDT 24
Finished Jul 23 04:51:02 PM PDT 24
Peak memory 267124 kb
Host smart-5cda75d9-508e-4db0-8c58-c3ff4f0e073a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=496048439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_error
s.496048439
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2258785574
Short name T125
Test name
Test status
Simulation time 14843838230 ps
CPU time 557.67 seconds
Started Jul 23 04:48:10 PM PDT 24
Finished Jul 23 04:57:34 PM PDT 24
Peak memory 266052 kb
Host smart-2f85948a-6bf2-4739-8331-3a863d126771
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258785574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2258785574
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.804303252
Short name T734
Test name
Test status
Simulation time 404001003 ps
CPU time 6.65 seconds
Started Jul 23 04:48:16 PM PDT 24
Finished Jul 23 04:48:27 PM PDT 24
Peak memory 251640 kb
Host smart-4c0fc260-6db4-48d9-8f9b-29865cc59d3d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=804303252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.804303252
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.231763189
Short name T757
Test name
Test status
Simulation time 8691512 ps
CPU time 1.37 seconds
Started Jul 23 04:49:02 PM PDT 24
Finished Jul 23 04:49:08 PM PDT 24
Peak memory 237140 kb
Host smart-dd03c2d3-fe03-47f7-9e3d-5fd4994b6969
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=231763189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.231763189
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.496081130
Short name T774
Test name
Test status
Simulation time 6993410 ps
CPU time 1.44 seconds
Started Jul 23 04:49:03 PM PDT 24
Finished Jul 23 04:49:10 PM PDT 24
Peak memory 238144 kb
Host smart-337cc1df-74f2-4656-8856-33da42d88d24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=496081130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.496081130
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2826666418
Short name T789
Test name
Test status
Simulation time 8923121 ps
CPU time 1.36 seconds
Started Jul 23 04:49:02 PM PDT 24
Finished Jul 23 04:49:07 PM PDT 24
Peak memory 237168 kb
Host smart-f772c082-428e-492d-9c3a-ea83e6aed705
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2826666418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.2826666418
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2462574026
Short name T758
Test name
Test status
Simulation time 15543343 ps
CPU time 1.89 seconds
Started Jul 23 04:49:03 PM PDT 24
Finished Jul 23 04:49:10 PM PDT 24
Peak memory 237160 kb
Host smart-bc8c7854-bab1-44d3-8926-3ddae4951153
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2462574026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2462574026
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1688919431
Short name T762
Test name
Test status
Simulation time 24541894 ps
CPU time 1.28 seconds
Started Jul 23 04:49:01 PM PDT 24
Finished Jul 23 04:49:04 PM PDT 24
Peak memory 238144 kb
Host smart-512585c0-ff4e-49df-a6c8-08ce9041efa0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1688919431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1688919431
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1015559628
Short name T775
Test name
Test status
Simulation time 10130743 ps
CPU time 1.55 seconds
Started Jul 23 04:49:03 PM PDT 24
Finished Jul 23 04:49:09 PM PDT 24
Peak memory 237176 kb
Host smart-ebc0ce2d-9cf3-4f15-a982-9c8c29343a38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1015559628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1015559628
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.914647070
Short name T760
Test name
Test status
Simulation time 26347191 ps
CPU time 1.52 seconds
Started Jul 23 04:49:03 PM PDT 24
Finished Jul 23 04:49:09 PM PDT 24
Peak memory 238084 kb
Host smart-a111bc81-8899-4b39-9c90-7f0766819307
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=914647070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.914647070
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1102051390
Short name T348
Test name
Test status
Simulation time 18288159 ps
CPU time 1.36 seconds
Started Jul 23 04:49:03 PM PDT 24
Finished Jul 23 04:49:09 PM PDT 24
Peak memory 237200 kb
Host smart-2354e426-f8fa-404b-85c6-8827fa716a3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1102051390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1102051390
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3546317634
Short name T809
Test name
Test status
Simulation time 66750247445 ps
CPU time 248.33 seconds
Started Jul 23 04:48:19 PM PDT 24
Finished Jul 23 04:52:32 PM PDT 24
Peak memory 242080 kb
Host smart-a91ad295-d4ea-4e3e-8fea-84273f144170
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3546317634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3546317634
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.2668424446
Short name T184
Test name
Test status
Simulation time 2911108740 ps
CPU time 169.71 seconds
Started Jul 23 04:48:18 PM PDT 24
Finished Jul 23 04:51:11 PM PDT 24
Peak memory 237196 kb
Host smart-5c8de073-d4a9-4b94-986e-e1c18d52d6f8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2668424446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.2668424446
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.2232573336
Short name T737
Test name
Test status
Simulation time 134272762 ps
CPU time 5.25 seconds
Started Jul 23 04:48:20 PM PDT 24
Finished Jul 23 04:48:30 PM PDT 24
Peak memory 249604 kb
Host smart-6d0d21f1-bce3-495f-828c-6f0e470104fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2232573336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.2232573336
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3164330686
Short name T785
Test name
Test status
Simulation time 137859473 ps
CPU time 10.41 seconds
Started Jul 23 04:48:19 PM PDT 24
Finished Jul 23 04:48:33 PM PDT 24
Peak memory 240168 kb
Host smart-50becf59-d5ed-49e6-b6b1-3c50a418661c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3164330686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3164330686
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1725010881
Short name T831
Test name
Test status
Simulation time 357841231 ps
CPU time 7.22 seconds
Started Jul 23 04:48:19 PM PDT 24
Finished Jul 23 04:48:29 PM PDT 24
Peak memory 237076 kb
Host smart-14a0c9d3-ea14-410d-abbb-f368ed527ba9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1725010881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1725010881
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1500115732
Short name T347
Test name
Test status
Simulation time 6904492 ps
CPU time 1.42 seconds
Started Jul 23 04:48:17 PM PDT 24
Finished Jul 23 04:48:22 PM PDT 24
Peak memory 238104 kb
Host smart-531f099e-bd3e-457b-a880-44aef95df939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1500115732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1500115732
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2377112103
Short name T787
Test name
Test status
Simulation time 313071046 ps
CPU time 22.03 seconds
Started Jul 23 04:48:19 PM PDT 24
Finished Jul 23 04:48:45 PM PDT 24
Peak memory 245248 kb
Host smart-1b0f8945-e4a7-46de-a708-2adf2b2b0c89
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2377112103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2377112103
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1412071062
Short name T124
Test name
Test status
Simulation time 16090434099 ps
CPU time 143.45 seconds
Started Jul 23 04:48:21 PM PDT 24
Finished Jul 23 04:50:49 PM PDT 24
Peak memory 266044 kb
Host smart-56006c87-879c-405b-938d-f6a91c8a497c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1412071062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1412071062
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3851339768
Short name T143
Test name
Test status
Simulation time 12155085748 ps
CPU time 485.55 seconds
Started Jul 23 04:48:18 PM PDT 24
Finished Jul 23 04:56:27 PM PDT 24
Peak memory 269448 kb
Host smart-af2ec628-51a3-4845-be66-3ef526019950
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851339768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.3851339768
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.79001214
Short name T797
Test name
Test status
Simulation time 253558060 ps
CPU time 8.28 seconds
Started Jul 23 04:48:20 PM PDT 24
Finished Jul 23 04:48:33 PM PDT 24
Peak memory 254800 kb
Host smart-06a9ef45-8f16-4215-8f2d-e86099103f47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=79001214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.79001214
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3239214015
Short name T766
Test name
Test status
Simulation time 52540167 ps
CPU time 1.41 seconds
Started Jul 23 04:49:03 PM PDT 24
Finished Jul 23 04:49:08 PM PDT 24
Peak memory 237180 kb
Host smart-f38e584a-6ebd-4f69-959d-0cd1c65fcd86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3239214015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3239214015
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.4090291780
Short name T761
Test name
Test status
Simulation time 9988606 ps
CPU time 1.62 seconds
Started Jul 23 04:49:03 PM PDT 24
Finished Jul 23 04:49:09 PM PDT 24
Peak memory 238144 kb
Host smart-4fa8f7ef-72ba-4264-88bc-5ec948e49a03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4090291780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.4090291780
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.501617158
Short name T156
Test name
Test status
Simulation time 15534607 ps
CPU time 1.27 seconds
Started Jul 23 04:49:04 PM PDT 24
Finished Jul 23 04:49:11 PM PDT 24
Peak memory 238060 kb
Host smart-2ad61ee9-f2b1-4d28-85cc-65c9c8fceccc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=501617158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.501617158
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.850077712
Short name T834
Test name
Test status
Simulation time 7623657 ps
CPU time 1.35 seconds
Started Jul 23 04:49:03 PM PDT 24
Finished Jul 23 04:49:09 PM PDT 24
Peak memory 236160 kb
Host smart-7c030103-6473-44b4-bc5c-8afc8b83c11c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=850077712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.850077712
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.6491867
Short name T784
Test name
Test status
Simulation time 14789985 ps
CPU time 1.35 seconds
Started Jul 23 04:49:02 PM PDT 24
Finished Jul 23 04:49:07 PM PDT 24
Peak memory 238152 kb
Host smart-60bcf2b8-5422-4b6f-9061-34e61888ea6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=6491867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.6491867
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2201426856
Short name T718
Test name
Test status
Simulation time 24631602 ps
CPU time 1.36 seconds
Started Jul 23 04:49:02 PM PDT 24
Finished Jul 23 04:49:08 PM PDT 24
Peak memory 237348 kb
Host smart-8ad068e5-b07f-41cb-a5b9-ba44cd7a7520
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2201426856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2201426856
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.589063875
Short name T754
Test name
Test status
Simulation time 11903513 ps
CPU time 1.39 seconds
Started Jul 23 04:49:02 PM PDT 24
Finished Jul 23 04:49:07 PM PDT 24
Peak memory 238144 kb
Host smart-1bcbe33f-8624-4064-b280-65df4571a370
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=589063875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.589063875
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.45190622
Short name T731
Test name
Test status
Simulation time 6371237 ps
CPU time 1.41 seconds
Started Jul 23 04:49:03 PM PDT 24
Finished Jul 23 04:49:10 PM PDT 24
Peak memory 237236 kb
Host smart-34695d31-d58a-431e-bca8-d60cf22b4af5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=45190622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.45190622
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3981716964
Short name T815
Test name
Test status
Simulation time 10875375 ps
CPU time 1.59 seconds
Started Jul 23 04:49:07 PM PDT 24
Finished Jul 23 04:49:14 PM PDT 24
Peak memory 238144 kb
Host smart-907df708-eb3b-45ac-a4a9-dc72b72d5900
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3981716964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3981716964
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3770033827
Short name T765
Test name
Test status
Simulation time 24718942 ps
CPU time 1.51 seconds
Started Jul 23 04:49:03 PM PDT 24
Finished Jul 23 04:49:09 PM PDT 24
Peak memory 238156 kb
Host smart-ff578c7e-7a49-40ab-af69-7d6a957578bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3770033827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3770033827
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2124180081
Short name T187
Test name
Test status
Simulation time 3298420988 ps
CPU time 202.8 seconds
Started Jul 23 04:48:17 PM PDT 24
Finished Jul 23 04:51:44 PM PDT 24
Peak memory 241440 kb
Host smart-9a0a3c16-1696-4b2f-99d6-647ba03f89f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2124180081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2124180081
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.2558842928
Short name T730
Test name
Test status
Simulation time 4317564738 ps
CPU time 273.02 seconds
Started Jul 23 04:48:21 PM PDT 24
Finished Jul 23 04:52:58 PM PDT 24
Peak memory 237960 kb
Host smart-06f14ffc-fdbe-42e2-9c09-28b1c355ba61
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2558842928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.2558842928
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2073737759
Short name T830
Test name
Test status
Simulation time 72646274 ps
CPU time 6.52 seconds
Started Jul 23 04:48:19 PM PDT 24
Finished Jul 23 04:48:30 PM PDT 24
Peak memory 249448 kb
Host smart-627db459-e029-4a62-92f5-9b989e37c333
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2073737759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2073737759
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.3474286203
Short name T768
Test name
Test status
Simulation time 505786659 ps
CPU time 9.21 seconds
Started Jul 23 04:48:20 PM PDT 24
Finished Jul 23 04:48:33 PM PDT 24
Peak memory 251324 kb
Host smart-f3e7c041-b1e4-4e12-a567-df2d84797f54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474286203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.3474286203
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2387293866
Short name T782
Test name
Test status
Simulation time 124067864 ps
CPU time 9.09 seconds
Started Jul 23 04:48:20 PM PDT 24
Finished Jul 23 04:48:33 PM PDT 24
Peak memory 240940 kb
Host smart-b22b9ecc-3df4-4be4-accf-4a3a96e73c2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2387293866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2387293866
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1017256246
Short name T822
Test name
Test status
Simulation time 25903151 ps
CPU time 1.61 seconds
Started Jul 23 04:48:17 PM PDT 24
Finished Jul 23 04:48:22 PM PDT 24
Peak memory 238060 kb
Host smart-f330447e-2ec5-43cb-bcf8-55e56419bb84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1017256246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1017256246
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1932799302
Short name T186
Test name
Test status
Simulation time 175151259 ps
CPU time 10.91 seconds
Started Jul 23 04:48:22 PM PDT 24
Finished Jul 23 04:48:37 PM PDT 24
Peak memory 245256 kb
Host smart-3bf6895e-a9af-4334-b7cd-4fd0b3688af5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1932799302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1932799302
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1746478339
Short name T140
Test name
Test status
Simulation time 806928327 ps
CPU time 93.38 seconds
Started Jul 23 04:48:19 PM PDT 24
Finished Jul 23 04:49:56 PM PDT 24
Peak memory 257988 kb
Host smart-3616b443-ec57-4f14-aa26-71b4ea44127f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1746478339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1746478339
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1727908164
Short name T136
Test name
Test status
Simulation time 51620907465 ps
CPU time 532.82 seconds
Started Jul 23 04:48:21 PM PDT 24
Finished Jul 23 04:57:18 PM PDT 24
Peak memory 270148 kb
Host smart-58206919-08f4-4b48-91ba-4db19ba10b23
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727908164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1727908164
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.12441267
Short name T812
Test name
Test status
Simulation time 568267907 ps
CPU time 9.17 seconds
Started Jul 23 04:48:20 PM PDT 24
Finished Jul 23 04:48:33 PM PDT 24
Peak memory 257240 kb
Host smart-b9cf2f16-123e-46fa-ad40-93bf38f7184f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=12441267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.12441267
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.1879862819
Short name T777
Test name
Test status
Simulation time 6466325 ps
CPU time 1.45 seconds
Started Jul 23 04:49:05 PM PDT 24
Finished Jul 23 04:49:11 PM PDT 24
Peak memory 238060 kb
Host smart-45044857-32fb-4ccd-a001-8e187ff0a2c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1879862819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.1879862819
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.4209625593
Short name T154
Test name
Test status
Simulation time 18622648 ps
CPU time 1.43 seconds
Started Jul 23 04:49:03 PM PDT 24
Finished Jul 23 04:49:08 PM PDT 24
Peak memory 238108 kb
Host smart-daeaeabf-1670-4473-92f5-3820c200cdf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4209625593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.4209625593
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2310565644
Short name T795
Test name
Test status
Simulation time 14544272 ps
CPU time 1.43 seconds
Started Jul 23 04:49:03 PM PDT 24
Finished Jul 23 04:49:09 PM PDT 24
Peak memory 238104 kb
Host smart-ddd31fc9-6503-4c5f-aa4d-8bc780559b6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2310565644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2310565644
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3845273892
Short name T741
Test name
Test status
Simulation time 10151353 ps
CPU time 1.4 seconds
Started Jul 23 04:49:06 PM PDT 24
Finished Jul 23 04:49:13 PM PDT 24
Peak memory 238104 kb
Host smart-66b88b2c-e765-4fce-a6a4-afbc00ff3b2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3845273892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3845273892
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1296358199
Short name T717
Test name
Test status
Simulation time 12077613 ps
CPU time 1.43 seconds
Started Jul 23 04:49:14 PM PDT 24
Finished Jul 23 04:49:23 PM PDT 24
Peak memory 238112 kb
Host smart-499144ca-07d4-4027-b9da-698c47bc26a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1296358199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1296358199
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2849755025
Short name T720
Test name
Test status
Simulation time 10244517 ps
CPU time 1.63 seconds
Started Jul 23 04:49:10 PM PDT 24
Finished Jul 23 04:49:18 PM PDT 24
Peak memory 237276 kb
Host smart-e62f5d66-15ff-476a-ac69-b721820b1caa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2849755025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2849755025
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.4209458624
Short name T733
Test name
Test status
Simulation time 15033073 ps
CPU time 1.34 seconds
Started Jul 23 04:49:10 PM PDT 24
Finished Jul 23 04:49:17 PM PDT 24
Peak memory 236068 kb
Host smart-969db178-d573-4a80-b64e-48de13c5da78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4209458624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.4209458624
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1195727540
Short name T824
Test name
Test status
Simulation time 7636830 ps
CPU time 1.4 seconds
Started Jul 23 04:49:09 PM PDT 24
Finished Jul 23 04:49:17 PM PDT 24
Peak memory 236112 kb
Host smart-fa8a92ae-68c4-442b-a347-a2b271139f71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1195727540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1195727540
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.900833650
Short name T155
Test name
Test status
Simulation time 16594398 ps
CPU time 1.32 seconds
Started Jul 23 04:49:10 PM PDT 24
Finished Jul 23 04:49:17 PM PDT 24
Peak memory 238068 kb
Host smart-482b5ffd-8847-4811-88e2-f28db487ccec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=900833650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.900833650
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.811097914
Short name T799
Test name
Test status
Simulation time 17908594 ps
CPU time 1.92 seconds
Started Jul 23 04:49:10 PM PDT 24
Finished Jul 23 04:49:18 PM PDT 24
Peak memory 238064 kb
Host smart-42e94001-a642-4980-9a08-ab1a75d1ea1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=811097914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.811097914
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3144947743
Short name T823
Test name
Test status
Simulation time 54661435 ps
CPU time 4.77 seconds
Started Jul 23 04:48:26 PM PDT 24
Finished Jul 23 04:48:35 PM PDT 24
Peak memory 241004 kb
Host smart-33a6bdd8-42ff-4658-8bc9-0ff073cc6978
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144947743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3144947743
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.1035990882
Short name T193
Test name
Test status
Simulation time 124199618 ps
CPU time 9.66 seconds
Started Jul 23 04:48:28 PM PDT 24
Finished Jul 23 04:48:41 PM PDT 24
Peak memory 238028 kb
Host smart-6ea9b5ab-a709-431b-a0e2-4921a4a3f561
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1035990882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.1035990882
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2177584510
Short name T829
Test name
Test status
Simulation time 22385702 ps
CPU time 1.39 seconds
Started Jul 23 04:48:30 PM PDT 24
Finished Jul 23 04:48:34 PM PDT 24
Peak memory 238068 kb
Host smart-2a0a28d8-d2a8-485b-8cd7-02db698d3939
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2177584510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2177584510
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.3723206371
Short name T800
Test name
Test status
Simulation time 1503870454 ps
CPU time 22.33 seconds
Started Jul 23 04:48:26 PM PDT 24
Finished Jul 23 04:48:52 PM PDT 24
Peak memory 246288 kb
Host smart-74bfe587-83e6-4689-9b24-9c5c4b41b298
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3723206371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.3723206371
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.1241649412
Short name T130
Test name
Test status
Simulation time 4132012311 ps
CPU time 328.85 seconds
Started Jul 23 04:48:22 PM PDT 24
Finished Jul 23 04:53:55 PM PDT 24
Peak memory 272336 kb
Host smart-d34544dd-38c5-45be-8577-def42cff91a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1241649412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.1241649412
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3090685649
Short name T746
Test name
Test status
Simulation time 354336571 ps
CPU time 11.02 seconds
Started Jul 23 04:48:21 PM PDT 24
Finished Jul 23 04:48:37 PM PDT 24
Peak memory 248240 kb
Host smart-e6d820f7-6024-44ed-be04-402f95cfe41e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3090685649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3090685649
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1526540476
Short name T804
Test name
Test status
Simulation time 97590974 ps
CPU time 5.22 seconds
Started Jul 23 04:48:26 PM PDT 24
Finished Jul 23 04:48:35 PM PDT 24
Peak memory 241020 kb
Host smart-18b78761-2718-4e4d-ba7d-b16618c443e1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526540476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1526540476
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2783961372
Short name T725
Test name
Test status
Simulation time 19616635 ps
CPU time 3.53 seconds
Started Jul 23 04:48:29 PM PDT 24
Finished Jul 23 04:48:36 PM PDT 24
Peak memory 238004 kb
Host smart-ea2bd6a2-c668-49e0-a7d3-7f6f0fc73f21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2783961372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2783961372
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3873379344
Short name T346
Test name
Test status
Simulation time 16232095 ps
CPU time 1.31 seconds
Started Jul 23 04:48:27 PM PDT 24
Finished Jul 23 04:48:32 PM PDT 24
Peak memory 238064 kb
Host smart-1f88df3a-72d0-4b0e-a254-e058235481bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3873379344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3873379344
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1661630256
Short name T808
Test name
Test status
Simulation time 4067767917 ps
CPU time 35.33 seconds
Started Jul 23 04:48:25 PM PDT 24
Finished Jul 23 04:49:04 PM PDT 24
Peak memory 249292 kb
Host smart-00e45b66-30de-460a-bd71-9dfb7fb4000c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1661630256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1661630256
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2188437414
Short name T146
Test name
Test status
Simulation time 7323517833 ps
CPU time 143.12 seconds
Started Jul 23 04:48:29 PM PDT 24
Finished Jul 23 04:50:55 PM PDT 24
Peak memory 267208 kb
Host smart-f7309a08-f3f0-4d22-873e-1126736f4976
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2188437414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.2188437414
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.691452009
Short name T818
Test name
Test status
Simulation time 82039083 ps
CPU time 6.56 seconds
Started Jul 23 04:48:29 PM PDT 24
Finished Jul 23 04:48:38 PM PDT 24
Peak memory 254132 kb
Host smart-586f2e74-06a7-418f-bf34-dbd0546c6d5f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=691452009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.691452009
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.231062181
Short name T353
Test name
Test status
Simulation time 60846116 ps
CPU time 5.85 seconds
Started Jul 23 04:48:25 PM PDT 24
Finished Jul 23 04:48:34 PM PDT 24
Peak memory 240952 kb
Host smart-bcb87066-2a4d-48cd-af1a-24eb1ad81167
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231062181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.231062181
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3056348718
Short name T773
Test name
Test status
Simulation time 506212685 ps
CPU time 9.47 seconds
Started Jul 23 04:48:27 PM PDT 24
Finished Jul 23 04:48:40 PM PDT 24
Peak memory 238076 kb
Host smart-812b25f8-d055-4e25-a194-dd2b9b0154ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3056348718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3056348718
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3136905673
Short name T736
Test name
Test status
Simulation time 15526031 ps
CPU time 1.38 seconds
Started Jul 23 04:48:29 PM PDT 24
Finished Jul 23 04:48:34 PM PDT 24
Peak memory 236188 kb
Host smart-af5db369-3d25-4a9b-b747-577322c34e2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3136905673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3136905673
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3885826109
Short name T793
Test name
Test status
Simulation time 185954751 ps
CPU time 14.04 seconds
Started Jul 23 04:48:29 PM PDT 24
Finished Jul 23 04:48:46 PM PDT 24
Peak memory 246244 kb
Host smart-da65976b-0e80-4d24-b902-f86a8297f9d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3885826109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3885826109
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.4197927395
Short name T139
Test name
Test status
Simulation time 5653189510 ps
CPU time 441.15 seconds
Started Jul 23 04:48:26 PM PDT 24
Finished Jul 23 04:55:51 PM PDT 24
Peak memory 266024 kb
Host smart-66e30df0-f847-46a4-9248-01985be08c4d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4197927395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.4197927395
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.1090823646
Short name T132
Test name
Test status
Simulation time 24026857158 ps
CPU time 481.06 seconds
Started Jul 23 04:48:28 PM PDT 24
Finished Jul 23 04:56:33 PM PDT 24
Peak memory 266180 kb
Host smart-3b1c4995-1182-4e5c-8530-071cb5784403
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090823646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.1090823646
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.4053319290
Short name T722
Test name
Test status
Simulation time 3563464572 ps
CPU time 14.56 seconds
Started Jul 23 04:48:26 PM PDT 24
Finished Jul 23 04:48:44 PM PDT 24
Peak memory 254412 kb
Host smart-cbc5024d-9942-42a0-bb58-3db4f0deb11a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4053319290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.4053319290
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1355137319
Short name T167
Test name
Test status
Simulation time 592306451 ps
CPU time 36.41 seconds
Started Jul 23 04:48:26 PM PDT 24
Finished Jul 23 04:49:07 PM PDT 24
Peak memory 240960 kb
Host smart-a48856d0-006e-4c0b-997f-bb22563488e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1355137319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.1355137319
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2048181616
Short name T780
Test name
Test status
Simulation time 61189938 ps
CPU time 8.79 seconds
Started Jul 23 04:48:37 PM PDT 24
Finished Jul 23 04:48:49 PM PDT 24
Peak memory 249200 kb
Host smart-48f7ce12-4eaf-4baf-be7c-a75c036ae886
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048181616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.2048181616
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.538686366
Short name T173
Test name
Test status
Simulation time 62657608 ps
CPU time 5.26 seconds
Started Jul 23 04:48:37 PM PDT 24
Finished Jul 23 04:48:45 PM PDT 24
Peak memory 237952 kb
Host smart-5c576c76-88aa-46de-a42c-9f67aa3726e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=538686366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.538686366
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.301932240
Short name T759
Test name
Test status
Simulation time 10344965 ps
CPU time 1.25 seconds
Started Jul 23 04:48:26 PM PDT 24
Finished Jul 23 04:48:31 PM PDT 24
Peak memory 238136 kb
Host smart-636fb0c5-38e5-4132-a7e0-df7474934340
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=301932240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.301932240
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.2520494504
Short name T769
Test name
Test status
Simulation time 1045411272 ps
CPU time 25.29 seconds
Started Jul 23 04:48:37 PM PDT 24
Finished Jul 23 04:49:06 PM PDT 24
Peak memory 246228 kb
Host smart-c120fd12-6026-4ac2-a70e-0bb1aea142e8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2520494504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.2520494504
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.735657894
Short name T750
Test name
Test status
Simulation time 710431415 ps
CPU time 22.54 seconds
Started Jul 23 04:48:25 PM PDT 24
Finished Jul 23 04:48:52 PM PDT 24
Peak memory 248384 kb
Host smart-51404dcf-545a-4a84-a4e6-3fc6a91bb368
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=735657894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.735657894
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.125041936
Short name T805
Test name
Test status
Simulation time 94719019 ps
CPU time 6.9 seconds
Started Jul 23 04:48:35 PM PDT 24
Finished Jul 23 04:48:45 PM PDT 24
Peak memory 241184 kb
Host smart-f4266138-e93e-48b6-b64f-a66de1dfa726
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125041936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.alert_handler_csr_mem_rw_with_rand_reset.125041936
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2773538213
Short name T764
Test name
Test status
Simulation time 20324887 ps
CPU time 3.2 seconds
Started Jul 23 04:48:35 PM PDT 24
Finished Jul 23 04:48:41 PM PDT 24
Peak memory 237984 kb
Host smart-f738d81e-39b2-4266-bee0-f9706602e49d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2773538213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2773538213
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.362440021
Short name T721
Test name
Test status
Simulation time 15712868 ps
CPU time 1.57 seconds
Started Jul 23 04:48:37 PM PDT 24
Finished Jul 23 04:48:41 PM PDT 24
Peak memory 238116 kb
Host smart-94d6fc34-1ef4-41dd-8dc4-1e66811ff471
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=362440021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.362440021
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.2849127738
Short name T763
Test name
Test status
Simulation time 635883669 ps
CPU time 23.99 seconds
Started Jul 23 04:48:35 PM PDT 24
Finished Jul 23 04:49:02 PM PDT 24
Peak memory 249172 kb
Host smart-e21102f1-980a-4e94-ae75-93092d76f61c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2849127738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.2849127738
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.528687400
Short name T116
Test name
Test status
Simulation time 6594198668 ps
CPU time 173.62 seconds
Started Jul 23 04:48:37 PM PDT 24
Finished Jul 23 04:51:34 PM PDT 24
Peak memory 269276 kb
Host smart-e9b38a25-c45f-4616-b613-871470204f5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=528687400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.528687400
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.1259505261
Short name T742
Test name
Test status
Simulation time 1171746003 ps
CPU time 17.99 seconds
Started Jul 23 04:48:34 PM PDT 24
Finished Jul 23 04:48:54 PM PDT 24
Peak memory 254744 kb
Host smart-63985ee5-9d1c-4b0f-ac4b-2b6cfc4a85f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1259505261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.1259505261
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.4101942489
Short name T194
Test name
Test status
Simulation time 100638160 ps
CPU time 4.02 seconds
Started Jul 23 04:48:34 PM PDT 24
Finished Jul 23 04:48:41 PM PDT 24
Peak memory 238044 kb
Host smart-c25cab63-a89c-4dee-a848-0cddd8c80f7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4101942489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.4101942489
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.2574474040
Short name T237
Test name
Test status
Simulation time 3374089712 ps
CPU time 35.88 seconds
Started Jul 23 04:49:55 PM PDT 24
Finished Jul 23 04:50:32 PM PDT 24
Peak memory 248636 kb
Host smart-8f105ddd-0d6f-4730-9931-0eb7a4c18d9b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2574474040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2574474040
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.4014983700
Short name T424
Test name
Test status
Simulation time 2855625663 ps
CPU time 118.37 seconds
Started Jul 23 04:49:56 PM PDT 24
Finished Jul 23 04:51:58 PM PDT 24
Peak memory 256824 kb
Host smart-f6e422dd-5aa7-4640-9507-4dd706a98a1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40149
83700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.4014983700
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2216237641
Short name T574
Test name
Test status
Simulation time 623540743 ps
CPU time 33.03 seconds
Started Jul 23 04:49:57 PM PDT 24
Finished Jul 23 04:50:34 PM PDT 24
Peak memory 255516 kb
Host smart-c7805c2a-aca6-41b4-ba1d-e2bd0ee0ff20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22162
37641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2216237641
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1988395396
Short name T5
Test name
Test status
Simulation time 17569885567 ps
CPU time 733.02 seconds
Started Jul 23 04:49:57 PM PDT 24
Finished Jul 23 05:02:15 PM PDT 24
Peak memory 272384 kb
Host smart-112ca8ef-2d50-4e8a-a7df-46f96d038052
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1988395396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1988395396
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.1108292797
Short name T468
Test name
Test status
Simulation time 248870763569 ps
CPU time 3019.9 seconds
Started Jul 23 04:49:55 PM PDT 24
Finished Jul 23 05:40:17 PM PDT 24
Peak memory 288240 kb
Host smart-f86e8545-1332-469d-b4bd-3dc1ffd8af39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108292797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.1108292797
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1436161748
Short name T300
Test name
Test status
Simulation time 50445091370 ps
CPU time 525.54 seconds
Started Jul 23 04:49:56 PM PDT 24
Finished Jul 23 04:58:44 PM PDT 24
Peak memory 248616 kb
Host smart-10ab0ecd-b91d-40f2-9873-1e8954c70209
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436161748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1436161748
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.458893413
Short name T430
Test name
Test status
Simulation time 703096351 ps
CPU time 39.58 seconds
Started Jul 23 04:49:59 PM PDT 24
Finished Jul 23 04:50:43 PM PDT 24
Peak memory 255828 kb
Host smart-71e7f3ec-db53-47e6-9152-fcd7a67bc8fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45889
3413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.458893413
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3506403229
Short name T488
Test name
Test status
Simulation time 600641479 ps
CPU time 21.9 seconds
Started Jul 23 04:49:56 PM PDT 24
Finished Jul 23 04:50:20 PM PDT 24
Peak memory 248996 kb
Host smart-5fc4fead-2312-4af1-a59b-71842f761bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35064
03229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3506403229
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.3450078639
Short name T395
Test name
Test status
Simulation time 4465197580 ps
CPU time 32.85 seconds
Started Jul 23 04:49:59 PM PDT 24
Finished Jul 23 04:50:36 PM PDT 24
Peak memory 248588 kb
Host smart-3bf6aaad-2e29-4e30-9afe-42b55762c459
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34500
78639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.3450078639
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.359343102
Short name T577
Test name
Test status
Simulation time 23639779 ps
CPU time 3.04 seconds
Started Jul 23 04:49:56 PM PDT 24
Finished Jul 23 04:50:01 PM PDT 24
Peak memory 250788 kb
Host smart-b7bfc5d7-f341-417b-b77c-1af38eef2c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35934
3102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.359343102
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.752247556
Short name T503
Test name
Test status
Simulation time 3629799420 ps
CPU time 74.79 seconds
Started Jul 23 04:49:56 PM PDT 24
Finished Jul 23 04:51:14 PM PDT 24
Peak memory 256796 kb
Host smart-18aab1cd-6f35-4b3a-8eb9-db917b611440
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752247556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_hand
ler_stress_all.752247556
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1091985184
Short name T299
Test name
Test status
Simulation time 7301700884 ps
CPU time 851.66 seconds
Started Jul 23 04:49:55 PM PDT 24
Finished Jul 23 05:04:08 PM PDT 24
Peak memory 272812 kb
Host smart-3cdac7b2-52f9-4272-9712-c249b942fa51
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091985184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1091985184
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.2810298772
Short name T579
Test name
Test status
Simulation time 4770135752 ps
CPU time 42.91 seconds
Started Jul 23 04:49:58 PM PDT 24
Finished Jul 23 04:50:46 PM PDT 24
Peak memory 248592 kb
Host smart-452af7e1-8a36-4bce-bbf2-dfd54649b557
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2810298772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.2810298772
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1975154823
Short name T216
Test name
Test status
Simulation time 2919212536 ps
CPU time 70.45 seconds
Started Jul 23 04:49:57 PM PDT 24
Finished Jul 23 04:51:12 PM PDT 24
Peak memory 256780 kb
Host smart-014e8ba3-660f-48e3-bbb1-a49b44ada1bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19751
54823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1975154823
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.2785279953
Short name T681
Test name
Test status
Simulation time 405195400 ps
CPU time 25.2 seconds
Started Jul 23 04:49:57 PM PDT 24
Finished Jul 23 04:50:26 PM PDT 24
Peak memory 248524 kb
Host smart-7cdde27a-167c-4491-b4f8-b10ebfcce33d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27852
79953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2785279953
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.703899250
Short name T331
Test name
Test status
Simulation time 26617677189 ps
CPU time 1036.38 seconds
Started Jul 23 04:49:55 PM PDT 24
Finished Jul 23 05:07:13 PM PDT 24
Peak memory 273252 kb
Host smart-b1a14044-1358-4ef5-8b71-b44f6ea0ee79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=703899250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.703899250
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.2600867150
Short name T507
Test name
Test status
Simulation time 163025367084 ps
CPU time 2644.09 seconds
Started Jul 23 04:49:56 PM PDT 24
Finished Jul 23 05:34:05 PM PDT 24
Peak memory 288044 kb
Host smart-8c97a478-22ba-415e-8ff6-d05cfc396be9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600867150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.2600867150
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.1643884435
Short name T307
Test name
Test status
Simulation time 10254942476 ps
CPU time 221.86 seconds
Started Jul 23 04:49:59 PM PDT 24
Finished Jul 23 04:53:45 PM PDT 24
Peak memory 248660 kb
Host smart-fa3823fd-fc8f-412b-9560-c513995d9351
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643884435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1643884435
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.127009456
Short name T236
Test name
Test status
Simulation time 349666185 ps
CPU time 9.73 seconds
Started Jul 23 04:49:59 PM PDT 24
Finished Jul 23 04:50:12 PM PDT 24
Peak memory 248608 kb
Host smart-3d0fab11-2db3-4f50-a22b-6dd097edbd41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12700
9456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.127009456
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1528461782
Short name T616
Test name
Test status
Simulation time 915750815 ps
CPU time 36.45 seconds
Started Jul 23 04:49:56 PM PDT 24
Finished Jul 23 04:50:36 PM PDT 24
Peak memory 255928 kb
Host smart-82137edf-82b3-4bbf-87ac-30d3fa5087d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15284
61782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1528461782
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.988968390
Short name T14
Test name
Test status
Simulation time 1474609692 ps
CPU time 19.74 seconds
Started Jul 23 04:49:56 PM PDT 24
Finished Jul 23 04:50:19 PM PDT 24
Peak memory 271004 kb
Host smart-44c5b283-3d08-4357-8ea5-9194de505632
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=988968390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.988968390
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.4029955933
Short name T286
Test name
Test status
Simulation time 311035419 ps
CPU time 22.28 seconds
Started Jul 23 04:49:57 PM PDT 24
Finished Jul 23 04:50:24 PM PDT 24
Peak memory 248656 kb
Host smart-f35e2111-cece-44de-bf44-2bb58a0164b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40299
55933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.4029955933
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3135179814
Short name T367
Test name
Test status
Simulation time 10098237527 ps
CPU time 59.96 seconds
Started Jul 23 04:49:54 PM PDT 24
Finished Jul 23 04:50:56 PM PDT 24
Peak memory 256244 kb
Host smart-0947ce6b-5c28-403e-bfe8-e5828c95b58b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31351
79814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3135179814
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.1144844086
Short name T73
Test name
Test status
Simulation time 1683925546 ps
CPU time 72.07 seconds
Started Jul 23 04:49:57 PM PDT 24
Finished Jul 23 04:51:13 PM PDT 24
Peak memory 256724 kb
Host smart-832f43a8-d5e5-4951-8989-12ed1ac2d981
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144844086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.1144844086
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.582857721
Short name T245
Test name
Test status
Simulation time 565181475853 ps
CPU time 3322.85 seconds
Started Jul 23 04:49:54 PM PDT 24
Finished Jul 23 05:45:18 PM PDT 24
Peak memory 289772 kb
Host smart-28d7ef12-d1a7-4260-abaa-4e217cfb608d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582857721 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.582857721
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.918026229
Short name T213
Test name
Test status
Simulation time 79123578 ps
CPU time 3.58 seconds
Started Jul 23 04:50:22 PM PDT 24
Finished Jul 23 04:50:39 PM PDT 24
Peak memory 248868 kb
Host smart-60dab46e-aa9c-4793-9d13-3cb747c88015
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=918026229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.918026229
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.2279155292
Short name T444
Test name
Test status
Simulation time 88197903552 ps
CPU time 1478.42 seconds
Started Jul 23 04:50:24 PM PDT 24
Finished Jul 23 05:15:17 PM PDT 24
Peak memory 272548 kb
Host smart-fa977ee6-2faa-4034-a705-9126fd046a21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279155292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.2279155292
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1581533434
Short name T411
Test name
Test status
Simulation time 1385830627 ps
CPU time 19.47 seconds
Started Jul 23 04:50:23 PM PDT 24
Finished Jul 23 04:50:56 PM PDT 24
Peak memory 248592 kb
Host smart-4afd468f-8d4f-4135-a2b9-5973629f1648
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1581533434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1581533434
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.4267628515
Short name T614
Test name
Test status
Simulation time 2238282177 ps
CPU time 45.3 seconds
Started Jul 23 04:50:21 PM PDT 24
Finished Jul 23 04:51:20 PM PDT 24
Peak memory 256428 kb
Host smart-bd59174b-7267-4caf-9504-474fbb0f2246
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42676
28515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.4267628515
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3450288702
Short name T405
Test name
Test status
Simulation time 4058068873 ps
CPU time 62.71 seconds
Started Jul 23 04:50:28 PM PDT 24
Finished Jul 23 04:51:46 PM PDT 24
Peak memory 256144 kb
Host smart-77cb61f7-eadf-45fd-a8e4-14e593bf299f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34502
88702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3450288702
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2193053156
Short name T335
Test name
Test status
Simulation time 28677646592 ps
CPU time 1659.7 seconds
Started Jul 23 04:50:29 PM PDT 24
Finished Jul 23 05:18:23 PM PDT 24
Peak memory 272500 kb
Host smart-73f4b489-ccad-4876-81f9-8a5c1fa12ace
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193053156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2193053156
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.4201067731
Short name T104
Test name
Test status
Simulation time 272746564404 ps
CPU time 1676.16 seconds
Started Jul 23 04:50:21 PM PDT 24
Finished Jul 23 05:18:30 PM PDT 24
Peak memory 272812 kb
Host smart-bb5c987a-7aff-4873-ae59-5137aeda9089
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201067731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.4201067731
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.322167312
Short name T447
Test name
Test status
Simulation time 340290141 ps
CPU time 17.48 seconds
Started Jul 23 04:50:23 PM PDT 24
Finished Jul 23 04:50:54 PM PDT 24
Peak memory 256012 kb
Host smart-036fd4ba-4b72-47ab-b6d7-96cd64fcf37c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32216
7312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.322167312
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.2498045645
Short name T46
Test name
Test status
Simulation time 811642680 ps
CPU time 14.99 seconds
Started Jul 23 04:50:21 PM PDT 24
Finished Jul 23 04:50:49 PM PDT 24
Peak memory 248772 kb
Host smart-50305a4e-e155-4a7f-8aad-2e8f988135cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24980
45645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.2498045645
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2879045793
Short name T379
Test name
Test status
Simulation time 159514793 ps
CPU time 4.13 seconds
Started Jul 23 04:50:24 PM PDT 24
Finished Jul 23 04:50:43 PM PDT 24
Peak memory 249000 kb
Host smart-724a5408-ab3d-45fb-ae61-4d38fcc234aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28790
45793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2879045793
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1552303773
Short name T247
Test name
Test status
Simulation time 1060279769 ps
CPU time 59.76 seconds
Started Jul 23 04:50:21 PM PDT 24
Finished Jul 23 04:51:34 PM PDT 24
Peak memory 256276 kb
Host smart-dea8f8d7-5568-4471-b6ed-15a450835f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15523
03773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1552303773
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.1560212856
Short name T210
Test name
Test status
Simulation time 36615196 ps
CPU time 2.4 seconds
Started Jul 23 04:50:25 PM PDT 24
Finished Jul 23 04:50:42 PM PDT 24
Peak memory 248924 kb
Host smart-726e2f71-ac64-4ff6-8220-895052dcff39
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1560212856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.1560212856
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3775571359
Short name T469
Test name
Test status
Simulation time 31654011164 ps
CPU time 1847.28 seconds
Started Jul 23 04:50:20 PM PDT 24
Finished Jul 23 05:21:18 PM PDT 24
Peak memory 280852 kb
Host smart-b3bec84b-aeaf-4c2d-86a3-72ca4fadbd7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775571359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3775571359
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.1981412528
Short name T459
Test name
Test status
Simulation time 499000271 ps
CPU time 20.95 seconds
Started Jul 23 04:50:28 PM PDT 24
Finished Jul 23 04:51:03 PM PDT 24
Peak memory 248564 kb
Host smart-c9b1fd7b-02c4-42ea-899d-4a79c902c2fd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1981412528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1981412528
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.3685486624
Short name T500
Test name
Test status
Simulation time 5404060429 ps
CPU time 316.4 seconds
Started Jul 23 04:50:21 PM PDT 24
Finished Jul 23 04:55:51 PM PDT 24
Peak memory 256760 kb
Host smart-a162d9fb-8587-443d-8871-394ba3233bcb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36854
86624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3685486624
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2311323200
Short name T539
Test name
Test status
Simulation time 1852534960 ps
CPU time 55.81 seconds
Started Jul 23 04:50:25 PM PDT 24
Finished Jul 23 04:51:35 PM PDT 24
Peak memory 256396 kb
Host smart-ac0c7c8c-a7f0-4ca1-b0e9-091f5b74364a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23113
23200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2311323200
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.3123621010
Short name T248
Test name
Test status
Simulation time 15630618277 ps
CPU time 657.15 seconds
Started Jul 23 04:50:25 PM PDT 24
Finished Jul 23 05:01:37 PM PDT 24
Peak memory 267048 kb
Host smart-f82bcc97-4a68-4e75-a840-dc5be6f7f6f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123621010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3123621010
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.2056061825
Short name T659
Test name
Test status
Simulation time 9350815372 ps
CPU time 154.49 seconds
Started Jul 23 04:50:29 PM PDT 24
Finished Jul 23 04:53:18 PM PDT 24
Peak memory 248632 kb
Host smart-a8c183da-c9a3-49e2-8ebb-56f9d3d64942
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056061825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.2056061825
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.586427783
Short name T369
Test name
Test status
Simulation time 2478289591 ps
CPU time 40.77 seconds
Started Jul 23 04:50:28 PM PDT 24
Finished Jul 23 04:51:24 PM PDT 24
Peak memory 256768 kb
Host smart-0d17456b-f7fa-4f2c-85f2-18e53ee9b5a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58642
7783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.586427783
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2013133911
Short name T33
Test name
Test status
Simulation time 206977953 ps
CPU time 19.17 seconds
Started Jul 23 04:50:24 PM PDT 24
Finished Jul 23 04:50:58 PM PDT 24
Peak memory 248924 kb
Host smart-2356f640-845d-4604-ba39-509891bad3a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20131
33911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2013133911
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.193799538
Short name T683
Test name
Test status
Simulation time 666964976 ps
CPU time 38.72 seconds
Started Jul 23 04:50:21 PM PDT 24
Finished Jul 23 04:51:12 PM PDT 24
Peak memory 256704 kb
Host smart-6d2bd427-5f84-462a-88e7-1a44d10657f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19379
9538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.193799538
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1415453433
Short name T562
Test name
Test status
Simulation time 749734361 ps
CPU time 42.72 seconds
Started Jul 23 04:50:22 PM PDT 24
Finished Jul 23 04:51:18 PM PDT 24
Peak memory 256684 kb
Host smart-329e04cd-f096-4101-804c-14d5d4508c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14154
53433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1415453433
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.665634641
Short name T77
Test name
Test status
Simulation time 17415805526 ps
CPU time 1506.61 seconds
Started Jul 23 04:50:27 PM PDT 24
Finished Jul 23 05:15:49 PM PDT 24
Peak memory 288644 kb
Host smart-40efc711-4751-4c88-a08a-a6299e0662c5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665634641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_han
dler_stress_all.665634641
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.3790252750
Short name T72
Test name
Test status
Simulation time 158121737072 ps
CPU time 2742.33 seconds
Started Jul 23 04:50:29 PM PDT 24
Finished Jul 23 05:36:27 PM PDT 24
Peak memory 297900 kb
Host smart-e49c300f-9870-495b-91d2-5862fb606766
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790252750 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.3790252750
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3265727794
Short name T476
Test name
Test status
Simulation time 328090481192 ps
CPU time 3062.05 seconds
Started Jul 23 04:50:20 PM PDT 24
Finished Jul 23 05:41:34 PM PDT 24
Peak memory 281404 kb
Host smart-1561c46f-e2d9-4405-ac78-4058f96951df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265727794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3265727794
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2132040498
Short name T394
Test name
Test status
Simulation time 539024571 ps
CPU time 14.62 seconds
Started Jul 23 04:50:30 PM PDT 24
Finished Jul 23 04:51:00 PM PDT 24
Peak memory 248624 kb
Host smart-383e2190-7973-4888-8b11-fa5f64cebfd7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2132040498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2132040498
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.4260106554
Short name T553
Test name
Test status
Simulation time 147125748 ps
CPU time 18.32 seconds
Started Jul 23 04:50:41 PM PDT 24
Finished Jul 23 04:51:17 PM PDT 24
Peak memory 255588 kb
Host smart-ffc43e29-3c6d-44e1-9d05-ac5bcde2b3fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42601
06554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.4260106554
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3231113067
Short name T570
Test name
Test status
Simulation time 314879051 ps
CPU time 33.09 seconds
Started Jul 23 04:50:23 PM PDT 24
Finished Jul 23 04:51:11 PM PDT 24
Peak memory 248500 kb
Host smart-08f188b1-0244-4981-bd6e-fe6a3792d1ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32311
13067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3231113067
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.1980164325
Short name T319
Test name
Test status
Simulation time 44102711443 ps
CPU time 1121.41 seconds
Started Jul 23 04:50:30 PM PDT 24
Finished Jul 23 05:09:27 PM PDT 24
Peak memory 288708 kb
Host smart-e5a6b727-e5ff-4ea7-b20a-6e54e7e6480f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980164325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1980164325
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.895864423
Short name T543
Test name
Test status
Simulation time 75422941457 ps
CPU time 1389.91 seconds
Started Jul 23 04:50:29 PM PDT 24
Finished Jul 23 05:13:53 PM PDT 24
Peak memory 289476 kb
Host smart-0b7c0349-b49d-4a65-b7af-67f46c44e2ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895864423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.895864423
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2911518392
Short name T677
Test name
Test status
Simulation time 6088559553 ps
CPU time 253.42 seconds
Started Jul 23 04:50:29 PM PDT 24
Finished Jul 23 04:54:58 PM PDT 24
Peak memory 255268 kb
Host smart-979739b9-ca95-451e-9190-2b9a62e845b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911518392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2911518392
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2989101905
Short name T49
Test name
Test status
Simulation time 730593365 ps
CPU time 44.77 seconds
Started Jul 23 04:50:28 PM PDT 24
Finished Jul 23 04:51:28 PM PDT 24
Peak memory 248528 kb
Host smart-bc99b419-afc1-4598-845e-ebfd2daa6660
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29891
01905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2989101905
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3956815587
Short name T533
Test name
Test status
Simulation time 746526189 ps
CPU time 11.68 seconds
Started Jul 23 04:50:24 PM PDT 24
Finished Jul 23 04:50:50 PM PDT 24
Peak memory 248548 kb
Host smart-6bd638f8-8714-4e98-9239-8e3e0adac1c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39568
15587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3956815587
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.833597926
Short name T709
Test name
Test status
Simulation time 1471808066 ps
CPU time 47.81 seconds
Started Jul 23 04:50:23 PM PDT 24
Finished Jul 23 04:51:26 PM PDT 24
Peak memory 255696 kb
Host smart-336e28ce-6ad8-403b-bffd-cc431343b9bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83359
7926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.833597926
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.4262247430
Short name T41
Test name
Test status
Simulation time 197601261792 ps
CPU time 2914.61 seconds
Started Jul 23 04:50:21 PM PDT 24
Finished Jul 23 05:39:09 PM PDT 24
Peak memory 297800 kb
Host smart-72b595f4-d928-4b59-be49-2711e6ac51f5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262247430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.4262247430
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1502532806
Short name T385
Test name
Test status
Simulation time 12815749538 ps
CPU time 1184.57 seconds
Started Jul 23 04:50:33 PM PDT 24
Finished Jul 23 05:10:34 PM PDT 24
Peak memory 285676 kb
Host smart-45bd6fee-a9eb-4a65-885b-754e581e63b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502532806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1502532806
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.2774774794
Short name T664
Test name
Test status
Simulation time 659286477 ps
CPU time 10.56 seconds
Started Jul 23 04:50:32 PM PDT 24
Finished Jul 23 04:50:59 PM PDT 24
Peak memory 248440 kb
Host smart-330ebae5-a746-4af4-b8e8-b0f0d549f833
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2774774794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.2774774794
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.518106227
Short name T648
Test name
Test status
Simulation time 8136422628 ps
CPU time 120.92 seconds
Started Jul 23 04:50:31 PM PDT 24
Finished Jul 23 04:52:49 PM PDT 24
Peak memory 256152 kb
Host smart-230a012f-dbda-4b56-b2fa-5ae02bc31720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51810
6227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.518106227
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.233092463
Short name T91
Test name
Test status
Simulation time 760666270 ps
CPU time 42.19 seconds
Started Jul 23 04:50:23 PM PDT 24
Finished Jul 23 04:51:19 PM PDT 24
Peak memory 248412 kb
Host smart-5617aea5-096f-414c-b6cb-88ef411af7f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23309
2463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.233092463
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3104639878
Short name T337
Test name
Test status
Simulation time 12052937593 ps
CPU time 877.66 seconds
Started Jul 23 04:50:32 PM PDT 24
Finished Jul 23 05:05:27 PM PDT 24
Peak memory 272836 kb
Host smart-7d7b07d8-4c0d-4b7c-8273-2b8bdd737ac3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104639878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3104639878
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.397144556
Short name T684
Test name
Test status
Simulation time 44285808232 ps
CPU time 1757.94 seconds
Started Jul 23 04:50:33 PM PDT 24
Finished Jul 23 05:20:07 PM PDT 24
Peak memory 289116 kb
Host smart-19eb93e0-2fd3-4ed3-9d13-0f87a909dd66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397144556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.397144556
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.4255846359
Short name T320
Test name
Test status
Simulation time 12454959064 ps
CPU time 479.3 seconds
Started Jul 23 04:50:23 PM PDT 24
Finished Jul 23 04:58:36 PM PDT 24
Peak memory 248672 kb
Host smart-4bae2fd2-ff1b-4a3a-8f70-b5ae5ae29683
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255846359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.4255846359
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3232018193
Short name T483
Test name
Test status
Simulation time 41599904 ps
CPU time 6.91 seconds
Started Jul 23 04:50:31 PM PDT 24
Finished Jul 23 04:50:55 PM PDT 24
Peak memory 254272 kb
Host smart-c9bf4878-1755-4593-ae21-bc555acce80b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32320
18193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3232018193
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.3670853300
Short name T391
Test name
Test status
Simulation time 4226744325 ps
CPU time 44.43 seconds
Started Jul 23 04:50:31 PM PDT 24
Finished Jul 23 04:51:33 PM PDT 24
Peak memory 255932 kb
Host smart-0685e56b-f864-410f-af37-bd0d1d2fe772
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36708
53300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3670853300
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.1459899383
Short name T511
Test name
Test status
Simulation time 247891745 ps
CPU time 25.9 seconds
Started Jul 23 04:50:23 PM PDT 24
Finished Jul 23 04:51:04 PM PDT 24
Peak memory 256608 kb
Host smart-12af7762-f1dc-47fb-873f-3c42714633dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14598
99383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.1459899383
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3179915805
Short name T656
Test name
Test status
Simulation time 1824090168 ps
CPU time 7.93 seconds
Started Jul 23 04:50:24 PM PDT 24
Finished Jul 23 04:50:46 PM PDT 24
Peak memory 251596 kb
Host smart-fc3faf14-5684-4b21-93d9-f1b373d35d27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31799
15805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3179915805
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2309602447
Short name T251
Test name
Test status
Simulation time 14054165647 ps
CPU time 1358.28 seconds
Started Jul 23 04:50:25 PM PDT 24
Finished Jul 23 05:13:18 PM PDT 24
Peak memory 289656 kb
Host smart-e6f00623-2ae2-430a-97b3-05596981f9d4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309602447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2309602447
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.637571059
Short name T207
Test name
Test status
Simulation time 453875468 ps
CPU time 3.95 seconds
Started Jul 23 04:50:36 PM PDT 24
Finished Jul 23 04:50:57 PM PDT 24
Peak memory 248804 kb
Host smart-0f9ddc30-e1af-4dbe-91ce-71fe602fbc21
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=637571059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.637571059
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.2344216983
Short name T708
Test name
Test status
Simulation time 6871657410 ps
CPU time 758.2 seconds
Started Jul 23 04:50:23 PM PDT 24
Finished Jul 23 05:03:15 PM PDT 24
Peak memory 273132 kb
Host smart-db923849-0823-490c-ba3e-0958136cd824
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344216983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2344216983
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2459366847
Short name T381
Test name
Test status
Simulation time 1572663737 ps
CPU time 34.05 seconds
Started Jul 23 04:50:31 PM PDT 24
Finished Jul 23 04:51:22 PM PDT 24
Peak memory 248508 kb
Host smart-ed9ac0c4-3a87-4969-ba27-8e2eb2dd18fd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2459366847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2459366847
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.3554956348
Short name T551
Test name
Test status
Simulation time 2783355778 ps
CPU time 145.11 seconds
Started Jul 23 04:50:24 PM PDT 24
Finished Jul 23 04:53:04 PM PDT 24
Peak memory 256244 kb
Host smart-1ff3daee-4543-4cc7-ab59-593b7b15e836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35549
56348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.3554956348
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.79166417
Short name T691
Test name
Test status
Simulation time 1708209472 ps
CPU time 17.51 seconds
Started Jul 23 04:50:24 PM PDT 24
Finished Jul 23 04:50:57 PM PDT 24
Peak memory 248256 kb
Host smart-40e5d1ba-db51-456c-8789-d16317026cf7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79166
417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.79166417
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.484571508
Short name T234
Test name
Test status
Simulation time 64976467415 ps
CPU time 1191.89 seconds
Started Jul 23 04:50:24 PM PDT 24
Finished Jul 23 05:10:31 PM PDT 24
Peak memory 282448 kb
Host smart-d169c8eb-2efd-419d-82de-93444f59baa4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484571508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.484571508
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.2631195734
Short name T673
Test name
Test status
Simulation time 69792284139 ps
CPU time 1231.44 seconds
Started Jul 23 04:50:26 PM PDT 24
Finished Jul 23 05:11:12 PM PDT 24
Peak memory 288572 kb
Host smart-dd5946be-1e7d-429d-8593-9c0f239e83a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631195734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.2631195734
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3193026783
Short name T82
Test name
Test status
Simulation time 2991729974 ps
CPU time 117.92 seconds
Started Jul 23 04:50:32 PM PDT 24
Finished Jul 23 04:52:47 PM PDT 24
Peak memory 255816 kb
Host smart-a1951def-e554-47d6-81f5-8f639e2b8841
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193026783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3193026783
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2275675635
Short name T43
Test name
Test status
Simulation time 1573388900 ps
CPU time 47.34 seconds
Started Jul 23 04:50:25 PM PDT 24
Finished Jul 23 04:51:27 PM PDT 24
Peak memory 257016 kb
Host smart-75a12bc5-cd11-41f9-b321-d075f399536f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22756
75635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2275675635
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.1059548939
Short name T45
Test name
Test status
Simulation time 1770338101 ps
CPU time 20.43 seconds
Started Jul 23 04:50:23 PM PDT 24
Finished Jul 23 04:50:58 PM PDT 24
Peak memory 256596 kb
Host smart-78653087-b527-4b93-b9d2-c9b423a3f8f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10595
48939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.1059548939
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1992240758
Short name T378
Test name
Test status
Simulation time 41727231 ps
CPU time 4.85 seconds
Started Jul 23 04:50:25 PM PDT 24
Finished Jul 23 04:50:44 PM PDT 24
Peak memory 248052 kb
Host smart-414ec87b-b1c1-45e2-86f7-a910cc1e5101
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19922
40758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1992240758
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3225910651
Short name T397
Test name
Test status
Simulation time 551938745 ps
CPU time 35.89 seconds
Started Jul 23 04:50:23 PM PDT 24
Finished Jul 23 04:51:14 PM PDT 24
Peak memory 248472 kb
Host smart-2aa3b50e-6001-41de-b387-8e89fcf778f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32259
10651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3225910651
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1688755286
Short name T50
Test name
Test status
Simulation time 62411151612 ps
CPU time 3401.29 seconds
Started Jul 23 04:50:37 PM PDT 24
Finished Jul 23 05:47:35 PM PDT 24
Peak memory 300208 kb
Host smart-acced09e-0bbe-479f-a589-d8bdf11979b3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688755286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1688755286
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.2662339137
Short name T676
Test name
Test status
Simulation time 27179049588 ps
CPU time 1514.76 seconds
Started Jul 23 04:50:39 PM PDT 24
Finished Jul 23 05:16:10 PM PDT 24
Peak memory 281476 kb
Host smart-0b17a8a7-02a4-4562-8f26-215e97f97292
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662339137 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.2662339137
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.1436885292
Short name T202
Test name
Test status
Simulation time 45212293 ps
CPU time 2.6 seconds
Started Jul 23 04:50:33 PM PDT 24
Finished Jul 23 04:50:52 PM PDT 24
Peak memory 248924 kb
Host smart-f432c321-9ad3-4d4f-bd6d-08b3c25db0bf
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1436885292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1436885292
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3604990208
Short name T594
Test name
Test status
Simulation time 12995260827 ps
CPU time 1098.04 seconds
Started Jul 23 04:50:35 PM PDT 24
Finished Jul 23 05:09:10 PM PDT 24
Peak memory 285280 kb
Host smart-0f0c5eb2-c760-451d-8ee3-6a2077974846
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604990208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3604990208
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1877371860
Short name T682
Test name
Test status
Simulation time 12893269662 ps
CPU time 52.73 seconds
Started Jul 23 04:50:33 PM PDT 24
Finished Jul 23 04:51:42 PM PDT 24
Peak memory 248612 kb
Host smart-c3c82483-aa00-479d-b985-cc6dc9780ced
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1877371860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1877371860
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1116008223
Short name T404
Test name
Test status
Simulation time 4359357005 ps
CPU time 256.36 seconds
Started Jul 23 04:50:31 PM PDT 24
Finished Jul 23 04:55:05 PM PDT 24
Peak memory 255984 kb
Host smart-6ccd88ce-0fe1-454f-b6e5-26e8f6e8c8fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11160
08223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1116008223
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1804184042
Short name T572
Test name
Test status
Simulation time 1279749189 ps
CPU time 33.78 seconds
Started Jul 23 04:50:33 PM PDT 24
Finished Jul 23 04:51:23 PM PDT 24
Peak memory 248448 kb
Host smart-46c48398-85d5-411b-80cc-3b2f6f718915
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18041
84042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1804184042
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.4001195514
Short name T339
Test name
Test status
Simulation time 180138823804 ps
CPU time 2221.85 seconds
Started Jul 23 04:50:38 PM PDT 24
Finished Jul 23 05:27:57 PM PDT 24
Peak memory 272324 kb
Host smart-7db1adc5-eb19-42b6-b8fb-931e2b27827c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001195514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.4001195514
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2288519767
Short name T485
Test name
Test status
Simulation time 337978102328 ps
CPU time 1989.15 seconds
Started Jul 23 04:50:40 PM PDT 24
Finished Jul 23 05:24:07 PM PDT 24
Peak memory 284496 kb
Host smart-e2bfe14f-84cd-481b-91f2-9ddfbb20a272
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288519767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2288519767
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3296641508
Short name T313
Test name
Test status
Simulation time 15966453244 ps
CPU time 335.49 seconds
Started Jul 23 04:50:37 PM PDT 24
Finished Jul 23 04:56:29 PM PDT 24
Peak memory 248592 kb
Host smart-b17351fe-7c09-4a6e-8693-0db57f71a22e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296641508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3296641508
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.2508635563
Short name T496
Test name
Test status
Simulation time 751914819 ps
CPU time 17.6 seconds
Started Jul 23 04:50:37 PM PDT 24
Finished Jul 23 04:51:11 PM PDT 24
Peak memory 255772 kb
Host smart-65e981f0-3d51-4579-a792-253456a4249b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25086
35563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.2508635563
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3408764209
Short name T568
Test name
Test status
Simulation time 1320836093 ps
CPU time 50.42 seconds
Started Jul 23 04:50:37 PM PDT 24
Finished Jul 23 04:51:44 PM PDT 24
Peak memory 256016 kb
Host smart-21b022ab-19c5-459d-bf3f-f74342e62b50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34087
64209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3408764209
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1871795547
Short name T460
Test name
Test status
Simulation time 773999758 ps
CPU time 41.95 seconds
Started Jul 23 04:50:34 PM PDT 24
Finished Jul 23 04:51:33 PM PDT 24
Peak memory 248008 kb
Host smart-9d4604f1-b234-4c3b-8ead-6d1f1b099896
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18717
95547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1871795547
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1617378212
Short name T440
Test name
Test status
Simulation time 342211167 ps
CPU time 23.05 seconds
Started Jul 23 04:50:38 PM PDT 24
Finished Jul 23 04:51:17 PM PDT 24
Peak memory 256544 kb
Host smart-4b62beca-cc76-4f42-b2ed-448a2a62fc61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16173
78212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1617378212
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.1243549588
Short name T244
Test name
Test status
Simulation time 55374917226 ps
CPU time 3814.29 seconds
Started Jul 23 04:50:31 PM PDT 24
Finished Jul 23 05:54:23 PM PDT 24
Peak memory 297968 kb
Host smart-411fca3b-d0e6-40f8-9222-9eb1f92d0cad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243549588 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.1243549588
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.1544852572
Short name T204
Test name
Test status
Simulation time 24059274 ps
CPU time 2.38 seconds
Started Jul 23 04:50:35 PM PDT 24
Finished Jul 23 04:50:54 PM PDT 24
Peak memory 248888 kb
Host smart-b82435ae-d0f5-41a4-bd94-0d588bb3fbf3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1544852572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.1544852572
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1298714756
Short name T608
Test name
Test status
Simulation time 103392791102 ps
CPU time 3085.39 seconds
Started Jul 23 04:50:38 PM PDT 24
Finished Jul 23 05:42:20 PM PDT 24
Peak memory 289368 kb
Host smart-cfef4fdc-3d9f-4afe-8a0f-ea13deff8011
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298714756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1298714756
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1422649897
Short name T7
Test name
Test status
Simulation time 2766115028 ps
CPU time 17.58 seconds
Started Jul 23 04:50:31 PM PDT 24
Finished Jul 23 04:51:06 PM PDT 24
Peak memory 248648 kb
Host smart-499b3fea-bd21-428d-b6ab-585f92188461
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1422649897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1422649897
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.997950175
Short name T589
Test name
Test status
Simulation time 4264385853 ps
CPU time 112.27 seconds
Started Jul 23 04:50:40 PM PDT 24
Finished Jul 23 04:52:50 PM PDT 24
Peak memory 256888 kb
Host smart-aeac1b1a-de83-4309-a0f5-52b89832213b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99795
0175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.997950175
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2688030845
Short name T560
Test name
Test status
Simulation time 3110309580 ps
CPU time 50.27 seconds
Started Jul 23 04:50:30 PM PDT 24
Finished Jul 23 04:51:36 PM PDT 24
Peak memory 256352 kb
Host smart-d0ae92c0-a322-4216-9e9b-8cc7378dcabf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26880
30845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2688030845
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3740432297
Short name T11
Test name
Test status
Simulation time 24653589220 ps
CPU time 1253.24 seconds
Started Jul 23 04:50:34 PM PDT 24
Finished Jul 23 05:11:44 PM PDT 24
Peak memory 287264 kb
Host smart-957c97c5-97d8-4b65-8a47-b10e3314d2a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740432297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3740432297
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1781692038
Short name T221
Test name
Test status
Simulation time 18794476169 ps
CPU time 362.36 seconds
Started Jul 23 04:50:31 PM PDT 24
Finished Jul 23 04:56:51 PM PDT 24
Peak memory 256468 kb
Host smart-fbe6db6f-50cf-43a1-b405-b9a674e56ffe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781692038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1781692038
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.3996103710
Short name T512
Test name
Test status
Simulation time 156637583 ps
CPU time 8.27 seconds
Started Jul 23 04:50:39 PM PDT 24
Finished Jul 23 04:51:04 PM PDT 24
Peak memory 248512 kb
Host smart-ccf3a728-2a9a-4981-b900-737808a1f9a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39961
03710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.3996103710
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2983738491
Short name T465
Test name
Test status
Simulation time 352404842 ps
CPU time 7.2 seconds
Started Jul 23 04:50:31 PM PDT 24
Finished Jul 23 04:50:56 PM PDT 24
Peak memory 248156 kb
Host smart-4857df8e-e3c6-43d0-9c39-4a4604608673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29837
38491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2983738491
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.378075915
Short name T590
Test name
Test status
Simulation time 548498779 ps
CPU time 39.35 seconds
Started Jul 23 04:50:34 PM PDT 24
Finished Jul 23 04:51:31 PM PDT 24
Peak memory 247932 kb
Host smart-ee40e531-072a-4495-bdd1-b2c92a691179
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37807
5915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.378075915
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.891623543
Short name T365
Test name
Test status
Simulation time 928537099 ps
CPU time 59.14 seconds
Started Jul 23 04:50:31 PM PDT 24
Finished Jul 23 04:51:47 PM PDT 24
Peak memory 256720 kb
Host smart-28f605dc-ae98-4e50-b6f7-302973978bcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89162
3543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.891623543
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.920126322
Short name T566
Test name
Test status
Simulation time 36581689181 ps
CPU time 1173.02 seconds
Started Jul 23 04:50:40 PM PDT 24
Finished Jul 23 05:10:31 PM PDT 24
Peak memory 272064 kb
Host smart-f9b2e64c-799d-483f-903a-7f858c3c6996
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920126322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_han
dler_stress_all.920126322
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.348153707
Short name T200
Test name
Test status
Simulation time 183475501 ps
CPU time 5.06 seconds
Started Jul 23 04:50:33 PM PDT 24
Finished Jul 23 04:50:54 PM PDT 24
Peak memory 248892 kb
Host smart-f7dd8ba4-66e6-406a-8554-ed5bf2a2e720
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=348153707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.348153707
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.1642409391
Short name T419
Test name
Test status
Simulation time 713596941621 ps
CPU time 2052.24 seconds
Started Jul 23 04:50:31 PM PDT 24
Finished Jul 23 05:25:01 PM PDT 24
Peak memory 282016 kb
Host smart-a504ac10-c3d4-410b-9cdb-ccc5aed9aa4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642409391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.1642409391
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.2663767848
Short name T600
Test name
Test status
Simulation time 6716394971 ps
CPU time 68.23 seconds
Started Jul 23 04:50:32 PM PDT 24
Finished Jul 23 04:51:57 PM PDT 24
Peak memory 248612 kb
Host smart-cc27db09-ace1-4953-bdeb-ca9fb19abfa5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2663767848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.2663767848
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.722870103
Short name T228
Test name
Test status
Simulation time 2529663486 ps
CPU time 135.53 seconds
Started Jul 23 04:50:39 PM PDT 24
Finished Jul 23 04:53:11 PM PDT 24
Peak memory 256328 kb
Host smart-345f118e-0599-476f-9121-0bb0a6011abf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72287
0103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.722870103
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1021053618
Short name T425
Test name
Test status
Simulation time 1939073870 ps
CPU time 40.12 seconds
Started Jul 23 04:50:34 PM PDT 24
Finished Jul 23 04:51:30 PM PDT 24
Peak memory 255928 kb
Host smart-6c0d47fa-4faf-4eb9-86d0-bc7fe3f5f39e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10210
53618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1021053618
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.3406882811
Short name T701
Test name
Test status
Simulation time 33525496004 ps
CPU time 176.78 seconds
Started Jul 23 04:50:40 PM PDT 24
Finished Jul 23 04:53:54 PM PDT 24
Peak memory 248680 kb
Host smart-80b3d734-772b-4442-8e18-32189ed04209
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406882811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.3406882811
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3818014327
Short name T711
Test name
Test status
Simulation time 1845074833 ps
CPU time 34.25 seconds
Started Jul 23 04:50:35 PM PDT 24
Finished Jul 23 04:51:27 PM PDT 24
Peak memory 256128 kb
Host smart-819d1582-ff5d-4fdb-85f4-c10a575cb74c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38180
14327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3818014327
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.101605563
Short name T431
Test name
Test status
Simulation time 420979308 ps
CPU time 9.89 seconds
Started Jul 23 04:50:33 PM PDT 24
Finished Jul 23 04:50:59 PM PDT 24
Peak memory 256280 kb
Host smart-3b24f6ea-00c4-4474-80d0-d3e400525354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10160
5563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.101605563
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.2829563516
Short name T591
Test name
Test status
Simulation time 3062871859 ps
CPU time 28.84 seconds
Started Jul 23 04:50:31 PM PDT 24
Finished Jul 23 04:51:17 PM PDT 24
Peak memory 249092 kb
Host smart-b8c7a5ec-929a-49eb-a673-21686dbb1b92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28295
63516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2829563516
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.727958328
Short name T663
Test name
Test status
Simulation time 474187758 ps
CPU time 22.25 seconds
Started Jul 23 04:50:34 PM PDT 24
Finished Jul 23 04:51:13 PM PDT 24
Peak memory 256748 kb
Host smart-1b1c183f-6372-497b-8934-30d16d74c699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72795
8328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.727958328
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2409764571
Short name T535
Test name
Test status
Simulation time 60686714105 ps
CPU time 1355.99 seconds
Started Jul 23 04:50:36 PM PDT 24
Finished Jul 23 05:13:29 PM PDT 24
Peak memory 288472 kb
Host smart-967f4805-3ff2-4017-b6a8-f1a8a635177a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409764571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2409764571
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.396092933
Short name T195
Test name
Test status
Simulation time 186694830 ps
CPU time 3.41 seconds
Started Jul 23 04:50:32 PM PDT 24
Finished Jul 23 04:50:52 PM PDT 24
Peak memory 249144 kb
Host smart-4558a6a4-3884-4142-9452-8cf1a54ff7e0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=396092933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.396092933
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2603314546
Short name T547
Test name
Test status
Simulation time 27285127258 ps
CPU time 1607.62 seconds
Started Jul 23 04:50:37 PM PDT 24
Finished Jul 23 05:17:41 PM PDT 24
Peak memory 272784 kb
Host smart-0af8c2e7-eba3-4347-9822-a8d9c6b51dbe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603314546 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2603314546
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1878203766
Short name T222
Test name
Test status
Simulation time 421181558 ps
CPU time 7.26 seconds
Started Jul 23 04:50:39 PM PDT 24
Finished Jul 23 04:51:03 PM PDT 24
Peak memory 248440 kb
Host smart-36d324be-e22b-4957-8b94-c1e37428500b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1878203766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1878203766
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3962443074
Short name T467
Test name
Test status
Simulation time 6826946702 ps
CPU time 217.29 seconds
Started Jul 23 04:50:36 PM PDT 24
Finished Jul 23 04:54:31 PM PDT 24
Peak memory 256788 kb
Host smart-1b4dd6bd-9a4b-42e3-815c-ec541cae0ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39624
43074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3962443074
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.455397195
Short name T23
Test name
Test status
Simulation time 4013174480 ps
CPU time 56.86 seconds
Started Jul 23 04:50:38 PM PDT 24
Finished Jul 23 04:51:52 PM PDT 24
Peak memory 248536 kb
Host smart-ec6c41c1-c249-4925-b9f0-3e1e0b0cb55b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45539
7195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.455397195
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2749288467
Short name T66
Test name
Test status
Simulation time 227908361129 ps
CPU time 3066.28 seconds
Started Jul 23 04:50:33 PM PDT 24
Finished Jul 23 05:41:56 PM PDT 24
Peak memory 289088 kb
Host smart-ab61bed4-9e37-44d2-91ba-5303e124a75f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749288467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2749288467
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.476001536
Short name T219
Test name
Test status
Simulation time 4225552751 ps
CPU time 55.83 seconds
Started Jul 23 04:50:37 PM PDT 24
Finished Jul 23 04:51:49 PM PDT 24
Peak memory 256352 kb
Host smart-de6f16a5-1406-4d98-bd8e-8db610fa5dd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47600
1536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.476001536
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.2222532297
Short name T710
Test name
Test status
Simulation time 51285970 ps
CPU time 6.92 seconds
Started Jul 23 04:50:40 PM PDT 24
Finished Jul 23 04:51:05 PM PDT 24
Peak memory 254416 kb
Host smart-5da0e5c0-0c70-4a18-8607-7da9b4b17e26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22225
32297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2222532297
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.3494230959
Short name T292
Test name
Test status
Simulation time 651707926 ps
CPU time 42.66 seconds
Started Jul 23 04:50:37 PM PDT 24
Finished Jul 23 04:51:36 PM PDT 24
Peak memory 255964 kb
Host smart-9534fc28-14f3-4cae-8337-5bfad298ac2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34942
30959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.3494230959
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.38710048
Short name T506
Test name
Test status
Simulation time 7877266720 ps
CPU time 38.5 seconds
Started Jul 23 04:50:36 PM PDT 24
Finished Jul 23 04:51:31 PM PDT 24
Peak memory 248900 kb
Host smart-1ac96460-39d9-47fe-806b-8421e3078ab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38710
048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.38710048
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1423250047
Short name T208
Test name
Test status
Simulation time 59514142 ps
CPU time 4.33 seconds
Started Jul 23 04:50:42 PM PDT 24
Finished Jul 23 04:51:03 PM PDT 24
Peak memory 248924 kb
Host smart-a3e83242-f813-4375-b2cd-fd9dc62ad149
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1423250047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1423250047
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.1993291229
Short name T587
Test name
Test status
Simulation time 77178866669 ps
CPU time 1608.45 seconds
Started Jul 23 04:50:40 PM PDT 24
Finished Jul 23 05:17:46 PM PDT 24
Peak memory 288856 kb
Host smart-608afb6f-364c-4c7a-9bc0-4234fbc00779
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993291229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1993291229
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.2871173112
Short name T94
Test name
Test status
Simulation time 217688038 ps
CPU time 13.5 seconds
Started Jul 23 04:50:43 PM PDT 24
Finished Jul 23 04:51:13 PM PDT 24
Peak memory 248440 kb
Host smart-d839f165-2223-491a-8bde-c5058e9129aa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2871173112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.2871173112
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.3991505954
Short name T363
Test name
Test status
Simulation time 1196350806 ps
CPU time 22.45 seconds
Started Jul 23 04:50:41 PM PDT 24
Finished Jul 23 04:51:21 PM PDT 24
Peak memory 256356 kb
Host smart-d86a1fcd-b8e2-4295-84ca-203491b6149b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39915
05954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.3991505954
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2773475278
Short name T693
Test name
Test status
Simulation time 104173374 ps
CPU time 6.87 seconds
Started Jul 23 04:50:41 PM PDT 24
Finished Jul 23 04:51:05 PM PDT 24
Peak memory 251564 kb
Host smart-239fa438-9052-4a07-844a-a4f76dad01e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27734
75278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2773475278
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.228729962
Short name T344
Test name
Test status
Simulation time 37343265476 ps
CPU time 2190.26 seconds
Started Jul 23 04:50:41 PM PDT 24
Finished Jul 23 05:27:29 PM PDT 24
Peak memory 273116 kb
Host smart-c0a733dd-92cb-405f-a139-784bab964654
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228729962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.228729962
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.3643547633
Short name T412
Test name
Test status
Simulation time 35934985240 ps
CPU time 2018.72 seconds
Started Jul 23 04:50:40 PM PDT 24
Finished Jul 23 05:24:37 PM PDT 24
Peak memory 272632 kb
Host smart-1b3afa68-f65f-479b-99ee-4a1537e975e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643547633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3643547633
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3770384256
Short name T705
Test name
Test status
Simulation time 35956990622 ps
CPU time 344.89 seconds
Started Jul 23 04:50:42 PM PDT 24
Finished Jul 23 04:56:44 PM PDT 24
Peak memory 248432 kb
Host smart-11069604-47a0-4474-8ae1-cdf58ac95287
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770384256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3770384256
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.895495072
Short name T37
Test name
Test status
Simulation time 78832796 ps
CPU time 8.49 seconds
Started Jul 23 04:50:39 PM PDT 24
Finished Jul 23 04:51:04 PM PDT 24
Peak memory 248612 kb
Host smart-aacd6cb4-b066-4957-9827-77516c3677f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89549
5072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.895495072
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3824932957
Short name T585
Test name
Test status
Simulation time 2453228912 ps
CPU time 56.79 seconds
Started Jul 23 04:50:41 PM PDT 24
Finished Jul 23 04:51:55 PM PDT 24
Peak memory 249260 kb
Host smart-3b84803a-c52e-41af-8f91-1f2e237864fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38249
32957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3824932957
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2567275003
Short name T586
Test name
Test status
Simulation time 19345425 ps
CPU time 2.97 seconds
Started Jul 23 04:50:39 PM PDT 24
Finished Jul 23 04:50:59 PM PDT 24
Peak memory 239928 kb
Host smart-167b4a55-08bc-4125-a184-93068de7b4d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25672
75003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2567275003
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.4291511413
Short name T609
Test name
Test status
Simulation time 202596230 ps
CPU time 19.88 seconds
Started Jul 23 04:50:32 PM PDT 24
Finished Jul 23 04:51:09 PM PDT 24
Peak memory 256664 kb
Host smart-3d18ada4-aceb-4c40-96a7-b72fa17f5def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42915
11413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.4291511413
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1961314284
Short name T206
Test name
Test status
Simulation time 502803406 ps
CPU time 3.83 seconds
Started Jul 23 04:49:56 PM PDT 24
Finished Jul 23 04:50:03 PM PDT 24
Peak memory 248824 kb
Host smart-01b95d67-68bf-4f2f-929e-e5ca51747bd9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1961314284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1961314284
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2636152023
Short name T462
Test name
Test status
Simulation time 100490079181 ps
CPU time 2051.37 seconds
Started Jul 23 04:50:00 PM PDT 24
Finished Jul 23 05:24:15 PM PDT 24
Peak memory 285480 kb
Host smart-617555a5-7e41-4954-ab53-cd9ba930255c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636152023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2636152023
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.3526828407
Short name T698
Test name
Test status
Simulation time 7705144591 ps
CPU time 79.79 seconds
Started Jul 23 04:49:57 PM PDT 24
Finished Jul 23 04:51:20 PM PDT 24
Peak memory 248572 kb
Host smart-28fbcd57-e0a9-4da3-b20e-b2012082024c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3526828407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3526828407
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.2879635663
Short name T622
Test name
Test status
Simulation time 20858426693 ps
CPU time 262.59 seconds
Started Jul 23 04:50:00 PM PDT 24
Finished Jul 23 04:54:26 PM PDT 24
Peak memory 250988 kb
Host smart-572d3538-5e01-43b2-a18a-bdcf7e016056
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28796
35663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.2879635663
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.3788290991
Short name T238
Test name
Test status
Simulation time 5425909081 ps
CPU time 37.74 seconds
Started Jul 23 04:49:56 PM PDT 24
Finished Jul 23 04:50:38 PM PDT 24
Peak memory 256496 kb
Host smart-6f3f2212-a68d-4f8f-b08e-5f2125e24656
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37882
90991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.3788290991
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1051673982
Short name T330
Test name
Test status
Simulation time 71405216643 ps
CPU time 1718.27 seconds
Started Jul 23 04:49:59 PM PDT 24
Finished Jul 23 05:18:42 PM PDT 24
Peak memory 289536 kb
Host smart-c378662a-1688-440a-b974-047fadfc0733
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051673982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1051673982
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1497390903
Short name T494
Test name
Test status
Simulation time 77644789358 ps
CPU time 2332.35 seconds
Started Jul 23 04:49:58 PM PDT 24
Finished Jul 23 05:28:55 PM PDT 24
Peak memory 282344 kb
Host smart-0c69c534-10c7-45d3-98c8-87093c62dda5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497390903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1497390903
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.1017698034
Short name T302
Test name
Test status
Simulation time 3496229005 ps
CPU time 148.47 seconds
Started Jul 23 04:49:58 PM PDT 24
Finished Jul 23 04:52:30 PM PDT 24
Peak memory 254412 kb
Host smart-f6b913ba-dbab-45b8-9c2f-74c2ca9bc281
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017698034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1017698034
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.3042465470
Short name T513
Test name
Test status
Simulation time 97532788 ps
CPU time 5.49 seconds
Started Jul 23 04:49:56 PM PDT 24
Finished Jul 23 04:50:04 PM PDT 24
Peak memory 240260 kb
Host smart-a7417244-f79f-4510-a37a-fb056603a07f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30424
65470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3042465470
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1794526876
Short name T31
Test name
Test status
Simulation time 1186493894 ps
CPU time 27.53 seconds
Started Jul 23 04:49:57 PM PDT 24
Finished Jul 23 04:50:29 PM PDT 24
Peak memory 256732 kb
Host smart-751d69d7-3466-434a-8e9e-fabd84c6e9c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17945
26876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1794526876
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.1759507622
Short name T36
Test name
Test status
Simulation time 577970342 ps
CPU time 18.64 seconds
Started Jul 23 04:49:57 PM PDT 24
Finished Jul 23 04:50:20 PM PDT 24
Peak memory 270672 kb
Host smart-0cee2262-2e00-43fb-b44b-ef26f3a4e69a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1759507622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.1759507622
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.101647409
Short name T48
Test name
Test status
Simulation time 2043750156 ps
CPU time 62.16 seconds
Started Jul 23 04:49:58 PM PDT 24
Finished Jul 23 04:51:05 PM PDT 24
Peak memory 248552 kb
Host smart-ebeec7e4-6270-4a99-8838-8fc3e76729e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10164
7409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.101647409
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2098800033
Short name T580
Test name
Test status
Simulation time 516139865 ps
CPU time 26.48 seconds
Started Jul 23 04:49:58 PM PDT 24
Finished Jul 23 04:50:29 PM PDT 24
Peak memory 256716 kb
Host smart-4c8ee89f-5bab-4bb9-ab1f-02a038cd02f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20988
00033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2098800033
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2694833430
Short name T502
Test name
Test status
Simulation time 26470531547 ps
CPU time 1712.64 seconds
Started Jul 23 04:49:57 PM PDT 24
Finished Jul 23 05:18:34 PM PDT 24
Peak memory 282692 kb
Host smart-82673992-b788-42e2-9381-8a134cafd67b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694833430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2694833430
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.605799224
Short name T273
Test name
Test status
Simulation time 132918856137 ps
CPU time 1594.73 seconds
Started Jul 23 04:50:40 PM PDT 24
Finished Jul 23 05:17:32 PM PDT 24
Peak memory 273128 kb
Host smart-5064f8f2-8662-4292-96f3-9998b0a93ba8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605799224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.605799224
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1585415611
Short name T437
Test name
Test status
Simulation time 4421736150 ps
CPU time 87.4 seconds
Started Jul 23 04:50:39 PM PDT 24
Finished Jul 23 04:52:24 PM PDT 24
Peak memory 256052 kb
Host smart-39103279-3ccb-42b8-9ca7-1ea6671e8a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15854
15611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1585415611
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.1869596852
Short name T627
Test name
Test status
Simulation time 374813627 ps
CPU time 8.83 seconds
Started Jul 23 04:50:39 PM PDT 24
Finished Jul 23 04:51:05 PM PDT 24
Peak memory 254184 kb
Host smart-6abd909e-92f0-43cf-bacb-f2f6c6ad9c43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18695
96852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1869596852
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.4254824301
Short name T342
Test name
Test status
Simulation time 76103845440 ps
CPU time 2319.71 seconds
Started Jul 23 04:50:41 PM PDT 24
Finished Jul 23 05:29:39 PM PDT 24
Peak memory 281376 kb
Host smart-5eab9139-2a6e-4302-a21e-530b666a273e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254824301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.4254824301
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2131765364
Short name T260
Test name
Test status
Simulation time 139454988521 ps
CPU time 2086.27 seconds
Started Jul 23 04:50:39 PM PDT 24
Finished Jul 23 05:25:42 PM PDT 24
Peak memory 273076 kb
Host smart-d379c582-0c87-4602-b105-de4a4be8f00b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131765364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2131765364
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.3832715268
Short name T452
Test name
Test status
Simulation time 1662654255 ps
CPU time 32.57 seconds
Started Jul 23 04:50:40 PM PDT 24
Finished Jul 23 04:51:30 PM PDT 24
Peak memory 256048 kb
Host smart-b964b99d-1a1f-4d61-81be-3b2d434acc2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38327
15268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.3832715268
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1208563823
Short name T285
Test name
Test status
Simulation time 1972133425 ps
CPU time 64.34 seconds
Started Jul 23 04:50:40 PM PDT 24
Finished Jul 23 04:52:02 PM PDT 24
Peak memory 248188 kb
Host smart-75e7c1f3-2664-4d1a-b904-cb48e7bbc8e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12085
63823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1208563823
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.467242334
Short name T264
Test name
Test status
Simulation time 379408105 ps
CPU time 13.68 seconds
Started Jul 23 04:50:41 PM PDT 24
Finished Jul 23 04:51:12 PM PDT 24
Peak memory 249008 kb
Host smart-4fb08f06-58a9-46de-8c3b-5e17cc9e7993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46724
2334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.467242334
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1203769072
Short name T700
Test name
Test status
Simulation time 116339593 ps
CPU time 12.26 seconds
Started Jul 23 04:50:40 PM PDT 24
Finished Jul 23 04:51:09 PM PDT 24
Peak memory 255112 kb
Host smart-4b0c9efc-d77a-4e8a-954e-d4aa7d8020ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12037
69072 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1203769072
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.18545519
Short name T56
Test name
Test status
Simulation time 107133322323 ps
CPU time 3149.52 seconds
Started Jul 23 04:50:40 PM PDT 24
Finished Jul 23 05:43:27 PM PDT 24
Peak memory 297792 kb
Host smart-f7196786-aa62-44c5-9a12-ff94768bfe0c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18545519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_hand
ler_stress_all.18545519
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.1809018429
Short name T29
Test name
Test status
Simulation time 10116460499 ps
CPU time 1048.02 seconds
Started Jul 23 04:50:39 PM PDT 24
Finished Jul 23 05:08:23 PM PDT 24
Peak memory 289736 kb
Host smart-892a6ca4-dc26-45aa-8181-bc641320425d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809018429 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.1809018429
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.186026446
Short name T416
Test name
Test status
Simulation time 81118567049 ps
CPU time 2567.32 seconds
Started Jul 23 04:50:38 PM PDT 24
Finished Jul 23 05:33:42 PM PDT 24
Peak memory 282220 kb
Host smart-c5c49e4c-ab0c-4dfc-8cb5-4dfde9b6d6a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186026446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.186026446
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.3714903405
Short name T556
Test name
Test status
Simulation time 1893259542 ps
CPU time 145.4 seconds
Started Jul 23 04:50:41 PM PDT 24
Finished Jul 23 04:53:24 PM PDT 24
Peak memory 256764 kb
Host smart-a0d851ff-4e08-4d40-ad90-2643fa1887d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37149
03405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.3714903405
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3985280217
Short name T474
Test name
Test status
Simulation time 5198424806 ps
CPU time 83.47 seconds
Started Jul 23 04:50:39 PM PDT 24
Finished Jul 23 04:52:20 PM PDT 24
Peak memory 256816 kb
Host smart-471281d8-866f-4845-b7a9-831f960a0a9f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39852
80217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3985280217
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3759083533
Short name T341
Test name
Test status
Simulation time 29007712886 ps
CPU time 731.1 seconds
Started Jul 23 04:50:39 PM PDT 24
Finished Jul 23 05:03:06 PM PDT 24
Peak memory 272952 kb
Host smart-8446a750-2491-49d8-94ea-75d6b63cea0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759083533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3759083533
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3918272124
Short name T413
Test name
Test status
Simulation time 37074569604 ps
CPU time 2368.68 seconds
Started Jul 23 04:50:41 PM PDT 24
Finished Jul 23 05:30:27 PM PDT 24
Peak memory 288836 kb
Host smart-eaae8ec1-e70c-4d6c-8555-58d70b906271
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918272124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3918272124
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.951248908
Short name T12
Test name
Test status
Simulation time 16760496451 ps
CPU time 387.83 seconds
Started Jul 23 04:50:42 PM PDT 24
Finished Jul 23 04:57:27 PM PDT 24
Peak memory 248432 kb
Host smart-877a91d5-30d9-4164-abe8-837ba344d35f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951248908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.951248908
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2530861360
Short name T667
Test name
Test status
Simulation time 2216822489 ps
CPU time 38.61 seconds
Started Jul 23 04:50:48 PM PDT 24
Finished Jul 23 04:51:41 PM PDT 24
Peak memory 248584 kb
Host smart-1d981584-f631-451e-8139-753e31d82afb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25308
61360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2530861360
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2161292076
Short name T575
Test name
Test status
Simulation time 42193891 ps
CPU time 4.86 seconds
Started Jul 23 04:50:39 PM PDT 24
Finished Jul 23 04:51:00 PM PDT 24
Peak memory 248060 kb
Host smart-6cf664e9-a412-46d7-8098-7cd62acabecb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21612
92076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2161292076
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3751273679
Short name T599
Test name
Test status
Simulation time 641324122 ps
CPU time 19.19 seconds
Started Jul 23 04:50:48 PM PDT 24
Finished Jul 23 04:51:21 PM PDT 24
Peak memory 247952 kb
Host smart-c9c69a1b-987b-4503-a913-72d2a1116f55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37512
73679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3751273679
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.1916053336
Short name T486
Test name
Test status
Simulation time 370872920 ps
CPU time 12.17 seconds
Started Jul 23 04:50:41 PM PDT 24
Finished Jul 23 04:51:11 PM PDT 24
Peak memory 255876 kb
Host smart-884ed043-e5cd-417d-bfbb-ffa88769ee4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19160
53336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1916053336
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.907494279
Short name T573
Test name
Test status
Simulation time 78278200243 ps
CPU time 818.73 seconds
Started Jul 23 04:50:38 PM PDT 24
Finished Jul 23 05:04:33 PM PDT 24
Peak memory 273128 kb
Host smart-236a7874-4da2-4d00-8ebb-5aa2c54fe8bd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907494279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_han
dler_stress_all.907494279
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.1865637768
Short name T240
Test name
Test status
Simulation time 12643311768 ps
CPU time 732.27 seconds
Started Jul 23 04:50:38 PM PDT 24
Finished Jul 23 05:03:07 PM PDT 24
Peak memory 269844 kb
Host smart-b74c67d3-7f34-4ff3-b38f-56135ebe0789
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865637768 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.1865637768
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.177133311
Short name T631
Test name
Test status
Simulation time 173336948897 ps
CPU time 2608.44 seconds
Started Jul 23 04:50:42 PM PDT 24
Finished Jul 23 05:34:28 PM PDT 24
Peak memory 284152 kb
Host smart-cbbc3f61-d731-4d24-904f-c65b0f7085c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177133311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.177133311
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.999771394
Short name T538
Test name
Test status
Simulation time 3029317119 ps
CPU time 87.73 seconds
Started Jul 23 04:50:48 PM PDT 24
Finished Jul 23 04:52:30 PM PDT 24
Peak memory 256384 kb
Host smart-37d95bcc-1cbe-4dad-91a3-ad02e5daf6d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99977
1394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.999771394
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.4158212329
Short name T69
Test name
Test status
Simulation time 4779966420 ps
CPU time 78.22 seconds
Started Jul 23 04:50:42 PM PDT 24
Finished Jul 23 04:52:17 PM PDT 24
Peak memory 248428 kb
Host smart-0289f174-bec6-41d4-b785-60342a3bafe0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41582
12329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.4158212329
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1577657695
Short name T576
Test name
Test status
Simulation time 16396809285 ps
CPU time 1291.72 seconds
Started Jul 23 04:50:41 PM PDT 24
Finished Jul 23 05:12:31 PM PDT 24
Peak memory 281380 kb
Host smart-836fdf86-b299-4d2a-af80-7b7902f4fc9a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577657695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1577657695
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.2147377164
Short name T453
Test name
Test status
Simulation time 457931188 ps
CPU time 15.37 seconds
Started Jul 23 04:50:42 PM PDT 24
Finished Jul 23 04:51:14 PM PDT 24
Peak memory 256584 kb
Host smart-656d8cb9-0be1-4e61-96d8-d25ae687fcad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21473
77164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.2147377164
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.627654386
Short name T62
Test name
Test status
Simulation time 705999586 ps
CPU time 15.45 seconds
Started Jul 23 04:50:39 PM PDT 24
Finished Jul 23 04:51:12 PM PDT 24
Peak memory 255596 kb
Host smart-9475fc40-26ae-42c3-ba0c-8ea918df6bb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62765
4386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.627654386
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.4141682894
Short name T364
Test name
Test status
Simulation time 418518868 ps
CPU time 16.13 seconds
Started Jul 23 04:50:44 PM PDT 24
Finished Jul 23 04:51:17 PM PDT 24
Peak memory 248828 kb
Host smart-7b239386-d781-493c-992b-9cc8e0d40982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41416
82894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.4141682894
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3245011050
Short name T79
Test name
Test status
Simulation time 33798569294 ps
CPU time 1692.1 seconds
Started Jul 23 04:50:48 PM PDT 24
Finished Jul 23 05:19:15 PM PDT 24
Peak memory 288824 kb
Host smart-fdb4bd0d-9892-4000-9e8f-370d9eadf018
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245011050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3245011050
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.3211297541
Short name T458
Test name
Test status
Simulation time 91893833514 ps
CPU time 1085.35 seconds
Started Jul 23 04:50:56 PM PDT 24
Finished Jul 23 05:09:11 PM PDT 24
Peak memory 288428 kb
Host smart-e110d8f9-6138-4738-b9cb-378adbc1990c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211297541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.3211297541
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1239809457
Short name T409
Test name
Test status
Simulation time 1744450062 ps
CPU time 88.25 seconds
Started Jul 23 04:50:50 PM PDT 24
Finished Jul 23 04:52:31 PM PDT 24
Peak memory 256132 kb
Host smart-f9cfda79-74b6-4a11-9cb8-a6f30cd24b27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12398
09457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1239809457
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.4162422586
Short name T21
Test name
Test status
Simulation time 1504635081 ps
CPU time 33.37 seconds
Started Jul 23 04:50:50 PM PDT 24
Finished Jul 23 04:51:36 PM PDT 24
Peak memory 248508 kb
Host smart-530b8a11-708b-412f-ae86-78fd32d4842f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41624
22586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.4162422586
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2593690881
Short name T550
Test name
Test status
Simulation time 38955635810 ps
CPU time 930.34 seconds
Started Jul 23 04:50:50 PM PDT 24
Finished Jul 23 05:06:33 PM PDT 24
Peak memory 272508 kb
Host smart-679e00d4-f4ad-4bed-853c-8f796cd729d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593690881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2593690881
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3930899557
Short name T604
Test name
Test status
Simulation time 8067070584 ps
CPU time 319.09 seconds
Started Jul 23 04:50:47 PM PDT 24
Finished Jul 23 04:56:21 PM PDT 24
Peak memory 248652 kb
Host smart-27117983-1328-48f3-accf-e011a53b8e03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3930899557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3930899557
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.4083959360
Short name T78
Test name
Test status
Simulation time 2313613295 ps
CPU time 19.67 seconds
Started Jul 23 04:50:47 PM PDT 24
Finished Jul 23 04:51:22 PM PDT 24
Peak memory 255544 kb
Host smart-04bb7638-63d8-41d5-942c-dc926cfb85db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40839
59360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.4083959360
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1136213951
Short name T65
Test name
Test status
Simulation time 800685306 ps
CPU time 36.75 seconds
Started Jul 23 04:50:57 PM PDT 24
Finished Jul 23 04:51:42 PM PDT 24
Peak memory 248332 kb
Host smart-8f93cb9f-6ba6-4ae4-a5c4-62dc5bfa6a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11362
13951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1136213951
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.1325677223
Short name T75
Test name
Test status
Simulation time 249453980 ps
CPU time 27.67 seconds
Started Jul 23 04:50:51 PM PDT 24
Finished Jul 23 04:51:31 PM PDT 24
Peak memory 248084 kb
Host smart-92c95135-8840-4ebc-8767-64768b3da6e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13256
77223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.1325677223
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.169194322
Short name T477
Test name
Test status
Simulation time 268382992 ps
CPU time 19.74 seconds
Started Jul 23 04:50:42 PM PDT 24
Finished Jul 23 04:51:19 PM PDT 24
Peak memory 255776 kb
Host smart-bf2c60c3-056a-4874-83df-43bf41d9df6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16919
4322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.169194322
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.937434223
Short name T445
Test name
Test status
Simulation time 25988236937 ps
CPU time 831.46 seconds
Started Jul 23 04:50:54 PM PDT 24
Finished Jul 23 05:04:56 PM PDT 24
Peak memory 272656 kb
Host smart-33f26a6d-9c68-4086-96b0-f9d7ee923ba5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937434223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_han
dler_stress_all.937434223
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.2982431743
Short name T668
Test name
Test status
Simulation time 454903807701 ps
CPU time 8611.14 seconds
Started Jul 23 04:50:52 PM PDT 24
Finished Jul 23 07:14:35 PM PDT 24
Peak memory 368148 kb
Host smart-cb165e4d-7884-4fa2-90b3-0e35f768ce9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982431743 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.2982431743
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1670621725
Short name T638
Test name
Test status
Simulation time 82528493522 ps
CPU time 1213.01 seconds
Started Jul 23 04:50:51 PM PDT 24
Finished Jul 23 05:11:16 PM PDT 24
Peak memory 273100 kb
Host smart-c8aea7c3-e94f-4cf5-9b0e-4f3fef2230fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1670621725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1670621725
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.1658965988
Short name T370
Test name
Test status
Simulation time 1134138959 ps
CPU time 47.27 seconds
Started Jul 23 04:50:50 PM PDT 24
Finished Jul 23 04:51:50 PM PDT 24
Peak memory 256636 kb
Host smart-505a9161-7dc0-49b2-99ad-a00091218838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16589
65988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.1658965988
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1688388324
Short name T321
Test name
Test status
Simulation time 15043349114 ps
CPU time 1423.24 seconds
Started Jul 23 04:50:50 PM PDT 24
Finished Jul 23 05:14:46 PM PDT 24
Peak memory 289588 kb
Host smart-ebc436f7-16a6-42e5-a2f3-e6a6234efe7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688388324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1688388324
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.103764046
Short name T704
Test name
Test status
Simulation time 41892688293 ps
CPU time 2569.85 seconds
Started Jul 23 04:50:47 PM PDT 24
Finished Jul 23 05:33:52 PM PDT 24
Peak memory 289316 kb
Host smart-76eeec7d-dca1-48e6-aa4e-b113a50d01e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103764046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.103764046
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.2019806474
Short name T482
Test name
Test status
Simulation time 227713605 ps
CPU time 22.22 seconds
Started Jul 23 04:50:51 PM PDT 24
Finished Jul 23 04:51:26 PM PDT 24
Peak memory 255832 kb
Host smart-e27b372e-e73b-4121-ba54-d82cbee14d03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20198
06474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2019806474
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.378865475
Short name T436
Test name
Test status
Simulation time 234490765 ps
CPU time 5.62 seconds
Started Jul 23 04:50:54 PM PDT 24
Finished Jul 23 04:51:09 PM PDT 24
Peak memory 240388 kb
Host smart-bbf9720f-bb41-4282-8c8f-fbc8612fcd42
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37886
5475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.378865475
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.804969872
Short name T688
Test name
Test status
Simulation time 1859469916 ps
CPU time 18.01 seconds
Started Jul 23 04:50:57 PM PDT 24
Finished Jul 23 04:51:24 PM PDT 24
Peak memory 248108 kb
Host smart-ea45ddba-634a-405b-80fa-f5eb2cdb20ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80496
9872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.804969872
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.881192076
Short name T390
Test name
Test status
Simulation time 11797164424 ps
CPU time 52.3 seconds
Started Jul 23 04:50:51 PM PDT 24
Finished Jul 23 04:51:56 PM PDT 24
Peak memory 255796 kb
Host smart-b6ef1f0b-e364-443d-be61-36475ee16bd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88119
2076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.881192076
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3576081984
Short name T368
Test name
Test status
Simulation time 51597633456 ps
CPU time 1042.78 seconds
Started Jul 23 04:50:47 PM PDT 24
Finished Jul 23 05:08:25 PM PDT 24
Peak memory 264984 kb
Host smart-66921987-98fb-470a-8bd9-7d3b0ace674f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576081984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3576081984
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.4112294665
Short name T98
Test name
Test status
Simulation time 24330638207 ps
CPU time 1743.67 seconds
Started Jul 23 04:50:58 PM PDT 24
Finished Jul 23 05:20:10 PM PDT 24
Peak memory 273008 kb
Host smart-bda4066a-55b6-46d6-ad35-543761964e12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112294665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.4112294665
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.743795282
Short name T495
Test name
Test status
Simulation time 3139004008 ps
CPU time 167.01 seconds
Started Jul 23 04:50:56 PM PDT 24
Finished Jul 23 04:53:52 PM PDT 24
Peak memory 256732 kb
Host smart-ffd4fef9-3178-4d9a-af23-1a0a34f5da91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74379
5282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.743795282
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.588337728
Short name T632
Test name
Test status
Simulation time 1005769409 ps
CPU time 31.83 seconds
Started Jul 23 04:50:56 PM PDT 24
Finished Jul 23 04:51:37 PM PDT 24
Peak memory 248604 kb
Host smart-48fc8f61-79b4-4246-852f-edb3d1383faa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58833
7728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.588337728
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.2397077773
Short name T106
Test name
Test status
Simulation time 38939019052 ps
CPU time 2476.65 seconds
Started Jul 23 04:50:58 PM PDT 24
Finished Jul 23 05:32:23 PM PDT 24
Peak memory 287080 kb
Host smart-8fdfafe4-e24d-4588-992e-65227d402cac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397077773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2397077773
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1826934447
Short name T592
Test name
Test status
Simulation time 44225343547 ps
CPU time 2684.91 seconds
Started Jul 23 04:50:58 PM PDT 24
Finished Jul 23 05:35:51 PM PDT 24
Peak memory 289496 kb
Host smart-9ee95ea3-e40f-4409-b658-1a9a6070048f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826934447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1826934447
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.2270008951
Short name T318
Test name
Test status
Simulation time 53933735588 ps
CPU time 223.29 seconds
Started Jul 23 04:50:54 PM PDT 24
Finished Jul 23 04:54:47 PM PDT 24
Peak memory 248588 kb
Host smart-c389af64-3d69-4e35-999d-7c1c79655873
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270008951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2270008951
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3392070519
Short name T624
Test name
Test status
Simulation time 571496850 ps
CPU time 10 seconds
Started Jul 23 04:50:55 PM PDT 24
Finished Jul 23 04:51:14 PM PDT 24
Peak memory 253576 kb
Host smart-d53a717a-0dc4-4abb-a8f0-15644a0365e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33920
70519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3392070519
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.1107461172
Short name T487
Test name
Test status
Simulation time 432604103 ps
CPU time 33.95 seconds
Started Jul 23 04:50:55 PM PDT 24
Finished Jul 23 04:51:39 PM PDT 24
Peak memory 256612 kb
Host smart-8053ffaf-caf6-476d-8177-b80083d4bdc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11074
61172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.1107461172
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.2664095022
Short name T699
Test name
Test status
Simulation time 1648247922 ps
CPU time 27.02 seconds
Started Jul 23 04:50:57 PM PDT 24
Finished Jul 23 04:51:32 PM PDT 24
Peak memory 248160 kb
Host smart-a3e4a9bc-e833-47dd-96b7-1785e1682988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26640
95022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2664095022
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.861639785
Short name T224
Test name
Test status
Simulation time 248220110 ps
CPU time 5.31 seconds
Started Jul 23 04:50:58 PM PDT 24
Finished Jul 23 04:51:11 PM PDT 24
Peak memory 250892 kb
Host smart-2edcf232-5865-4225-a10c-bb779cecdb6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86163
9785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.861639785
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.208588200
Short name T383
Test name
Test status
Simulation time 111871839847 ps
CPU time 3339.17 seconds
Started Jul 23 04:50:58 PM PDT 24
Finished Jul 23 05:46:45 PM PDT 24
Peak memory 289452 kb
Host smart-6c4654b7-b0aa-4633-8951-7cf650c99e2a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208588200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_han
dler_stress_all.208588200
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.2988667533
Short name T559
Test name
Test status
Simulation time 19736168082 ps
CPU time 1556.9 seconds
Started Jul 23 04:50:56 PM PDT 24
Finished Jul 23 05:17:02 PM PDT 24
Peak memory 289676 kb
Host smart-f8b51f43-f199-498f-b77c-a41265c9e55e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988667533 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.2988667533
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.2300511197
Short name T606
Test name
Test status
Simulation time 31435982169 ps
CPU time 1913.18 seconds
Started Jul 23 04:51:05 PM PDT 24
Finished Jul 23 05:23:03 PM PDT 24
Peak memory 272508 kb
Host smart-bd38bec2-a50b-45d5-bb96-8634448bf792
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300511197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.2300511197
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.726497421
Short name T417
Test name
Test status
Simulation time 3763727500 ps
CPU time 226.4 seconds
Started Jul 23 04:50:56 PM PDT 24
Finished Jul 23 04:54:51 PM PDT 24
Peak memory 256800 kb
Host smart-13ad5ce7-99ee-47d8-a5b3-87cf2829558c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72649
7421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.726497421
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.790793748
Short name T647
Test name
Test status
Simulation time 216383311 ps
CPU time 5.12 seconds
Started Jul 23 04:50:56 PM PDT 24
Finished Jul 23 04:51:10 PM PDT 24
Peak memory 252016 kb
Host smart-9abff772-8d4a-45be-a599-2212310850d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79079
3748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.790793748
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1386737215
Short name T10
Test name
Test status
Simulation time 34225226790 ps
CPU time 1168.17 seconds
Started Jul 23 04:51:05 PM PDT 24
Finished Jul 23 05:10:38 PM PDT 24
Peak memory 285288 kb
Host smart-0805c767-22d3-4076-9428-5b571419eeca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386737215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1386737215
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.2680132454
Short name T218
Test name
Test status
Simulation time 98134169992 ps
CPU time 1568.41 seconds
Started Jul 23 04:51:07 PM PDT 24
Finished Jul 23 05:17:20 PM PDT 24
Peak memory 289108 kb
Host smart-26ec2645-adf6-407a-93f7-f2e606c7c8a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680132454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.2680132454
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2324813788
Short name T696
Test name
Test status
Simulation time 18922564683 ps
CPU time 416.19 seconds
Started Jul 23 04:51:04 PM PDT 24
Finished Jul 23 04:58:05 PM PDT 24
Peak memory 256536 kb
Host smart-b9342374-efaf-4ce0-a4ff-a5dac26c9397
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324813788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2324813788
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.92727953
Short name T449
Test name
Test status
Simulation time 113384476 ps
CPU time 8.66 seconds
Started Jul 23 04:50:56 PM PDT 24
Finished Jul 23 04:51:14 PM PDT 24
Peak memory 254476 kb
Host smart-67e1a5be-a680-45bf-9407-966e3b3c389b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92727
953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.92727953
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.2770768207
Short name T657
Test name
Test status
Simulation time 1597549837 ps
CPU time 28.64 seconds
Started Jul 23 04:51:04 PM PDT 24
Finished Jul 23 04:51:38 PM PDT 24
Peak memory 256372 kb
Host smart-bc6c7559-5776-4b87-8aa8-c10540af8f12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27707
68207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2770768207
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2851564028
Short name T461
Test name
Test status
Simulation time 81923059 ps
CPU time 10.03 seconds
Started Jul 23 04:50:58 PM PDT 24
Finished Jul 23 04:51:16 PM PDT 24
Peak memory 254648 kb
Host smart-f3ea6b02-1579-4a83-8ac7-ffc433693235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28515
64028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2851564028
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.615892924
Short name T55
Test name
Test status
Simulation time 39744969616 ps
CPU time 2755.48 seconds
Started Jul 23 04:51:07 PM PDT 24
Finished Jul 23 05:37:06 PM PDT 24
Peak memory 288796 kb
Host smart-9cc7c1ab-eec2-4649-b8e1-f1bf0a89e311
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615892924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_han
dler_stress_all.615892924
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3356528427
Short name T675
Test name
Test status
Simulation time 59866673112 ps
CPU time 850.96 seconds
Started Jul 23 04:51:06 PM PDT 24
Finished Jul 23 05:05:21 PM PDT 24
Peak memory 273168 kb
Host smart-8effda32-c44a-43e9-a8b9-eba4bbc46200
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356528427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3356528427
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.4141943846
Short name T380
Test name
Test status
Simulation time 9698640022 ps
CPU time 167.25 seconds
Started Jul 23 04:51:05 PM PDT 24
Finished Jul 23 04:53:57 PM PDT 24
Peak memory 256140 kb
Host smart-4e460ac9-fcb7-42ac-b272-f9ecdc785752
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41419
43846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.4141943846
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.624250184
Short name T545
Test name
Test status
Simulation time 4550546116 ps
CPU time 56.14 seconds
Started Jul 23 04:51:08 PM PDT 24
Finished Jul 23 04:52:09 PM PDT 24
Peak memory 248612 kb
Host smart-54a34a59-c40e-41fc-9d25-7efd3920244c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62425
0184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.624250184
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3662583000
Short name T362
Test name
Test status
Simulation time 88271725124 ps
CPU time 1670.72 seconds
Started Jul 23 04:51:07 PM PDT 24
Finished Jul 23 05:19:03 PM PDT 24
Peak memory 289468 kb
Host smart-cc9976b2-0a71-42f0-a5e2-23864b33b49c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662583000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3662583000
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.721922517
Short name T595
Test name
Test status
Simulation time 5213740305 ps
CPU time 213.53 seconds
Started Jul 23 04:51:06 PM PDT 24
Finished Jul 23 04:54:44 PM PDT 24
Peak memory 248688 kb
Host smart-2b9c1023-0e5e-4412-b922-6f466fca03cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721922517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.721922517
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.783104487
Short name T403
Test name
Test status
Simulation time 351627229 ps
CPU time 16.27 seconds
Started Jul 23 04:51:04 PM PDT 24
Finished Jul 23 04:51:25 PM PDT 24
Peak memory 255360 kb
Host smart-7d9ad59c-b1dd-4ab7-ab65-4082022ba6a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78310
4487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.783104487
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3873685781
Short name T276
Test name
Test status
Simulation time 449981355 ps
CPU time 40.72 seconds
Started Jul 23 04:51:04 PM PDT 24
Finished Jul 23 04:51:49 PM PDT 24
Peak memory 248556 kb
Host smart-fbab868b-b33d-456e-8397-d5a66468386a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38736
85781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3873685781
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3998311710
Short name T58
Test name
Test status
Simulation time 1288543757 ps
CPU time 25.77 seconds
Started Jul 23 04:51:08 PM PDT 24
Finished Jul 23 04:51:39 PM PDT 24
Peak memory 248084 kb
Host smart-748ce12a-82ed-4c7e-a089-c31fcb7564dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39983
11710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3998311710
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.2750326894
Short name T34
Test name
Test status
Simulation time 1635957972 ps
CPU time 49.11 seconds
Started Jul 23 04:51:06 PM PDT 24
Finished Jul 23 04:51:59 PM PDT 24
Peak memory 256664 kb
Host smart-bf5f0d9e-1e68-40f3-bcd5-c9339f0abf57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27503
26894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2750326894
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3068821705
Short name T564
Test name
Test status
Simulation time 51916034023 ps
CPU time 1453.34 seconds
Started Jul 23 04:51:07 PM PDT 24
Finished Jul 23 05:15:26 PM PDT 24
Peak memory 289256 kb
Host smart-6f95e17a-b482-4609-bbc9-336784aa62a4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068821705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3068821705
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.1781005418
Short name T90
Test name
Test status
Simulation time 24812379673 ps
CPU time 1530.05 seconds
Started Jul 23 04:51:07 PM PDT 24
Finished Jul 23 05:16:42 PM PDT 24
Peak memory 272592 kb
Host smart-d03eb8e6-1e07-44d4-855f-691e10f26638
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781005418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1781005418
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2738292350
Short name T387
Test name
Test status
Simulation time 2383873218 ps
CPU time 104.83 seconds
Started Jul 23 04:51:08 PM PDT 24
Finished Jul 23 04:52:58 PM PDT 24
Peak memory 256872 kb
Host smart-76efde20-eab0-4a4b-b460-98cadcbf14f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27382
92350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2738292350
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3751092839
Short name T61
Test name
Test status
Simulation time 300166255 ps
CPU time 19.55 seconds
Started Jul 23 04:51:08 PM PDT 24
Finished Jul 23 04:51:33 PM PDT 24
Peak memory 248412 kb
Host smart-ca76965d-56f1-4c0e-8290-b129dbad8c81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37510
92839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3751092839
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2554895511
Short name T466
Test name
Test status
Simulation time 121416977879 ps
CPU time 928.09 seconds
Started Jul 23 04:51:08 PM PDT 24
Finished Jul 23 05:06:42 PM PDT 24
Peak memory 273152 kb
Host smart-ce2598fa-bb61-4904-9d3d-cf5344493417
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554895511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2554895511
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.4014270080
Short name T262
Test name
Test status
Simulation time 183623314890 ps
CPU time 1953.7 seconds
Started Jul 23 04:51:12 PM PDT 24
Finished Jul 23 05:23:50 PM PDT 24
Peak memory 273084 kb
Host smart-92d9d770-e35b-40fc-83b9-87176bdb5366
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014270080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.4014270080
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1415723542
Short name T373
Test name
Test status
Simulation time 4222252022 ps
CPU time 61.68 seconds
Started Jul 23 04:51:07 PM PDT 24
Finished Jul 23 04:52:14 PM PDT 24
Peak memory 255980 kb
Host smart-2ddf8f0d-488c-41d5-906b-6f4889543c00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14157
23542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1415723542
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1672972360
Short name T685
Test name
Test status
Simulation time 48933239 ps
CPU time 4.8 seconds
Started Jul 23 04:51:09 PM PDT 24
Finished Jul 23 04:51:19 PM PDT 24
Peak memory 239684 kb
Host smart-53b5d91a-2e37-4b9b-a279-2f75996e5513
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16729
72360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1672972360
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3160359410
Short name T686
Test name
Test status
Simulation time 2144303344 ps
CPU time 17.35 seconds
Started Jul 23 04:51:07 PM PDT 24
Finished Jul 23 04:51:30 PM PDT 24
Peak memory 247964 kb
Host smart-1f886756-ee10-4a77-aede-7db36b170671
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31603
59410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3160359410
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.1061683176
Short name T563
Test name
Test status
Simulation time 401224335 ps
CPU time 24.73 seconds
Started Jul 23 04:51:06 PM PDT 24
Finished Jul 23 04:51:35 PM PDT 24
Peak memory 256516 kb
Host smart-acbafab7-a9f3-40f1-a3d8-7c12918497e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10616
83176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.1061683176
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.879902086
Short name T626
Test name
Test status
Simulation time 121916645597 ps
CPU time 2688.85 seconds
Started Jul 23 04:51:07 PM PDT 24
Finished Jul 23 05:36:00 PM PDT 24
Peak memory 289268 kb
Host smart-59e9c8ce-0fad-4d91-9ee8-7b9ad7c2d3f6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879902086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_han
dler_stress_all.879902086
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.1724565416
Short name T241
Test name
Test status
Simulation time 281523595875 ps
CPU time 4515.85 seconds
Started Jul 23 04:51:18 PM PDT 24
Finished Jul 23 06:06:38 PM PDT 24
Peak memory 305456 kb
Host smart-d140b63e-b2ae-4d11-8e3c-e2110343ed25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724565416 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.1724565416
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3079692071
Short name T448
Test name
Test status
Simulation time 64383335405 ps
CPU time 1785.5 seconds
Started Jul 23 04:51:16 PM PDT 24
Finished Jul 23 05:21:06 PM PDT 24
Peak memory 288880 kb
Host smart-fdb59d73-d19e-4633-8c79-0ac2d8b13c8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079692071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3079692071
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.2077540181
Short name T257
Test name
Test status
Simulation time 1076315781 ps
CPU time 60.51 seconds
Started Jul 23 04:51:17 PM PDT 24
Finished Jul 23 04:52:22 PM PDT 24
Peak memory 256000 kb
Host smart-346e0f5a-6fe1-4186-bdda-1b21b1680562
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20775
40181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2077540181
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.1379807243
Short name T24
Test name
Test status
Simulation time 1990457487 ps
CPU time 32.05 seconds
Started Jul 23 04:51:15 PM PDT 24
Finished Jul 23 04:51:52 PM PDT 24
Peak memory 256752 kb
Host smart-e7c37e0b-4bef-4181-9e6b-6ee70914bdfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13798
07243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1379807243
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.3116297935
Short name T327
Test name
Test status
Simulation time 19427837842 ps
CPU time 1011.38 seconds
Started Jul 23 04:51:19 PM PDT 24
Finished Jul 23 05:08:15 PM PDT 24
Peak memory 272524 kb
Host smart-ea2a3063-f528-4a3a-9a53-4fc3bf6bc02a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116297935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3116297935
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.3007664710
Short name T531
Test name
Test status
Simulation time 42429091155 ps
CPU time 2262.43 seconds
Started Jul 23 04:51:15 PM PDT 24
Finished Jul 23 05:29:01 PM PDT 24
Peak memory 289228 kb
Host smart-14b9b349-e375-47e9-981f-76a9aea719ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007664710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3007664710
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3676007868
Short name T308
Test name
Test status
Simulation time 11800942535 ps
CPU time 463.56 seconds
Started Jul 23 04:51:16 PM PDT 24
Finished Jul 23 04:59:04 PM PDT 24
Peak memory 248620 kb
Host smart-98a71fb2-df01-43d7-bd1f-49005f75379f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676007868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3676007868
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.893920392
Short name T497
Test name
Test status
Simulation time 149991435 ps
CPU time 24.78 seconds
Started Jul 23 04:51:16 PM PDT 24
Finished Jul 23 04:51:45 PM PDT 24
Peak memory 248584 kb
Host smart-cdb62181-4d50-4c57-971c-da3c5a80391b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89392
0392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.893920392
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3337716043
Short name T532
Test name
Test status
Simulation time 995680267 ps
CPU time 22.03 seconds
Started Jul 23 04:51:16 PM PDT 24
Finished Jul 23 04:51:42 PM PDT 24
Peak memory 248052 kb
Host smart-dc2d4df5-4c94-4bba-ba64-d0ace448e098
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33377
16043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3337716043
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3607166828
Short name T456
Test name
Test status
Simulation time 2794588639 ps
CPU time 52.98 seconds
Started Jul 23 04:51:16 PM PDT 24
Finished Jul 23 04:52:13 PM PDT 24
Peak memory 249900 kb
Host smart-7c8e95ef-6dd0-40d5-8c46-1db574dce576
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36071
66828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3607166828
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1167959191
Short name T450
Test name
Test status
Simulation time 521944831 ps
CPU time 33.78 seconds
Started Jul 23 04:51:17 PM PDT 24
Finished Jul 23 04:51:55 PM PDT 24
Peak memory 256640 kb
Host smart-3ded4d0c-d3c4-4cd2-b0ad-628789b1ecff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11679
59191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1167959191
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3573680966
Short name T47
Test name
Test status
Simulation time 61378811740 ps
CPU time 3661.7 seconds
Started Jul 23 04:51:16 PM PDT 24
Finished Jul 23 05:52:23 PM PDT 24
Peak memory 289496 kb
Host smart-b5770627-c7af-40f1-9874-4d7b30053d5d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573680966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3573680966
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.2593472930
Short name T111
Test name
Test status
Simulation time 122335273214 ps
CPU time 3786.3 seconds
Started Jul 23 04:51:15 PM PDT 24
Finished Jul 23 05:54:26 PM PDT 24
Peak memory 297784 kb
Host smart-66d05036-1efe-4369-a717-98493cb06536
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593472930 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.2593472930
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1307361151
Short name T40
Test name
Test status
Simulation time 129442000 ps
CPU time 3.29 seconds
Started Jul 23 04:50:11 PM PDT 24
Finished Jul 23 04:50:21 PM PDT 24
Peak memory 248912 kb
Host smart-b690e3cf-004f-4afe-948e-b2d82291c27f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1307361151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1307361151
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2028749214
Short name T235
Test name
Test status
Simulation time 66907986335 ps
CPU time 1531 seconds
Started Jul 23 04:50:13 PM PDT 24
Finished Jul 23 05:15:51 PM PDT 24
Peak memory 288984 kb
Host smart-b29fa761-cbf0-491d-aad4-003c4828cab6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028749214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2028749214
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2370622306
Short name T384
Test name
Test status
Simulation time 135381753 ps
CPU time 8.07 seconds
Started Jul 23 04:50:12 PM PDT 24
Finished Jul 23 04:50:27 PM PDT 24
Peak memory 248460 kb
Host smart-68dbc53d-3290-4cba-bcfb-11fac7fe33a4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2370622306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2370622306
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.976837715
Short name T571
Test name
Test status
Simulation time 1302238532 ps
CPU time 52.8 seconds
Started Jul 23 04:50:11 PM PDT 24
Finished Jul 23 04:51:09 PM PDT 24
Peak memory 255860 kb
Host smart-4df3cd2c-c030-4b20-b259-9499026573bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97683
7715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.976837715
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1078455067
Short name T433
Test name
Test status
Simulation time 110930836 ps
CPU time 11.46 seconds
Started Jul 23 04:50:10 PM PDT 24
Finished Jul 23 04:50:25 PM PDT 24
Peak memory 248184 kb
Host smart-6a15b90d-1543-4f5e-84db-82dfe8ca8f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10784
55067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1078455067
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2498439884
Short name T270
Test name
Test status
Simulation time 172047533686 ps
CPU time 2555.62 seconds
Started Jul 23 04:50:10 PM PDT 24
Finished Jul 23 05:32:51 PM PDT 24
Peak memory 289004 kb
Host smart-e3c0803b-7179-40b7-8aab-3945f43657de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498439884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2498439884
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.165542741
Short name T471
Test name
Test status
Simulation time 28709673568 ps
CPU time 843.85 seconds
Started Jul 23 04:50:09 PM PDT 24
Finished Jul 23 05:04:17 PM PDT 24
Peak memory 273188 kb
Host smart-8b8cfc6c-2c44-46e1-8f87-9c5cf4ddac86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165542741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.165542741
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.714990014
Short name T640
Test name
Test status
Simulation time 1132952511 ps
CPU time 63.51 seconds
Started Jul 23 04:50:12 PM PDT 24
Finished Jul 23 04:51:22 PM PDT 24
Peak memory 256328 kb
Host smart-144bea07-fdcc-408c-a5d9-eb5d79025b94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71499
0014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.714990014
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2413822688
Short name T74
Test name
Test status
Simulation time 1819075151 ps
CPU time 24.86 seconds
Started Jul 23 04:50:10 PM PDT 24
Finished Jul 23 04:50:40 PM PDT 24
Peak memory 256812 kb
Host smart-6ddf0441-ea52-49cc-9ae8-ad18f9f678f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24138
22688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2413822688
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.366372394
Short name T525
Test name
Test status
Simulation time 370801662 ps
CPU time 28.89 seconds
Started Jul 23 04:50:11 PM PDT 24
Finished Jul 23 04:50:45 PM PDT 24
Peak memory 256076 kb
Host smart-c59cf12c-19c3-4f8e-821a-9e748cf92448
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36637
2394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.366372394
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2499598830
Short name T76
Test name
Test status
Simulation time 391628589 ps
CPU time 13.76 seconds
Started Jul 23 04:49:56 PM PDT 24
Finished Jul 23 04:50:13 PM PDT 24
Peak memory 254968 kb
Host smart-e8043512-5e7e-45e6-96a1-96a4d86a4bc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24995
98830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2499598830
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.3976814329
Short name T253
Test name
Test status
Simulation time 27933295675 ps
CPU time 1983.57 seconds
Started Jul 23 04:50:12 PM PDT 24
Finished Jul 23 05:23:23 PM PDT 24
Peak memory 286420 kb
Host smart-a741da8d-35f2-42f0-aa3b-9e07e514d6a6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976814329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.3976814329
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.843081094
Short name T113
Test name
Test status
Simulation time 31892500100 ps
CPU time 655.38 seconds
Started Jul 23 04:51:17 PM PDT 24
Finished Jul 23 05:02:16 PM PDT 24
Peak memory 273108 kb
Host smart-19f0a6fe-56cc-4334-bfb9-fb33d4ee6e61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843081094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.843081094
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.945004808
Short name T214
Test name
Test status
Simulation time 1485839000 ps
CPU time 85.34 seconds
Started Jul 23 04:51:15 PM PDT 24
Finished Jul 23 04:52:45 PM PDT 24
Peak memory 256808 kb
Host smart-189abf1f-1648-486e-9f95-be7aaa19a34f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94500
4808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.945004808
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3255517693
Short name T439
Test name
Test status
Simulation time 874563518 ps
CPU time 23.62 seconds
Started Jul 23 04:51:16 PM PDT 24
Finished Jul 23 04:51:44 PM PDT 24
Peak memory 248196 kb
Host smart-4b63d138-f0e6-456e-97a5-4d9cb5a362d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32555
17693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3255517693
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1652499058
Short name T325
Test name
Test status
Simulation time 28940689959 ps
CPU time 1999.49 seconds
Started Jul 23 04:51:18 PM PDT 24
Finished Jul 23 05:24:43 PM PDT 24
Peak memory 282896 kb
Host smart-31c7db82-4954-44a4-9db4-ba4379adbc46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652499058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1652499058
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.2642338744
Short name T481
Test name
Test status
Simulation time 89413482116 ps
CPU time 1753.93 seconds
Started Jul 23 04:51:15 PM PDT 24
Finished Jul 23 05:20:33 PM PDT 24
Peak memory 272512 kb
Host smart-6da76dc1-be73-4512-aaf9-050fea96046d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642338744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2642338744
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.1447154972
Short name T303
Test name
Test status
Simulation time 22699737494 ps
CPU time 239.57 seconds
Started Jul 23 04:51:15 PM PDT 24
Finished Jul 23 04:55:20 PM PDT 24
Peak memory 248612 kb
Host smart-98e81783-dd35-4127-93da-0138aa01ac11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447154972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.1447154972
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.799227378
Short name T371
Test name
Test status
Simulation time 804264460 ps
CPU time 45.96 seconds
Started Jul 23 04:51:15 PM PDT 24
Finished Jul 23 04:52:05 PM PDT 24
Peak memory 256016 kb
Host smart-462de6db-315c-4f52-ba47-cf6da659066c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79922
7378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.799227378
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.1552322078
Short name T372
Test name
Test status
Simulation time 102042757 ps
CPU time 7.75 seconds
Started Jul 23 04:51:15 PM PDT 24
Finished Jul 23 04:51:27 PM PDT 24
Peak memory 248180 kb
Host smart-4e868faf-b768-4512-a47e-2706da4e2ee0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15523
22078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1552322078
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3487165057
Short name T374
Test name
Test status
Simulation time 688495290 ps
CPU time 22.75 seconds
Started Jul 23 04:51:14 PM PDT 24
Finished Jul 23 04:51:41 PM PDT 24
Peak memory 248616 kb
Host smart-f8242851-b91a-425b-9190-d2c9c8a72213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34871
65057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3487165057
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2336252039
Short name T565
Test name
Test status
Simulation time 245203814 ps
CPU time 9.07 seconds
Started Jul 23 04:51:18 PM PDT 24
Finished Jul 23 04:51:31 PM PDT 24
Peak memory 254872 kb
Host smart-d4b339b5-bf33-4c90-8658-477e9a64b8a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23362
52039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2336252039
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.221777751
Short name T613
Test name
Test status
Simulation time 8192962232 ps
CPU time 90.53 seconds
Started Jul 23 04:51:23 PM PDT 24
Finished Jul 23 04:52:57 PM PDT 24
Peak memory 256872 kb
Host smart-45c82c92-4773-45c0-a305-c17ddba08282
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=221777751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_han
dler_stress_all.221777751
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3517118305
Short name T53
Test name
Test status
Simulation time 84355325815 ps
CPU time 994.29 seconds
Started Jul 23 04:51:23 PM PDT 24
Finished Jul 23 05:08:00 PM PDT 24
Peak memory 267136 kb
Host smart-f5b8a870-b21e-49df-8a9f-f774ee47b192
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517118305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3517118305
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2911572718
Short name T451
Test name
Test status
Simulation time 12588375805 ps
CPU time 191.06 seconds
Started Jul 23 04:51:23 PM PDT 24
Finished Jul 23 04:54:37 PM PDT 24
Peak memory 256828 kb
Host smart-631ad597-b371-4619-a592-e45cecbad990
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29115
72718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2911572718
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.510097042
Short name T227
Test name
Test status
Simulation time 141171387 ps
CPU time 14.27 seconds
Started Jul 23 04:51:23 PM PDT 24
Finished Jul 23 04:51:40 PM PDT 24
Peak memory 248048 kb
Host smart-b865656c-e5ec-4067-a568-0988e971f902
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51009
7042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.510097042
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3868052396
Short name T329
Test name
Test status
Simulation time 49189819948 ps
CPU time 2630.79 seconds
Started Jul 23 04:51:30 PM PDT 24
Finished Jul 23 05:35:26 PM PDT 24
Peak memory 288516 kb
Host smart-f740bc23-1f8e-4c8b-928b-7183402ce0f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868052396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3868052396
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.396937338
Short name T619
Test name
Test status
Simulation time 20338504069 ps
CPU time 1172.66 seconds
Started Jul 23 04:51:25 PM PDT 24
Finished Jul 23 05:11:01 PM PDT 24
Peak memory 283456 kb
Host smart-441aa4c3-b6ef-472f-bf97-18ecfb5f4b58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=396937338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.396937338
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.3008031977
Short name T220
Test name
Test status
Simulation time 20123151778 ps
CPU time 353.36 seconds
Started Jul 23 04:51:25 PM PDT 24
Finished Jul 23 04:57:22 PM PDT 24
Peak memory 248664 kb
Host smart-fc37aab2-9fef-4f1f-bb41-f20e33768cf4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008031977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.3008031977
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1983101542
Short name T217
Test name
Test status
Simulation time 594729172 ps
CPU time 15.54 seconds
Started Jul 23 04:51:27 PM PDT 24
Finished Jul 23 04:51:46 PM PDT 24
Peak memory 256044 kb
Host smart-d12b3194-0697-4857-806f-00c766dfd175
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19831
01542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1983101542
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3339132682
Short name T95
Test name
Test status
Simulation time 161465557 ps
CPU time 5.82 seconds
Started Jul 23 04:51:28 PM PDT 24
Finished Jul 23 04:51:38 PM PDT 24
Peak memory 248564 kb
Host smart-4fb85f2c-659a-4520-8cf4-ca54c9c7a802
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33391
32682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3339132682
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.3602126353
Short name T290
Test name
Test status
Simulation time 1415114407 ps
CPU time 26.56 seconds
Started Jul 23 04:51:27 PM PDT 24
Finished Jul 23 04:51:56 PM PDT 24
Peak memory 248488 kb
Host smart-be72b0ff-29b9-47b7-b923-60c6f68b4bf4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36021
26353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3602126353
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2270611830
Short name T386
Test name
Test status
Simulation time 221772477 ps
CPU time 13.36 seconds
Started Jul 23 04:51:23 PM PDT 24
Finished Jul 23 04:51:39 PM PDT 24
Peak memory 256708 kb
Host smart-23fa4ad9-8407-4366-98fe-e5cb75ef792f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22706
11830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2270611830
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.1706226176
Short name T268
Test name
Test status
Simulation time 21347165900 ps
CPU time 349.13 seconds
Started Jul 23 04:51:25 PM PDT 24
Finished Jul 23 04:57:18 PM PDT 24
Peak memory 256792 kb
Host smart-efa37dcc-ccae-4fd4-b5fe-9ccd2a6eee91
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706226176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.1706226176
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3649903458
Short name T85
Test name
Test status
Simulation time 29190127898 ps
CPU time 1416.23 seconds
Started Jul 23 04:51:24 PM PDT 24
Finished Jul 23 05:15:03 PM PDT 24
Peak memory 288212 kb
Host smart-46d4cebb-4a77-4497-a6f9-940eedb1b85a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649903458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3649903458
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1640932158
Short name T658
Test name
Test status
Simulation time 4687301568 ps
CPU time 133.89 seconds
Started Jul 23 04:51:25 PM PDT 24
Finished Jul 23 04:53:41 PM PDT 24
Peak memory 256764 kb
Host smart-77faa43e-ed5d-4cdb-809e-a8437deb2976
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16409
32158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1640932158
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2665459852
Short name T554
Test name
Test status
Simulation time 2796049676 ps
CPU time 44.03 seconds
Started Jul 23 04:51:29 PM PDT 24
Finished Jul 23 04:52:17 PM PDT 24
Peak memory 248708 kb
Host smart-788342d5-a534-49b1-b704-fceb05d6d7f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26654
59852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2665459852
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.1379740582
Short name T333
Test name
Test status
Simulation time 13489593040 ps
CPU time 1075.67 seconds
Started Jul 23 04:51:23 PM PDT 24
Finished Jul 23 05:09:22 PM PDT 24
Peak memory 272428 kb
Host smart-58867e97-1b44-4c3a-8dbd-b639260d7322
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379740582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1379740582
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.863436745
Short name T703
Test name
Test status
Simulation time 108234113501 ps
CPU time 2061.98 seconds
Started Jul 23 04:51:22 PM PDT 24
Finished Jul 23 05:25:47 PM PDT 24
Peak memory 283728 kb
Host smart-d9b05b1a-8fc1-4202-a86b-2390eb45e7ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=863436745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.863436745
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.230722886
Short name T107
Test name
Test status
Simulation time 23187076889 ps
CPU time 242.3 seconds
Started Jul 23 04:51:24 PM PDT 24
Finished Jul 23 04:55:29 PM PDT 24
Peak memory 248636 kb
Host smart-26e0f8cf-f3b6-4dd4-b02d-413b39a11411
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230722886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.230722886
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1641157866
Short name T645
Test name
Test status
Simulation time 4712737735 ps
CPU time 22.33 seconds
Started Jul 23 04:51:28 PM PDT 24
Finished Jul 23 04:51:54 PM PDT 24
Peak memory 248704 kb
Host smart-7cac1dba-0006-4547-82e7-cfee1e0fa0c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16411
57866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1641157866
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.1246577921
Short name T561
Test name
Test status
Simulation time 465543504 ps
CPU time 28.35 seconds
Started Jul 23 04:51:24 PM PDT 24
Finished Jul 23 04:51:55 PM PDT 24
Peak memory 248044 kb
Host smart-78a638b0-e2dd-464d-8cbf-6801b571c598
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12465
77921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1246577921
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.2014539722
Short name T103
Test name
Test status
Simulation time 10033556202 ps
CPU time 58.4 seconds
Started Jul 23 04:51:25 PM PDT 24
Finished Jul 23 04:52:27 PM PDT 24
Peak memory 255600 kb
Host smart-16b4f18b-c500-4edf-b3dc-8f5eef6db0ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20145
39722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.2014539722
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2634468425
Short name T435
Test name
Test status
Simulation time 205661226 ps
CPU time 19.16 seconds
Started Jul 23 04:51:22 PM PDT 24
Finished Jul 23 04:51:45 PM PDT 24
Peak memory 256472 kb
Host smart-2dc1d89a-ba1a-4ccf-b25c-ca537272bc07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26344
68425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2634468425
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1416903027
Short name T628
Test name
Test status
Simulation time 18031060445 ps
CPU time 1183.77 seconds
Started Jul 23 04:51:24 PM PDT 24
Finished Jul 23 05:11:11 PM PDT 24
Peak memory 272396 kb
Host smart-27d8303a-e168-4c28-bed4-2c115b3cbbd9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416903027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1416903027
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.89656074
Short name T689
Test name
Test status
Simulation time 149116141781 ps
CPU time 2512.79 seconds
Started Jul 23 04:51:31 PM PDT 24
Finished Jul 23 05:33:30 PM PDT 24
Peak memory 285308 kb
Host smart-80824a79-633b-47c0-84df-9bc1b64c97fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89656074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.89656074
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1430587647
Short name T558
Test name
Test status
Simulation time 2162791200 ps
CPU time 120.28 seconds
Started Jul 23 04:51:30 PM PDT 24
Finished Jul 23 04:53:36 PM PDT 24
Peak memory 256084 kb
Host smart-9a0315d7-024d-4f0d-a365-e3d6a4ddba1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14305
87647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1430587647
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.1214713112
Short name T289
Test name
Test status
Simulation time 2150622604 ps
CPU time 37.13 seconds
Started Jul 23 04:51:23 PM PDT 24
Finished Jul 23 04:52:03 PM PDT 24
Peak memory 255984 kb
Host smart-7ea567e3-df3d-4bbb-93c6-d0883c24c556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12147
13112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1214713112
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.505446193
Short name T255
Test name
Test status
Simulation time 36224725459 ps
CPU time 2373.34 seconds
Started Jul 23 04:51:35 PM PDT 24
Finished Jul 23 05:31:14 PM PDT 24
Peak memory 288968 kb
Host smart-b21e961c-c0d6-43a1-a442-80d6bd2ca320
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505446193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.505446193
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1367944042
Short name T304
Test name
Test status
Simulation time 11586041010 ps
CPU time 233 seconds
Started Jul 23 04:51:35 PM PDT 24
Finished Jul 23 04:55:33 PM PDT 24
Peak memory 248588 kb
Host smart-fd0528d9-3c30-490a-a542-4093c2082a60
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367944042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1367944042
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.2796839513
Short name T527
Test name
Test status
Simulation time 1670246146 ps
CPU time 33.47 seconds
Started Jul 23 04:51:25 PM PDT 24
Finished Jul 23 04:52:02 PM PDT 24
Peak memory 256552 kb
Host smart-79b796a5-b6a2-4608-92e0-055baeb57986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27968
39513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2796839513
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2475640885
Short name T505
Test name
Test status
Simulation time 380034816 ps
CPU time 11.79 seconds
Started Jul 23 04:51:26 PM PDT 24
Finished Jul 23 04:51:41 PM PDT 24
Peak memory 248064 kb
Host smart-f99183e1-1142-4831-b373-22b0125ee682
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24756
40885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2475640885
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2942461379
Short name T38
Test name
Test status
Simulation time 318141176 ps
CPU time 9.09 seconds
Started Jul 23 04:51:31 PM PDT 24
Finished Jul 23 04:51:46 PM PDT 24
Peak memory 248028 kb
Host smart-c4b75bd4-b9fa-4d0c-9239-a87a2928b9a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29424
61379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2942461379
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.753428369
Short name T694
Test name
Test status
Simulation time 455409831 ps
CPU time 30.05 seconds
Started Jul 23 04:51:25 PM PDT 24
Finished Jul 23 04:51:59 PM PDT 24
Peak memory 248612 kb
Host smart-9d3768d4-b596-49fc-954c-6befcec688c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75342
8369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.753428369
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2961121950
Short name T271
Test name
Test status
Simulation time 14432301346 ps
CPU time 852.67 seconds
Started Jul 23 04:51:31 PM PDT 24
Finished Jul 23 05:05:50 PM PDT 24
Peak memory 265024 kb
Host smart-e96525b5-2d7b-4e53-8751-89c114e758ce
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961121950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2961121950
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.3055960626
Short name T89
Test name
Test status
Simulation time 27016350891 ps
CPU time 1275.03 seconds
Started Jul 23 04:51:29 PM PDT 24
Finished Jul 23 05:12:50 PM PDT 24
Peak memory 286440 kb
Host smart-f1722099-ff9d-4e34-aa81-7014c71fcd32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055960626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3055960626
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.157424373
Short name T259
Test name
Test status
Simulation time 151588735 ps
CPU time 12.11 seconds
Started Jul 23 04:51:30 PM PDT 24
Finished Jul 23 04:51:47 PM PDT 24
Peak memory 254760 kb
Host smart-71290afb-9748-45ff-9347-638317bfca3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15742
4373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.157424373
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2181506683
Short name T491
Test name
Test status
Simulation time 3472106508 ps
CPU time 54.68 seconds
Started Jul 23 04:51:30 PM PDT 24
Finished Jul 23 04:52:30 PM PDT 24
Peak memory 255456 kb
Host smart-b1e50093-810f-4618-9975-dd1e3970addf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21815
06683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2181506683
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1691739110
Short name T317
Test name
Test status
Simulation time 10823423035 ps
CPU time 1104.12 seconds
Started Jul 23 04:51:30 PM PDT 24
Finished Jul 23 05:10:00 PM PDT 24
Peak memory 271332 kb
Host smart-438dfb3b-50f9-4af6-b556-7a4d8bdd1390
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691739110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1691739110
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.3537808924
Short name T692
Test name
Test status
Simulation time 17935138469 ps
CPU time 1699.93 seconds
Started Jul 23 04:51:31 PM PDT 24
Finished Jul 23 05:19:57 PM PDT 24
Peak memory 288724 kb
Host smart-395f6db7-343f-48d4-9919-93634ada6ea3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537808924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.3537808924
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3648908991
Short name T301
Test name
Test status
Simulation time 47571401092 ps
CPU time 326.03 seconds
Started Jul 23 04:51:29 PM PDT 24
Finished Jul 23 04:57:01 PM PDT 24
Peak memory 248224 kb
Host smart-1f27407a-a631-4189-bfc7-c484676b3ad3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648908991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3648908991
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.271177476
Short name T541
Test name
Test status
Simulation time 3856217097 ps
CPU time 57.08 seconds
Started Jul 23 04:51:29 PM PDT 24
Finished Jul 23 04:52:31 PM PDT 24
Peak memory 256568 kb
Host smart-0945e38c-2a0d-4b8e-996f-d5d4e675c2b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27117
7476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.271177476
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.540100336
Short name T544
Test name
Test status
Simulation time 202166190 ps
CPU time 17.04 seconds
Started Jul 23 04:51:30 PM PDT 24
Finished Jul 23 04:51:52 PM PDT 24
Peak memory 255920 kb
Host smart-bea726ce-e81d-4d5d-9f88-e8a209321bff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54010
0336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.540100336
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.373495971
Short name T101
Test name
Test status
Simulation time 2755067686 ps
CPU time 45.74 seconds
Started Jul 23 04:51:31 PM PDT 24
Finished Jul 23 04:52:23 PM PDT 24
Peak memory 256300 kb
Host smart-5245c73d-19d2-463d-9099-dc58efebada8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37349
5971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.373495971
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1684970685
Short name T650
Test name
Test status
Simulation time 198157746 ps
CPU time 12.44 seconds
Started Jul 23 04:51:29 PM PDT 24
Finished Jul 23 04:51:46 PM PDT 24
Peak memory 253596 kb
Host smart-4956da36-27e1-42c5-9116-885acc933c52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16849
70685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1684970685
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.277741011
Short name T526
Test name
Test status
Simulation time 19187465954 ps
CPU time 1027.92 seconds
Started Jul 23 04:51:29 PM PDT 24
Finished Jul 23 05:08:42 PM PDT 24
Peak memory 285536 kb
Host smart-49b1811e-5ce8-4cb0-9fc5-6787834e653e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277741011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.277741011
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.4284639374
Short name T455
Test name
Test status
Simulation time 643819801 ps
CPU time 59.27 seconds
Started Jul 23 04:51:39 PM PDT 24
Finished Jul 23 04:52:42 PM PDT 24
Peak memory 256044 kb
Host smart-d9700bd1-cc27-428b-9322-082e702675bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42846
39374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.4284639374
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.812617538
Short name T472
Test name
Test status
Simulation time 2278654878 ps
CPU time 28.7 seconds
Started Jul 23 04:51:36 PM PDT 24
Finished Jul 23 04:52:09 PM PDT 24
Peak memory 249088 kb
Host smart-3a061b50-b881-4e27-a095-8448706aa4c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81261
7538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.812617538
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.439046749
Short name T623
Test name
Test status
Simulation time 196155467346 ps
CPU time 2601.42 seconds
Started Jul 23 04:51:35 PM PDT 24
Finished Jul 23 05:35:02 PM PDT 24
Peak memory 283960 kb
Host smart-368b0a02-3fea-4d64-b97a-8fbc0d730793
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439046749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.439046749
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.606002351
Short name T92
Test name
Test status
Simulation time 10490795413 ps
CPU time 394.19 seconds
Started Jul 23 04:51:41 PM PDT 24
Finished Jul 23 04:58:18 PM PDT 24
Peak memory 248620 kb
Host smart-c617a5f5-2673-4f54-886e-4fefe65e78c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606002351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.606002351
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.1386479091
Short name T175
Test name
Test status
Simulation time 1572285931 ps
CPU time 28.73 seconds
Started Jul 23 04:51:35 PM PDT 24
Finished Jul 23 04:52:09 PM PDT 24
Peak memory 256108 kb
Host smart-34968dba-2cc5-44a7-8966-6dea49d2e4b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13864
79091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1386479091
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.3517033731
Short name T63
Test name
Test status
Simulation time 120837820 ps
CPU time 9.84 seconds
Started Jul 23 04:51:39 PM PDT 24
Finished Jul 23 04:51:53 PM PDT 24
Peak memory 250732 kb
Host smart-d980fbe8-60e7-4984-bc7a-a7594b0c182b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35170
33731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.3517033731
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.4120370560
Short name T275
Test name
Test status
Simulation time 528939895 ps
CPU time 26.59 seconds
Started Jul 23 04:51:34 PM PDT 24
Finished Jul 23 04:52:06 PM PDT 24
Peak memory 248176 kb
Host smart-fed43a0f-a63d-4257-a70c-12659abd525d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41203
70560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.4120370560
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.3793355626
Short name T420
Test name
Test status
Simulation time 66394563 ps
CPU time 4.6 seconds
Started Jul 23 04:51:29 PM PDT 24
Finished Jul 23 04:51:39 PM PDT 24
Peak memory 250732 kb
Host smart-0e8a5d6a-c889-4801-b667-57ec79982219
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37933
55626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.3793355626
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3689765407
Short name T283
Test name
Test status
Simulation time 43664675334 ps
CPU time 2309.47 seconds
Started Jul 23 04:51:41 PM PDT 24
Finished Jul 23 05:30:14 PM PDT 24
Peak memory 289092 kb
Host smart-17928548-8536-4656-909c-e6100a9edda4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689765407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3689765407
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.1761390183
Short name T393
Test name
Test status
Simulation time 106720175628 ps
CPU time 1521.41 seconds
Started Jul 23 04:51:41 PM PDT 24
Finished Jul 23 05:17:06 PM PDT 24
Peak memory 272380 kb
Host smart-cf52f2c0-f720-4aba-b9b4-f49488bb8cfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1761390183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.1761390183
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.4009361276
Short name T581
Test name
Test status
Simulation time 1768862648 ps
CPU time 121.55 seconds
Started Jul 23 04:51:35 PM PDT 24
Finished Jul 23 04:53:42 PM PDT 24
Peak memory 256404 kb
Host smart-809908d8-80fb-4471-8018-7e3a173c0764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40093
61276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.4009361276
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3976718254
Short name T181
Test name
Test status
Simulation time 604799217 ps
CPU time 21.62 seconds
Started Jul 23 04:51:36 PM PDT 24
Finished Jul 23 04:52:03 PM PDT 24
Peak memory 255304 kb
Host smart-8bbcb46e-9875-4447-bfab-f0f700a2cd63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39767
18254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3976718254
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3880863002
Short name T297
Test name
Test status
Simulation time 41143253159 ps
CPU time 1791.16 seconds
Started Jul 23 04:51:36 PM PDT 24
Finished Jul 23 05:21:32 PM PDT 24
Peak memory 288728 kb
Host smart-d7f23ea4-0eb7-4d2d-b2d7-75b8ab2eadd9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880863002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3880863002
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.826727396
Short name T418
Test name
Test status
Simulation time 14560642648 ps
CPU time 622.91 seconds
Started Jul 23 04:51:36 PM PDT 24
Finished Jul 23 05:02:04 PM PDT 24
Peak memory 273176 kb
Host smart-9689e46d-b448-43b8-bac5-40cacc3503f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826727396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.826727396
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.422462738
Short name T310
Test name
Test status
Simulation time 6604260416 ps
CPU time 258.07 seconds
Started Jul 23 04:51:36 PM PDT 24
Finished Jul 23 04:55:59 PM PDT 24
Peak memory 255600 kb
Host smart-6a82ce87-002b-4bc9-b418-d9e06fb06f56
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422462738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.422462738
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2056871571
Short name T588
Test name
Test status
Simulation time 602465655 ps
CPU time 37.06 seconds
Started Jul 23 04:51:37 PM PDT 24
Finished Jul 23 04:52:19 PM PDT 24
Peak memory 248612 kb
Host smart-4db249ca-9602-41ab-9d0c-1cf8fdb2fe25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20568
71571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2056871571
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2025456751
Short name T87
Test name
Test status
Simulation time 370889705 ps
CPU time 41.89 seconds
Started Jul 23 04:51:36 PM PDT 24
Finished Jul 23 04:52:23 PM PDT 24
Peak memory 256304 kb
Host smart-6e6f5a05-c36c-49b3-a29c-3fb484340028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20254
56751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2025456751
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2933002976
Short name T287
Test name
Test status
Simulation time 1164270362 ps
CPU time 35.88 seconds
Started Jul 23 04:51:35 PM PDT 24
Finished Jul 23 04:52:16 PM PDT 24
Peak memory 248560 kb
Host smart-aa2398b2-4e79-4817-83d8-d3d0ea320ae9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29330
02976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2933002976
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.163110632
Short name T400
Test name
Test status
Simulation time 288775977 ps
CPU time 18.19 seconds
Started Jul 23 04:51:35 PM PDT 24
Finished Jul 23 04:51:58 PM PDT 24
Peak memory 248572 kb
Host smart-459608d8-8a58-4d89-8c23-17abb1d63ea1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16311
0632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.163110632
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1232138088
Short name T680
Test name
Test status
Simulation time 45975680936 ps
CPU time 1037.58 seconds
Started Jul 23 04:51:37 PM PDT 24
Finished Jul 23 05:08:59 PM PDT 24
Peak memory 273008 kb
Host smart-d4e26773-65a2-4460-b63f-79e57a2de4a0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232138088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1232138088
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1204508767
Short name T4
Test name
Test status
Simulation time 34444323719 ps
CPU time 938.11 seconds
Started Jul 23 04:51:44 PM PDT 24
Finished Jul 23 05:07:24 PM PDT 24
Peak memory 272728 kb
Host smart-4bb885c9-c479-4662-b281-a0a901e4641f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204508767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1204508767
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1269821463
Short name T660
Test name
Test status
Simulation time 1342269645 ps
CPU time 24.05 seconds
Started Jul 23 04:51:44 PM PDT 24
Finished Jul 23 04:52:10 PM PDT 24
Peak memory 255144 kb
Host smart-c0d44594-381d-4329-aba8-233ca35152dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12698
21463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1269821463
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3315200326
Short name T1
Test name
Test status
Simulation time 328648186 ps
CPU time 34.22 seconds
Started Jul 23 04:51:44 PM PDT 24
Finished Jul 23 04:52:21 PM PDT 24
Peak memory 248572 kb
Host smart-a3380d78-1c16-4180-a6b0-981442d12bad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33152
00326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3315200326
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.3061820843
Short name T671
Test name
Test status
Simulation time 27715790008 ps
CPU time 1080.06 seconds
Started Jul 23 04:51:43 PM PDT 24
Finished Jul 23 05:09:46 PM PDT 24
Peak memory 272324 kb
Host smart-e47e019f-db2d-457d-aa9c-11533c298843
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061820843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3061820843
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3140697017
Short name T67
Test name
Test status
Simulation time 10627630906 ps
CPU time 938.49 seconds
Started Jul 23 04:51:44 PM PDT 24
Finished Jul 23 05:07:25 PM PDT 24
Peak memory 273124 kb
Host smart-eabb196e-3b9e-405d-9aab-3f79a61e114e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140697017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3140697017
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.3522394641
Short name T625
Test name
Test status
Simulation time 12340507471 ps
CPU time 475.51 seconds
Started Jul 23 04:51:42 PM PDT 24
Finished Jul 23 04:59:40 PM PDT 24
Peak memory 248672 kb
Host smart-4c426b0a-c103-4c47-9fb9-f7c5323d7d79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522394641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3522394641
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.1544607509
Short name T366
Test name
Test status
Simulation time 348443549 ps
CPU time 32.27 seconds
Started Jul 23 04:51:44 PM PDT 24
Finished Jul 23 04:52:19 PM PDT 24
Peak memory 248620 kb
Host smart-feeb85ed-fe58-4d52-ae3d-0defb2bb4674
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15446
07509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.1544607509
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2155858363
Short name T246
Test name
Test status
Simulation time 1214520744 ps
CPU time 74.71 seconds
Started Jul 23 04:51:49 PM PDT 24
Finished Jul 23 04:53:07 PM PDT 24
Peak memory 256456 kb
Host smart-446d4771-5bd8-4b86-b83b-e21366dfe504
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21558
58363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2155858363
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.2448566317
Short name T652
Test name
Test status
Simulation time 1169288675 ps
CPU time 24.7 seconds
Started Jul 23 04:51:45 PM PDT 24
Finished Jul 23 04:52:12 PM PDT 24
Peak memory 248160 kb
Host smart-297de7f3-ad27-4720-8322-37b723631eec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24485
66317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.2448566317
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3667527158
Short name T410
Test name
Test status
Simulation time 2121506124 ps
CPU time 30.57 seconds
Started Jul 23 04:51:40 PM PDT 24
Finished Jul 23 04:52:14 PM PDT 24
Peak memory 248732 kb
Host smart-1c531905-c0eb-4862-b755-2d38e5726b07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36675
27158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3667527158
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.2634898891
Short name T242
Test name
Test status
Simulation time 63673109305 ps
CPU time 4046.44 seconds
Started Jul 23 04:51:44 PM PDT 24
Finished Jul 23 05:59:13 PM PDT 24
Peak memory 305132 kb
Host smart-b295db48-d71f-4ed7-8bf8-959b79969ad5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634898891 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.2634898891
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.1965402755
Short name T284
Test name
Test status
Simulation time 65373536442 ps
CPU time 2252 seconds
Started Jul 23 04:51:43 PM PDT 24
Finished Jul 23 05:29:18 PM PDT 24
Peak memory 284424 kb
Host smart-a41accc6-a5a3-43b1-8666-1115968a0f07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965402755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.1965402755
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.292508024
Short name T605
Test name
Test status
Simulation time 554759533 ps
CPU time 45.05 seconds
Started Jul 23 04:51:43 PM PDT 24
Finished Jul 23 04:52:31 PM PDT 24
Peak memory 256816 kb
Host smart-a1f022cc-e996-4fcf-aff5-0275df6a5d58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29250
8024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.292508024
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.3893774093
Short name T20
Test name
Test status
Simulation time 4470917907 ps
CPU time 35.29 seconds
Started Jul 23 04:51:44 PM PDT 24
Finished Jul 23 04:52:22 PM PDT 24
Peak memory 248624 kb
Host smart-cf4b1205-341b-4ba2-8d87-8a0ab9f6e303
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38937
74093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.3893774093
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.3098855469
Short name T340
Test name
Test status
Simulation time 55780787789 ps
CPU time 1207.49 seconds
Started Jul 23 04:51:50 PM PDT 24
Finished Jul 23 05:12:00 PM PDT 24
Peak memory 282996 kb
Host smart-8a65df4e-50fa-43f4-a659-4d64ff631653
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098855469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3098855469
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1544482078
Short name T401
Test name
Test status
Simulation time 31962152029 ps
CPU time 929.19 seconds
Started Jul 23 04:51:44 PM PDT 24
Finished Jul 23 05:07:16 PM PDT 24
Peak memory 273144 kb
Host smart-868a15e5-5739-478a-80c5-71a6908853f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544482078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1544482078
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.3629153486
Short name T13
Test name
Test status
Simulation time 11869763171 ps
CPU time 473.7 seconds
Started Jul 23 04:51:44 PM PDT 24
Finished Jul 23 04:59:40 PM PDT 24
Peak memory 256400 kb
Host smart-ca51133a-847c-4c04-8725-e513ae40041c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3629153486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.3629153486
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3652896724
Short name T475
Test name
Test status
Simulation time 204653015 ps
CPU time 19.07 seconds
Started Jul 23 04:51:50 PM PDT 24
Finished Jul 23 04:52:11 PM PDT 24
Peak memory 255856 kb
Host smart-f7da69d3-c8d1-4c22-86d3-a62aeeb9ff22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36528
96724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3652896724
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.248736644
Short name T661
Test name
Test status
Simulation time 414856378 ps
CPU time 33.67 seconds
Started Jul 23 04:51:51 PM PDT 24
Finished Jul 23 04:52:27 PM PDT 24
Peak memory 256284 kb
Host smart-85f9170b-6e26-470b-9496-0cfa78295a3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24873
6644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.248736644
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.2093862400
Short name T712
Test name
Test status
Simulation time 146262582 ps
CPU time 18.37 seconds
Started Jul 23 04:51:44 PM PDT 24
Finished Jul 23 04:52:05 PM PDT 24
Peak memory 255804 kb
Host smart-e0eecfbc-b237-447f-8165-a1f2d676e353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20938
62400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2093862400
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2517603274
Short name T567
Test name
Test status
Simulation time 415632118 ps
CPU time 7.68 seconds
Started Jul 23 04:51:44 PM PDT 24
Finished Jul 23 04:51:54 PM PDT 24
Peak memory 251400 kb
Host smart-26ce09f3-5422-4d10-b078-b7f08ff1d8d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25176
03274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2517603274
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.1953795022
Short name T406
Test name
Test status
Simulation time 26142308253 ps
CPU time 1815.62 seconds
Started Jul 23 04:51:51 PM PDT 24
Finished Jul 23 05:22:09 PM PDT 24
Peak memory 272960 kb
Host smart-0ce29418-2533-495b-a979-7a3845ef9d74
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953795022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.1953795022
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.3784518960
Short name T423
Test name
Test status
Simulation time 2343033354 ps
CPU time 73.02 seconds
Started Jul 23 04:51:52 PM PDT 24
Finished Jul 23 04:53:07 PM PDT 24
Peak memory 256324 kb
Host smart-31c9ea4b-68d6-4aa9-bef9-e4cd7240195b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37845
18960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3784518960
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.397717202
Short name T678
Test name
Test status
Simulation time 232365793 ps
CPU time 25.71 seconds
Started Jul 23 04:51:49 PM PDT 24
Finished Jul 23 04:52:17 PM PDT 24
Peak memory 248560 kb
Host smart-8bb384ec-c622-4d24-8d85-85f0e7b526d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39771
7202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.397717202
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.4039327027
Short name T695
Test name
Test status
Simulation time 39597134034 ps
CPU time 2197.58 seconds
Started Jul 23 04:51:49 PM PDT 24
Finished Jul 23 05:28:30 PM PDT 24
Peak memory 272528 kb
Host smart-6b132a25-aa5d-4c29-93a9-88519893af90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039327027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.4039327027
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.2250357539
Short name T392
Test name
Test status
Simulation time 50762260098 ps
CPU time 1722.38 seconds
Started Jul 23 04:51:51 PM PDT 24
Finished Jul 23 05:20:36 PM PDT 24
Peak memory 289348 kb
Host smart-8352a0b4-5266-480b-86ca-5233d02a85d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250357539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.2250357539
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.3425707434
Short name T191
Test name
Test status
Simulation time 24154626955 ps
CPU time 249.25 seconds
Started Jul 23 04:51:50 PM PDT 24
Finished Jul 23 04:56:02 PM PDT 24
Peak memory 248488 kb
Host smart-fe0ec7b9-542d-43ce-b57e-d84d593c6555
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425707434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3425707434
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.1647601056
Short name T60
Test name
Test status
Simulation time 2913477488 ps
CPU time 23.02 seconds
Started Jul 23 04:51:49 PM PDT 24
Finished Jul 23 04:52:14 PM PDT 24
Peak memory 255244 kb
Host smart-3c1a484c-050d-4ae6-903c-5dc09cf6d64c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16476
01056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.1647601056
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2790755188
Short name T615
Test name
Test status
Simulation time 274245338 ps
CPU time 11.72 seconds
Started Jul 23 04:51:50 PM PDT 24
Finished Jul 23 04:52:04 PM PDT 24
Peak memory 248588 kb
Host smart-1fc87477-2f8d-4c85-b9c8-54354a528f23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27907
55188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2790755188
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2262615798
Short name T646
Test name
Test status
Simulation time 302652936 ps
CPU time 10.37 seconds
Started Jul 23 04:51:52 PM PDT 24
Finished Jul 23 04:52:05 PM PDT 24
Peak memory 248528 kb
Host smart-ff44a857-4ce9-40c3-b5b2-478036ca8aae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22626
15798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2262615798
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3626047121
Short name T642
Test name
Test status
Simulation time 323674258 ps
CPU time 29.49 seconds
Started Jul 23 04:51:49 PM PDT 24
Finished Jul 23 04:52:21 PM PDT 24
Peak memory 256664 kb
Host smart-a5b8e97c-3c15-48ab-bf2a-0fe662e8452c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36260
47121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3626047121
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2970190703
Short name T438
Test name
Test status
Simulation time 217587624200 ps
CPU time 3455.3 seconds
Started Jul 23 04:51:50 PM PDT 24
Finished Jul 23 05:49:28 PM PDT 24
Peak memory 289020 kb
Host smart-938ae644-e38c-4c0c-810b-106ee1c254e4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970190703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2970190703
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.695412359
Short name T252
Test name
Test status
Simulation time 232524409447 ps
CPU time 4829.29 seconds
Started Jul 23 04:51:49 PM PDT 24
Finished Jul 23 06:12:20 PM PDT 24
Peak memory 305988 kb
Host smart-8c0410da-6163-49e1-8028-5adcd928a755
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695412359 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.695412359
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2446996322
Short name T203
Test name
Test status
Simulation time 56051663 ps
CPU time 2.66 seconds
Started Jul 23 04:50:11 PM PDT 24
Finished Jul 23 04:50:19 PM PDT 24
Peak memory 248956 kb
Host smart-e8d06847-1bd1-4324-863b-1eacbcef2edd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2446996322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2446996322
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.658217578
Short name T516
Test name
Test status
Simulation time 50242880971 ps
CPU time 2946.95 seconds
Started Jul 23 04:50:11 PM PDT 24
Finished Jul 23 05:39:24 PM PDT 24
Peak memory 289008 kb
Host smart-1ff6adf1-5a8a-4ceb-be6a-2f3483abc4b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658217578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.658217578
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2050177846
Short name T546
Test name
Test status
Simulation time 514140403 ps
CPU time 13.9 seconds
Started Jul 23 04:50:11 PM PDT 24
Finished Jul 23 04:50:32 PM PDT 24
Peak memory 248572 kb
Host smart-d337170f-70de-4796-a31f-d7c69f9bcfbc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2050177846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2050177846
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.4284041096
Short name T389
Test name
Test status
Simulation time 11628433728 ps
CPU time 88.24 seconds
Started Jul 23 04:50:10 PM PDT 24
Finished Jul 23 04:51:43 PM PDT 24
Peak memory 256796 kb
Host smart-e039cd4a-60a2-40e6-b53e-5cc5a9aca778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42840
41096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.4284041096
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3095783446
Short name T454
Test name
Test status
Simulation time 1193203537 ps
CPU time 29.11 seconds
Started Jul 23 04:50:11 PM PDT 24
Finished Jul 23 04:50:46 PM PDT 24
Peak memory 248572 kb
Host smart-09cfa88c-a883-4cc7-a791-813cb4889099
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30957
83446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3095783446
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.9806031
Short name T192
Test name
Test status
Simulation time 81708319235 ps
CPU time 661.53 seconds
Started Jul 23 04:50:12 PM PDT 24
Finished Jul 23 05:01:21 PM PDT 24
Peak memory 272536 kb
Host smart-de47628d-6fb8-4abe-86e1-a3273ebdd97f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9806031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.9806031
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.730990515
Short name T8
Test name
Test status
Simulation time 104926625775 ps
CPU time 1794.05 seconds
Started Jul 23 04:50:11 PM PDT 24
Finished Jul 23 05:20:11 PM PDT 24
Peak memory 273212 kb
Host smart-1a5d3a53-b84a-483b-b25a-2a54664491f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730990515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.730990515
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2330685966
Short name T643
Test name
Test status
Simulation time 25487950808 ps
CPU time 533.21 seconds
Started Jul 23 04:50:11 PM PDT 24
Finished Jul 23 04:59:10 PM PDT 24
Peak memory 248584 kb
Host smart-c9cb42eb-bbfb-4f4a-a7e8-e0d1a3f9d65d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330685966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2330685966
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3664545272
Short name T396
Test name
Test status
Simulation time 3077207682 ps
CPU time 43.05 seconds
Started Jul 23 04:50:14 PM PDT 24
Finished Jul 23 04:51:04 PM PDT 24
Peak memory 255948 kb
Host smart-9947bcba-c09d-47cf-8c83-7ae25b28dbc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36645
45272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3664545272
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1424164330
Short name T665
Test name
Test status
Simulation time 2695810599 ps
CPU time 53.98 seconds
Started Jul 23 04:50:09 PM PDT 24
Finished Jul 23 04:51:08 PM PDT 24
Peak memory 256680 kb
Host smart-d2240baf-69eb-4598-bcd6-11895cc0e83d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14241
64330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1424164330
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.3965163246
Short name T35
Test name
Test status
Simulation time 828254330 ps
CPU time 15.44 seconds
Started Jul 23 04:50:15 PM PDT 24
Finished Jul 23 04:50:39 PM PDT 24
Peak memory 270792 kb
Host smart-6d927b7f-47b5-4f9a-8693-895a42cb91bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3965163246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3965163246
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.2021821950
Short name T266
Test name
Test status
Simulation time 8601930276 ps
CPU time 42.94 seconds
Started Jul 23 04:50:10 PM PDT 24
Finished Jul 23 04:50:58 PM PDT 24
Peak memory 248304 kb
Host smart-df95e406-1eab-4674-ab02-e1187e1908a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20218
21950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2021821950
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.2224640930
Short name T484
Test name
Test status
Simulation time 1164161369 ps
CPU time 20.28 seconds
Started Jul 23 04:50:12 PM PDT 24
Finished Jul 23 04:50:39 PM PDT 24
Peak memory 255756 kb
Host smart-a40b543e-8817-4bf5-ba5b-a6ce66a1a50b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22246
40930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.2224640930
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.166705876
Short name T607
Test name
Test status
Simulation time 80200012836 ps
CPU time 1756.96 seconds
Started Jul 23 04:50:12 PM PDT 24
Finished Jul 23 05:19:36 PM PDT 24
Peak memory 297564 kb
Host smart-070f8dc3-4d44-4d10-b67c-a92366d293d0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166705876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand
ler_stress_all.166705876
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.4189989205
Short name T97
Test name
Test status
Simulation time 209731387965 ps
CPU time 4853.9 seconds
Started Jul 23 04:50:11 PM PDT 24
Finished Jul 23 06:11:11 PM PDT 24
Peak memory 330600 kb
Host smart-e21e2d7d-4443-45be-b7a9-bf2250e4eab0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189989205 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.4189989205
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.4203762044
Short name T232
Test name
Test status
Simulation time 15303355647 ps
CPU time 1335.51 seconds
Started Jul 23 04:51:50 PM PDT 24
Finished Jul 23 05:14:08 PM PDT 24
Peak memory 284484 kb
Host smart-943144fb-466a-4ab8-9557-6f545c8d4eac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203762044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.4203762044
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.2008993458
Short name T429
Test name
Test status
Simulation time 911673117 ps
CPU time 26.9 seconds
Started Jul 23 04:51:49 PM PDT 24
Finished Jul 23 04:52:17 PM PDT 24
Peak memory 256376 kb
Host smart-8accf6b3-2480-4bc2-9c78-bb9364d1acfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20089
93458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2008993458
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.926216215
Short name T672
Test name
Test status
Simulation time 538202995 ps
CPU time 34.99 seconds
Started Jul 23 04:51:51 PM PDT 24
Finished Jul 23 04:52:28 PM PDT 24
Peak memory 248004 kb
Host smart-5c036508-a1be-4662-9738-1e684c8c3119
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92621
6215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.926216215
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2272993369
Short name T621
Test name
Test status
Simulation time 58118825951 ps
CPU time 3295.5 seconds
Started Jul 23 04:51:51 PM PDT 24
Finished Jul 23 05:46:50 PM PDT 24
Peak memory 289484 kb
Host smart-f0c401dc-b2c3-4323-acee-0e3c780949a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272993369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2272993369
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.3805725994
Short name T549
Test name
Test status
Simulation time 36581965638 ps
CPU time 1100.85 seconds
Started Jul 23 04:51:48 PM PDT 24
Finished Jul 23 05:10:10 PM PDT 24
Peak memory 283700 kb
Host smart-a38514ab-0e4a-4192-bbdc-55c9188caf3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805725994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3805725994
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.3600243333
Short name T311
Test name
Test status
Simulation time 2166372840 ps
CPU time 89.73 seconds
Started Jul 23 04:51:52 PM PDT 24
Finished Jul 23 04:53:24 PM PDT 24
Peak memory 254864 kb
Host smart-d96426d6-290c-45d9-9a00-6a53b422be6f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600243333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3600243333
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3602219971
Short name T510
Test name
Test status
Simulation time 3026612721 ps
CPU time 49.38 seconds
Started Jul 23 04:51:50 PM PDT 24
Finished Jul 23 04:52:42 PM PDT 24
Peak memory 256108 kb
Host smart-2e073120-e54c-47e0-a384-82e0af0745a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36022
19971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3602219971
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.233150017
Short name T536
Test name
Test status
Simulation time 1077545057 ps
CPU time 71.87 seconds
Started Jul 23 04:51:50 PM PDT 24
Finished Jul 23 04:53:04 PM PDT 24
Peak memory 256000 kb
Host smart-a3366bed-13eb-4dff-bb84-d73e9317e4b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23315
0017 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.233150017
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.2254663192
Short name T226
Test name
Test status
Simulation time 1617182087 ps
CPU time 29.38 seconds
Started Jul 23 04:51:52 PM PDT 24
Finished Jul 23 04:52:24 PM PDT 24
Peak memory 256072 kb
Host smart-e84dcc97-642a-4a0e-8036-c9514ab54082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22546
63192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2254663192
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1937204979
Short name T3
Test name
Test status
Simulation time 3953072296 ps
CPU time 62.7 seconds
Started Jul 23 04:51:51 PM PDT 24
Finished Jul 23 04:52:56 PM PDT 24
Peak memory 255952 kb
Host smart-2e7aaaab-9eb4-4d79-b104-6af63893b473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19372
04979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1937204979
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.3404740811
Short name T584
Test name
Test status
Simulation time 192773435 ps
CPU time 12.67 seconds
Started Jul 23 04:51:49 PM PDT 24
Finished Jul 23 04:52:04 PM PDT 24
Peak memory 254752 kb
Host smart-826c1676-412e-43cd-b06f-1678f2a1594e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404740811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.3404740811
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.2156489583
Short name T555
Test name
Test status
Simulation time 40163120574 ps
CPU time 4256.56 seconds
Started Jul 23 04:51:53 PM PDT 24
Finished Jul 23 06:02:51 PM PDT 24
Peak memory 351404 kb
Host smart-0a3ea59b-925c-4cb6-96c0-76ba941c7c16
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156489583 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.2156489583
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.280495974
Short name T630
Test name
Test status
Simulation time 44836612854 ps
CPU time 1473.32 seconds
Started Jul 23 04:51:57 PM PDT 24
Finished Jul 23 05:16:32 PM PDT 24
Peak memory 281248 kb
Host smart-738947ed-98ea-41bb-8375-2aaec03e4b41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280495974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.280495974
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.1465965096
Short name T250
Test name
Test status
Simulation time 15467546447 ps
CPU time 233.59 seconds
Started Jul 23 04:51:57 PM PDT 24
Finished Jul 23 04:55:52 PM PDT 24
Peak memory 256832 kb
Host smart-b9dd4e68-481a-4c9b-baf2-25de155f4769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14659
65096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1465965096
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1498637115
Short name T432
Test name
Test status
Simulation time 919498310 ps
CPU time 56.98 seconds
Started Jul 23 04:51:49 PM PDT 24
Finished Jul 23 04:52:49 PM PDT 24
Peak memory 248516 kb
Host smart-635c8fb1-8a73-4b20-8e99-66f83eeb11bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14986
37115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1498637115
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.597576916
Short name T332
Test name
Test status
Simulation time 123322454114 ps
CPU time 1309.36 seconds
Started Jul 23 04:51:59 PM PDT 24
Finished Jul 23 05:13:49 PM PDT 24
Peak memory 264852 kb
Host smart-66632160-d712-4916-b2d6-aba0bc857baf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597576916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.597576916
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2961154056
Short name T407
Test name
Test status
Simulation time 8737011458 ps
CPU time 1052.99 seconds
Started Jul 23 04:52:00 PM PDT 24
Finished Jul 23 05:09:33 PM PDT 24
Peak memory 281836 kb
Host smart-05334036-685d-4471-b39f-1f65c2bf0dfa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2961154056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2961154056
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1608739665
Short name T176
Test name
Test status
Simulation time 44137614 ps
CPU time 3.94 seconds
Started Jul 23 04:51:52 PM PDT 24
Finished Jul 23 04:51:58 PM PDT 24
Peak memory 248552 kb
Host smart-ec73146e-43fe-4523-90d0-d9e5e85342bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16087
39665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1608739665
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.434361672
Short name T509
Test name
Test status
Simulation time 1612415044 ps
CPU time 42.07 seconds
Started Jul 23 04:51:51 PM PDT 24
Finished Jul 23 04:52:35 PM PDT 24
Peak memory 248428 kb
Host smart-9a2b6d23-b571-455c-abd5-23fadf31321b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43436
1672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.434361672
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3069396108
Short name T501
Test name
Test status
Simulation time 646394579 ps
CPU time 36.81 seconds
Started Jul 23 04:51:57 PM PDT 24
Finished Jul 23 04:52:34 PM PDT 24
Peak memory 248568 kb
Host smart-d3620973-7f4f-4b0d-a912-5de0cfcad5b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30693
96108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3069396108
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.3412704610
Short name T514
Test name
Test status
Simulation time 1026962876 ps
CPU time 58.27 seconds
Started Jul 23 04:51:51 PM PDT 24
Finished Jul 23 04:52:52 PM PDT 24
Peak memory 256732 kb
Host smart-5b6fc95d-f5db-4b9f-b266-bee7afa8b5d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34127
04610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.3412704610
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.3876761508
Short name T108
Test name
Test status
Simulation time 786369296 ps
CPU time 67.39 seconds
Started Jul 23 04:51:58 PM PDT 24
Finished Jul 23 04:53:07 PM PDT 24
Peak memory 256700 kb
Host smart-45ae7ace-2600-4d30-b92d-d08f0d109714
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876761508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.3876761508
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.4109042503
Short name T521
Test name
Test status
Simulation time 165270961466 ps
CPU time 3006.3 seconds
Started Jul 23 04:51:57 PM PDT 24
Finished Jul 23 05:42:04 PM PDT 24
Peak memory 288976 kb
Host smart-c50e088a-26ad-460d-8031-3141a39e13e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109042503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.4109042503
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1776707879
Short name T557
Test name
Test status
Simulation time 113787810 ps
CPU time 7.42 seconds
Started Jul 23 04:51:57 PM PDT 24
Finished Jul 23 04:52:06 PM PDT 24
Peak memory 254280 kb
Host smart-7715820a-11ed-43a5-a3ab-7251a7bffca7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17767
07879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1776707879
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.921010818
Short name T398
Test name
Test status
Simulation time 7769845955 ps
CPU time 61.92 seconds
Started Jul 23 04:51:56 PM PDT 24
Finished Jul 23 04:52:59 PM PDT 24
Peak memory 256408 kb
Host smart-26e7baff-2837-4600-844a-0f4d9b880425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92101
0818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.921010818
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.2049673709
Short name T225
Test name
Test status
Simulation time 46503772113 ps
CPU time 875.5 seconds
Started Jul 23 04:52:06 PM PDT 24
Finished Jul 23 05:06:43 PM PDT 24
Peak memory 272544 kb
Host smart-318edbc8-befe-411a-952a-a298932586ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049673709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.2049673709
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1517975750
Short name T96
Test name
Test status
Simulation time 69727016959 ps
CPU time 2037.81 seconds
Started Jul 23 04:52:06 PM PDT 24
Finished Jul 23 05:26:05 PM PDT 24
Peak memory 272488 kb
Host smart-743e27e7-22aa-47b0-bf7c-328aa3700beb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517975750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1517975750
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1664894062
Short name T635
Test name
Test status
Simulation time 7563953470 ps
CPU time 314.75 seconds
Started Jul 23 04:51:56 PM PDT 24
Finished Jul 23 04:57:11 PM PDT 24
Peak memory 254924 kb
Host smart-15743862-c03b-4bcc-922b-2e4225079ede
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664894062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1664894062
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.951302879
Short name T382
Test name
Test status
Simulation time 85300066 ps
CPU time 9.81 seconds
Started Jul 23 04:51:59 PM PDT 24
Finished Jul 23 04:52:10 PM PDT 24
Peak memory 248608 kb
Host smart-ff9073aa-1d72-4d1f-bbb5-6956511f58e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95130
2879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.951302879
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3201955569
Short name T414
Test name
Test status
Simulation time 282085105 ps
CPU time 8.05 seconds
Started Jul 23 04:51:57 PM PDT 24
Finished Jul 23 04:52:06 PM PDT 24
Peak memory 248172 kb
Host smart-c92fdf7f-8e72-47c1-8d57-7869d96124ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32019
55569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3201955569
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.58333040
Short name T291
Test name
Test status
Simulation time 262905177 ps
CPU time 26.92 seconds
Started Jul 23 04:51:58 PM PDT 24
Finished Jul 23 04:52:26 PM PDT 24
Peak memory 256320 kb
Host smart-044f20a4-7afe-4114-8dcf-67a7556a4ba2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58333
040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.58333040
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.634520067
Short name T399
Test name
Test status
Simulation time 1111199886 ps
CPU time 59.86 seconds
Started Jul 23 04:51:56 PM PDT 24
Finished Jul 23 04:52:56 PM PDT 24
Peak memory 256748 kb
Host smart-7c1a2800-e16d-4230-b7cb-2298ad0a2b11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63452
0067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.634520067
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.121752269
Short name T548
Test name
Test status
Simulation time 19532176422 ps
CPU time 2023.21 seconds
Started Jul 23 04:52:07 PM PDT 24
Finished Jul 23 05:25:52 PM PDT 24
Peak memory 304848 kb
Host smart-2a7c1986-fe06-4114-be84-139dae4abda5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121752269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.121752269
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2539864111
Short name T697
Test name
Test status
Simulation time 46582748621 ps
CPU time 1041.04 seconds
Started Jul 23 04:52:06 PM PDT 24
Finished Jul 23 05:09:29 PM PDT 24
Peak memory 281744 kb
Host smart-91d6b9fa-b641-4550-87e6-ef6cd5ceab71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539864111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2539864111
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3720167769
Short name T376
Test name
Test status
Simulation time 3416212893 ps
CPU time 66.81 seconds
Started Jul 23 04:52:07 PM PDT 24
Finished Jul 23 04:53:15 PM PDT 24
Peak memory 256320 kb
Host smart-4a62a2a4-8acd-49f7-9184-e38b5893d064
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37201
67769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3720167769
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.750047914
Short name T669
Test name
Test status
Simulation time 1719291031 ps
CPU time 30.97 seconds
Started Jul 23 04:52:08 PM PDT 24
Finished Jul 23 04:52:40 PM PDT 24
Peak memory 248436 kb
Host smart-7b124730-2bd5-47e5-a659-61a49571404b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75004
7914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.750047914
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.3058441223
Short name T629
Test name
Test status
Simulation time 56370568453 ps
CPU time 1477.21 seconds
Started Jul 23 04:52:06 PM PDT 24
Finished Jul 23 05:16:45 PM PDT 24
Peak memory 289548 kb
Host smart-e6e67482-c93d-4c8e-a3e5-4559e2b55da6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058441223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.3058441223
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.4020546619
Short name T598
Test name
Test status
Simulation time 131176942958 ps
CPU time 2337.66 seconds
Started Jul 23 04:52:05 PM PDT 24
Finished Jul 23 05:31:04 PM PDT 24
Peak memory 281340 kb
Host smart-748627d8-0f9e-4dcb-8ce6-5b823177d459
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020546619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.4020546619
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.2386523628
Short name T603
Test name
Test status
Simulation time 2759042024 ps
CPU time 64.09 seconds
Started Jul 23 04:52:06 PM PDT 24
Finished Jul 23 04:53:11 PM PDT 24
Peak memory 248596 kb
Host smart-185fbabc-63fe-40e4-abc1-260bad8a670d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386523628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.2386523628
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3383877389
Short name T633
Test name
Test status
Simulation time 753773527 ps
CPU time 7.24 seconds
Started Jul 23 04:52:05 PM PDT 24
Finished Jul 23 04:52:14 PM PDT 24
Peak memory 248472 kb
Host smart-ca811271-0f2b-49d3-adb9-bdcedb2c7b49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33838
77389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3383877389
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.4054991258
Short name T402
Test name
Test status
Simulation time 3288044428 ps
CPU time 50.37 seconds
Started Jul 23 04:52:07 PM PDT 24
Finished Jul 23 04:52:59 PM PDT 24
Peak memory 256824 kb
Host smart-f901be96-65a8-4c66-882a-b958784df544
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40549
91258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.4054991258
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.821883368
Short name T649
Test name
Test status
Simulation time 4182632738 ps
CPU time 30.67 seconds
Started Jul 23 04:52:06 PM PDT 24
Finished Jul 23 04:52:37 PM PDT 24
Peak memory 256840 kb
Host smart-522abea2-56a0-466c-8b60-b51e11972fd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82188
3368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.821883368
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.3023906572
Short name T84
Test name
Test status
Simulation time 42299546849 ps
CPU time 2190.04 seconds
Started Jul 23 04:52:07 PM PDT 24
Finished Jul 23 05:28:38 PM PDT 24
Peak memory 281400 kb
Host smart-8d61c7b6-4f1f-42c0-bd2e-3b450965f0b3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023906572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.3023906572
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.4249698621
Short name T294
Test name
Test status
Simulation time 89896223673 ps
CPU time 8708.29 seconds
Started Jul 23 04:52:06 PM PDT 24
Finished Jul 23 07:17:17 PM PDT 24
Peak memory 371232 kb
Host smart-3cfd91b5-71c6-4959-a50c-4d5ee0ec10aa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249698621 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.4249698621
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.1069509654
Short name T637
Test name
Test status
Simulation time 149593214894 ps
CPU time 2898.8 seconds
Started Jul 23 04:52:15 PM PDT 24
Finished Jul 23 05:40:35 PM PDT 24
Peak memory 288560 kb
Host smart-bf1bf0b1-c4d0-4e27-83b1-5bf1ec315395
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1069509654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1069509654
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3893053175
Short name T360
Test name
Test status
Simulation time 4316889621 ps
CPU time 68.45 seconds
Started Jul 23 04:52:07 PM PDT 24
Finished Jul 23 04:53:17 PM PDT 24
Peak memory 256344 kb
Host smart-dc451e18-d981-4d21-a4f6-b81089f42f71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38930
53175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3893053175
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1537282647
Short name T490
Test name
Test status
Simulation time 1501559398 ps
CPU time 44.85 seconds
Started Jul 23 04:52:08 PM PDT 24
Finished Jul 23 04:52:54 PM PDT 24
Peak memory 255956 kb
Host smart-4a9a9c79-f969-486c-9c08-bb641edebca4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15372
82647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1537282647
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.1770558643
Short name T670
Test name
Test status
Simulation time 72003350762 ps
CPU time 1228.91 seconds
Started Jul 23 04:52:14 PM PDT 24
Finished Jul 23 05:12:44 PM PDT 24
Peak memory 273068 kb
Host smart-5c30207f-fd0b-4efe-a262-70c0b828700c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770558643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.1770558643
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.452380011
Short name T569
Test name
Test status
Simulation time 137545740923 ps
CPU time 2236.86 seconds
Started Jul 23 04:52:13 PM PDT 24
Finished Jul 23 05:29:32 PM PDT 24
Peak memory 272536 kb
Host smart-ac9f9dd9-a905-4a51-9500-6ce8860af15c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452380011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.452380011
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.1394292858
Short name T59
Test name
Test status
Simulation time 92663155 ps
CPU time 6.86 seconds
Started Jul 23 04:52:06 PM PDT 24
Finished Jul 23 04:52:14 PM PDT 24
Peak memory 248636 kb
Host smart-9f809652-f45c-4a06-9bcb-fc46609ffd71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13942
92858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.1394292858
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3819273955
Short name T377
Test name
Test status
Simulation time 257442544 ps
CPU time 22.01 seconds
Started Jul 23 04:52:06 PM PDT 24
Finished Jul 23 04:52:29 PM PDT 24
Peak memory 256744 kb
Host smart-5a3a44c4-248a-4f73-a394-8cc4c00b4c60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38192
73955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3819273955
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.963919544
Short name T51
Test name
Test status
Simulation time 47966932180 ps
CPU time 1161.64 seconds
Started Jul 23 04:52:14 PM PDT 24
Finished Jul 23 05:11:37 PM PDT 24
Peak memory 288288 kb
Host smart-1c1f0652-0380-4731-994d-6622f163bf92
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=963919544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_han
dler_stress_all.963919544
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.353348839
Short name T54
Test name
Test status
Simulation time 202301282255 ps
CPU time 3203.77 seconds
Started Jul 23 04:52:15 PM PDT 24
Finished Jul 23 05:45:40 PM PDT 24
Peak memory 297908 kb
Host smart-86002403-d7b7-4cdd-8d4e-8a499ea7869c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353348839 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.353348839
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.914476665
Short name T508
Test name
Test status
Simulation time 26586895593 ps
CPU time 775.27 seconds
Started Jul 23 04:52:17 PM PDT 24
Finished Jul 23 05:05:13 PM PDT 24
Peak memory 272892 kb
Host smart-a3f98c15-2152-4e1e-98b7-3ce92ddcb607
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914476665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.914476665
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3321684392
Short name T702
Test name
Test status
Simulation time 2819402546 ps
CPU time 40.66 seconds
Started Jul 23 04:52:13 PM PDT 24
Finished Jul 23 04:52:54 PM PDT 24
Peak memory 248132 kb
Host smart-aad614d6-7a1f-4de3-b50d-ddf07fd5d978
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33216
84392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3321684392
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3094802025
Short name T57
Test name
Test status
Simulation time 806940227 ps
CPU time 50.78 seconds
Started Jul 23 04:52:16 PM PDT 24
Finished Jul 23 04:53:08 PM PDT 24
Peak memory 256368 kb
Host smart-5f3e02e0-c701-4ccc-ae83-37f0d6f3ff67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30948
02025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3094802025
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2329972457
Short name T480
Test name
Test status
Simulation time 64539470679 ps
CPU time 1023.48 seconds
Started Jul 23 04:52:13 PM PDT 24
Finished Jul 23 05:09:18 PM PDT 24
Peak memory 272244 kb
Host smart-ecee1859-ac2e-498a-aa47-46ffb4cc51c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329972457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2329972457
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1936316847
Short name T178
Test name
Test status
Simulation time 142462943 ps
CPU time 5.34 seconds
Started Jul 23 04:52:16 PM PDT 24
Finished Jul 23 04:52:22 PM PDT 24
Peak memory 248532 kb
Host smart-4d3d89da-3e26-41aa-95fd-2818a67f09d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19363
16847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1936316847
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3120113453
Short name T421
Test name
Test status
Simulation time 421462961 ps
CPU time 11.88 seconds
Started Jul 23 04:52:16 PM PDT 24
Finished Jul 23 04:52:29 PM PDT 24
Peak memory 255364 kb
Host smart-95cff1cc-6d7e-4470-8a18-0a4e8aee6fb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31201
13453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3120113453
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.3468365828
Short name T441
Test name
Test status
Simulation time 33908197 ps
CPU time 5.52 seconds
Started Jul 23 04:52:15 PM PDT 24
Finished Jul 23 04:52:21 PM PDT 24
Peak memory 251252 kb
Host smart-b7006db9-37bf-4edb-9c0a-54fbf162ca60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34683
65828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.3468365828
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.4109655040
Short name T593
Test name
Test status
Simulation time 1010356524 ps
CPU time 14.55 seconds
Started Jul 23 04:52:14 PM PDT 24
Finished Jul 23 04:52:30 PM PDT 24
Peak memory 254968 kb
Host smart-84b7176f-712f-4638-b9c0-cdc37cf45025
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41096
55040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.4109655040
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2937331950
Short name T52
Test name
Test status
Simulation time 62077600190 ps
CPU time 1980.85 seconds
Started Jul 23 04:52:14 PM PDT 24
Finished Jul 23 05:25:16 PM PDT 24
Peak memory 286076 kb
Host smart-ebf8183d-7cb4-46d4-9c1b-3f7bbb709cce
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937331950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2937331950
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.2633919653
Short name T493
Test name
Test status
Simulation time 153822072787 ps
CPU time 6640.95 seconds
Started Jul 23 04:52:17 PM PDT 24
Finished Jul 23 06:42:59 PM PDT 24
Peak memory 336052 kb
Host smart-69ad0819-4a6a-48a1-8d11-2cf5dc376fce
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633919653 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.2633919653
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.516078838
Short name T690
Test name
Test status
Simulation time 38279339399 ps
CPU time 2245.25 seconds
Started Jul 23 04:52:24 PM PDT 24
Finished Jul 23 05:29:52 PM PDT 24
Peak memory 283192 kb
Host smart-fc098b51-eedd-4c6a-8496-33c864dcde78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516078838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.516078838
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.654758941
Short name T189
Test name
Test status
Simulation time 10034090071 ps
CPU time 112.91 seconds
Started Jul 23 04:52:22 PM PDT 24
Finished Jul 23 04:54:19 PM PDT 24
Peak memory 255956 kb
Host smart-4a1987b0-d167-4e56-80a7-119e24fddeb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65475
8941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.654758941
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1520877986
Short name T68
Test name
Test status
Simulation time 606690228 ps
CPU time 19.62 seconds
Started Jul 23 04:52:14 PM PDT 24
Finished Jul 23 04:52:35 PM PDT 24
Peak memory 248540 kb
Host smart-fd657f23-db68-4f61-90ef-a868004bf44d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15208
77986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1520877986
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.858592356
Short name T612
Test name
Test status
Simulation time 89645816746 ps
CPU time 2804.26 seconds
Started Jul 23 04:52:21 PM PDT 24
Finished Jul 23 05:39:09 PM PDT 24
Peak memory 281364 kb
Host smart-e5a3a11e-1343-48d5-9c49-e3d14940ab54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858592356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.858592356
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.4241537138
Short name T457
Test name
Test status
Simulation time 127983508202 ps
CPU time 2035.49 seconds
Started Jul 23 04:52:24 PM PDT 24
Finished Jul 23 05:26:22 PM PDT 24
Peak memory 281328 kb
Host smart-a6717c10-e174-4a48-b685-58a96762cfa5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241537138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.4241537138
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.4126956456
Short name T578
Test name
Test status
Simulation time 48126725315 ps
CPU time 516.31 seconds
Started Jul 23 04:52:22 PM PDT 24
Finished Jul 23 05:01:01 PM PDT 24
Peak memory 248540 kb
Host smart-4f96ca05-de2a-42db-b242-748db8686cfd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126956456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.4126956456
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3057025676
Short name T274
Test name
Test status
Simulation time 702250980 ps
CPU time 34.98 seconds
Started Jul 23 04:52:18 PM PDT 24
Finished Jul 23 04:52:54 PM PDT 24
Peak memory 248488 kb
Host smart-428bfa77-0a80-43f3-906a-4583d340ab32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30570
25676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3057025676
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2401547760
Short name T83
Test name
Test status
Simulation time 262901918 ps
CPU time 9.6 seconds
Started Jul 23 04:52:14 PM PDT 24
Finished Jul 23 04:52:25 PM PDT 24
Peak memory 254732 kb
Host smart-4bd2dffb-5c5b-46c5-8ff6-caa31c916980
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24015
47760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2401547760
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.1869954053
Short name T442
Test name
Test status
Simulation time 227371288 ps
CPU time 4.34 seconds
Started Jul 23 04:52:22 PM PDT 24
Finished Jul 23 04:52:29 PM PDT 24
Peak memory 239988 kb
Host smart-ebeec562-c1e8-4fc5-89f5-8e951dec0852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18699
54053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1869954053
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2344350067
Short name T662
Test name
Test status
Simulation time 532024685 ps
CPU time 12.73 seconds
Started Jul 23 04:52:17 PM PDT 24
Finished Jul 23 04:52:31 PM PDT 24
Peak memory 256616 kb
Host smart-5a556def-2334-4bef-9ce5-2a30073c966d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23443
50067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2344350067
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.2635089986
Short name T258
Test name
Test status
Simulation time 310262721248 ps
CPU time 3297.95 seconds
Started Jul 23 04:52:22 PM PDT 24
Finished Jul 23 05:47:24 PM PDT 24
Peak memory 303264 kb
Host smart-bebdd9bc-a0d8-43c1-87dc-4e33cd8b7db2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2635089986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.2635089986
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.1374326677
Short name T263
Test name
Test status
Simulation time 180158268068 ps
CPU time 4334.58 seconds
Started Jul 23 04:52:20 PM PDT 24
Finished Jul 23 06:04:36 PM PDT 24
Peak memory 306108 kb
Host smart-077517d2-4939-4381-b0cd-759b734b5d1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374326677 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.1374326677
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.88522379
Short name T443
Test name
Test status
Simulation time 54449795490 ps
CPU time 3298.18 seconds
Started Jul 23 04:52:20 PM PDT 24
Finished Jul 23 05:47:21 PM PDT 24
Peak memory 289244 kb
Host smart-ce0f3204-4ad7-4a96-b866-f70005689736
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88522379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.88522379
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.133515252
Short name T105
Test name
Test status
Simulation time 293990262 ps
CPU time 19.88 seconds
Started Jul 23 04:52:23 PM PDT 24
Finished Jul 23 04:52:46 PM PDT 24
Peak memory 247696 kb
Host smart-7116ff83-75d6-4e3f-94d9-031f8d665f66
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13351
5252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.133515252
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.1956388589
Short name T634
Test name
Test status
Simulation time 1545969929 ps
CPU time 25.23 seconds
Started Jul 23 04:52:22 PM PDT 24
Finished Jul 23 04:52:51 PM PDT 24
Peak memory 248568 kb
Host smart-75ba16a6-90c7-40c6-9264-0987df55c2cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19563
88589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.1956388589
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3109451024
Short name T654
Test name
Test status
Simulation time 33942568738 ps
CPU time 739.04 seconds
Started Jul 23 04:52:21 PM PDT 24
Finished Jul 23 05:04:42 PM PDT 24
Peak memory 264996 kb
Host smart-d49527b2-cff8-45d8-887e-9d565088f893
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109451024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3109451024
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.940487004
Short name T86
Test name
Test status
Simulation time 86922150594 ps
CPU time 1554.17 seconds
Started Jul 23 04:52:22 PM PDT 24
Finished Jul 23 05:18:19 PM PDT 24
Peak memory 272592 kb
Host smart-556e424b-6da8-44b0-b59c-81154b06de94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940487004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.940487004
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.1668252213
Short name T305
Test name
Test status
Simulation time 28434039827 ps
CPU time 569.56 seconds
Started Jul 23 04:52:24 PM PDT 24
Finished Jul 23 05:01:56 PM PDT 24
Peak memory 248660 kb
Host smart-d0f7c9c2-74e4-47e4-96fb-ba39895072e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668252213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.1668252213
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2931467107
Short name T515
Test name
Test status
Simulation time 958869258 ps
CPU time 25.64 seconds
Started Jul 23 04:52:22 PM PDT 24
Finished Jul 23 04:52:51 PM PDT 24
Peak memory 255936 kb
Host smart-16df504f-2105-482f-b8ba-7e26610cef35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29314
67107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2931467107
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2424651114
Short name T617
Test name
Test status
Simulation time 850647648 ps
CPU time 49.49 seconds
Started Jul 23 04:52:22 PM PDT 24
Finished Jul 23 04:53:14 PM PDT 24
Peak memory 248608 kb
Host smart-981759fd-e06e-464f-965b-e610ad5b77e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24246
51114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2424651114
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2958604359
Short name T295
Test name
Test status
Simulation time 1040951361 ps
CPU time 19.64 seconds
Started Jul 23 04:52:22 PM PDT 24
Finished Jul 23 04:52:44 PM PDT 24
Peak memory 248028 kb
Host smart-b92bd82d-39f7-4a6b-b324-377b32782db2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29586
04359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2958604359
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3907636116
Short name T679
Test name
Test status
Simulation time 2072832293 ps
CPU time 72.69 seconds
Started Jul 23 04:52:20 PM PDT 24
Finished Jul 23 04:53:34 PM PDT 24
Peak memory 256548 kb
Host smart-cbf4e219-16da-453e-a0a4-275beb460826
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39076
36116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3907636116
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.980078485
Short name T478
Test name
Test status
Simulation time 5223892205 ps
CPU time 217.66 seconds
Started Jul 23 04:52:21 PM PDT 24
Finished Jul 23 04:56:01 PM PDT 24
Peak memory 256852 kb
Host smart-8f38951b-8143-4c12-9d8f-5e6aa4e4cb1d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980078485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_han
dler_stress_all.980078485
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.3486175749
Short name T479
Test name
Test status
Simulation time 56877893317 ps
CPU time 1306 seconds
Started Jul 23 04:52:20 PM PDT 24
Finished Jul 23 05:14:08 PM PDT 24
Peak memory 279460 kb
Host smart-1a8e1270-8729-442c-85be-0fa9ba0297ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486175749 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.3486175749
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.4155044963
Short name T601
Test name
Test status
Simulation time 54949395002 ps
CPU time 1114.46 seconds
Started Jul 23 04:52:32 PM PDT 24
Finished Jul 23 05:11:13 PM PDT 24
Peak memory 288912 kb
Host smart-14385868-8c49-4e9a-93b1-33573506fa24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155044963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.4155044963
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2584595842
Short name T223
Test name
Test status
Simulation time 7554685568 ps
CPU time 167.21 seconds
Started Jul 23 04:52:21 PM PDT 24
Finished Jul 23 04:55:11 PM PDT 24
Peak memory 257040 kb
Host smart-f1640617-e144-4d95-8bdb-50df5ec1e74a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25845
95842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2584595842
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.1368796675
Short name T388
Test name
Test status
Simulation time 855489182 ps
CPU time 52.36 seconds
Started Jul 23 04:52:20 PM PDT 24
Finished Jul 23 04:53:15 PM PDT 24
Peak memory 255908 kb
Host smart-d22045a8-0b24-44dd-a5a8-63a59553a1da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13687
96675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1368796675
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.4044130572
Short name T343
Test name
Test status
Simulation time 324223451465 ps
CPU time 1199.34 seconds
Started Jul 23 04:52:34 PM PDT 24
Finished Jul 23 05:12:39 PM PDT 24
Peak memory 265000 kb
Host smart-cb131fdb-9eaf-4e29-b3fc-627ebe72ff93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044130572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.4044130572
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2441422816
Short name T542
Test name
Test status
Simulation time 31833983745 ps
CPU time 2089.07 seconds
Started Jul 23 04:52:34 PM PDT 24
Finished Jul 23 05:27:28 PM PDT 24
Peak memory 286404 kb
Host smart-edf17e26-5915-4065-ba34-2a76675855b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441422816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2441422816
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1603052858
Short name T322
Test name
Test status
Simulation time 23311294830 ps
CPU time 252.69 seconds
Started Jul 23 04:52:32 PM PDT 24
Finished Jul 23 04:56:51 PM PDT 24
Peak memory 248596 kb
Host smart-bcaec140-3bb0-4121-b11d-65f5ba5913bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603052858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1603052858
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2305255587
Short name T190
Test name
Test status
Simulation time 1035528649 ps
CPU time 17.87 seconds
Started Jul 23 04:52:21 PM PDT 24
Finished Jul 23 04:52:42 PM PDT 24
Peak memory 255880 kb
Host smart-c0fbf7e3-8ca2-4178-bc0c-9a39d554d7df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23052
55587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2305255587
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.437253600
Short name T463
Test name
Test status
Simulation time 824497109 ps
CPU time 25.44 seconds
Started Jul 23 04:52:22 PM PDT 24
Finished Jul 23 04:52:51 PM PDT 24
Peak memory 256328 kb
Host smart-66c0d3da-0618-4078-9d7d-29dbd2c1b140
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43725
3600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.437253600
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2652969995
Short name T64
Test name
Test status
Simulation time 1391962140 ps
CPU time 51.14 seconds
Started Jul 23 04:52:22 PM PDT 24
Finished Jul 23 04:53:17 PM PDT 24
Peak memory 256684 kb
Host smart-2f464235-6d3f-4aae-a7d0-b8f75c943f14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26529
69995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2652969995
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2520807797
Short name T530
Test name
Test status
Simulation time 388525982 ps
CPU time 14.13 seconds
Started Jul 23 04:52:22 PM PDT 24
Finished Jul 23 04:52:39 PM PDT 24
Peak memory 254012 kb
Host smart-6f64db2b-b9d5-4a27-ae7f-745e13551e65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25208
07797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2520807797
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1395600718
Short name T426
Test name
Test status
Simulation time 8281293653 ps
CPU time 558 seconds
Started Jul 23 04:52:31 PM PDT 24
Finished Jul 23 05:01:56 PM PDT 24
Peak memory 264996 kb
Host smart-eb29304a-2085-4e3f-987f-9c428ad26bdf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395600718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1395600718
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.2596776946
Short name T282
Test name
Test status
Simulation time 30655399270 ps
CPU time 2186.41 seconds
Started Jul 23 04:52:34 PM PDT 24
Finished Jul 23 05:29:06 PM PDT 24
Peak memory 289348 kb
Host smart-f38a27f6-b4d2-455f-88c5-226a2cd86ebb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596776946 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.2596776946
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2861328852
Short name T641
Test name
Test status
Simulation time 48363283912 ps
CPU time 1436.96 seconds
Started Jul 23 04:52:33 PM PDT 24
Finished Jul 23 05:16:36 PM PDT 24
Peak memory 288648 kb
Host smart-60a59a4c-73ef-4903-a4b9-6f6516bb9ddb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861328852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2861328852
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3525321209
Short name T523
Test name
Test status
Simulation time 12040437386 ps
CPU time 178.41 seconds
Started Jul 23 04:52:32 PM PDT 24
Finished Jul 23 04:55:37 PM PDT 24
Peak memory 256832 kb
Host smart-64fce335-9195-4db4-8949-52b02d1760b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35253
21209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3525321209
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.1277465716
Short name T2
Test name
Test status
Simulation time 330100629 ps
CPU time 19.13 seconds
Started Jul 23 04:52:32 PM PDT 24
Finished Jul 23 04:52:58 PM PDT 24
Peak memory 248032 kb
Host smart-26b66cff-cab4-4473-bbf1-a5a529a02843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12774
65716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.1277465716
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2159964051
Short name T552
Test name
Test status
Simulation time 49502126831 ps
CPU time 3140.16 seconds
Started Jul 23 04:52:34 PM PDT 24
Finished Jul 23 05:45:00 PM PDT 24
Peak memory 289456 kb
Host smart-8b916488-6054-47cc-8599-6525951444a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159964051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2159964051
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2850670797
Short name T233
Test name
Test status
Simulation time 35782120207 ps
CPU time 387.62 seconds
Started Jul 23 04:52:32 PM PDT 24
Finished Jul 23 04:59:06 PM PDT 24
Peak memory 248620 kb
Host smart-b4157b2c-783c-4d66-9478-f570c04b8010
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850670797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2850670797
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.2269493142
Short name T528
Test name
Test status
Simulation time 1329273377 ps
CPU time 48.8 seconds
Started Jul 23 04:52:31 PM PDT 24
Finished Jul 23 04:53:26 PM PDT 24
Peak memory 256744 kb
Host smart-8c5581d8-0f8b-4d40-a877-8bb6b27d8ee6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22694
93142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2269493142
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.18249483
Short name T597
Test name
Test status
Simulation time 68814496 ps
CPU time 5.41 seconds
Started Jul 23 04:52:32 PM PDT 24
Finished Jul 23 04:52:44 PM PDT 24
Peak memory 239568 kb
Host smart-b49498c1-230b-4dde-9403-71c25945041d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18249
483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.18249483
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2877604254
Short name T499
Test name
Test status
Simulation time 1452978898 ps
CPU time 51.64 seconds
Started Jul 23 04:52:33 PM PDT 24
Finished Jul 23 04:53:30 PM PDT 24
Peak memory 248456 kb
Host smart-685fcca0-e522-4278-831b-ab55e1034912
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28776
04254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2877604254
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1080752438
Short name T375
Test name
Test status
Simulation time 26727263 ps
CPU time 3.05 seconds
Started Jul 23 04:52:32 PM PDT 24
Finished Jul 23 04:52:41 PM PDT 24
Peak memory 250412 kb
Host smart-c3fe8590-00d2-47a8-8107-0ef80096a928
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10807
52438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1080752438
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1602361848
Short name T464
Test name
Test status
Simulation time 40160627077 ps
CPU time 2496.02 seconds
Started Jul 23 04:52:33 PM PDT 24
Finished Jul 23 05:34:15 PM PDT 24
Peak memory 297648 kb
Host smart-4a42101f-6248-4488-a403-db9ee2a99101
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602361848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1602361848
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.3644894479
Short name T180
Test name
Test status
Simulation time 147344197170 ps
CPU time 3126.44 seconds
Started Jul 23 04:52:33 PM PDT 24
Finished Jul 23 05:44:45 PM PDT 24
Peak memory 300900 kb
Host smart-d8a24e15-de5a-463d-9496-028f2f58103e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644894479 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.3644894479
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1265672037
Short name T196
Test name
Test status
Simulation time 218809214 ps
CPU time 3.29 seconds
Started Jul 23 04:50:11 PM PDT 24
Finished Jul 23 04:50:20 PM PDT 24
Peak memory 248828 kb
Host smart-d9605190-9bea-4a11-8c3d-be79503fdc16
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1265672037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1265672037
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.618128626
Short name T540
Test name
Test status
Simulation time 166726470930 ps
CPU time 2481.88 seconds
Started Jul 23 04:50:14 PM PDT 24
Finished Jul 23 05:31:44 PM PDT 24
Peak memory 289560 kb
Host smart-33239b85-a165-4d82-92a5-6f5083b6b3fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618128626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.618128626
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2015345886
Short name T470
Test name
Test status
Simulation time 2956145005 ps
CPU time 35.34 seconds
Started Jul 23 04:50:11 PM PDT 24
Finished Jul 23 04:50:52 PM PDT 24
Peak memory 248540 kb
Host smart-000fc439-4b0c-4d25-baf2-d2860d6bfc84
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2015345886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2015345886
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.159900873
Short name T428
Test name
Test status
Simulation time 1319671508 ps
CPU time 111.1 seconds
Started Jul 23 04:50:12 PM PDT 24
Finished Jul 23 04:52:10 PM PDT 24
Peak memory 256360 kb
Host smart-fabd987a-92dd-4283-862b-52f10b7c7cd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15990
0873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.159900873
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.970352158
Short name T653
Test name
Test status
Simulation time 1331280017 ps
CPU time 68.9 seconds
Started Jul 23 04:50:12 PM PDT 24
Finished Jul 23 04:51:28 PM PDT 24
Peak memory 256740 kb
Host smart-27f72eab-f794-4fd6-9649-266224bfe329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97035
2158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.970352158
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2387455428
Short name T338
Test name
Test status
Simulation time 28229945111 ps
CPU time 1017.52 seconds
Started Jul 23 04:50:13 PM PDT 24
Finished Jul 23 05:07:18 PM PDT 24
Peak memory 272628 kb
Host smart-a1bbdfc6-7eb8-4d9c-a5f3-4b215c440655
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387455428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2387455428
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.1717403243
Short name T179
Test name
Test status
Simulation time 42747678298 ps
CPU time 2437.89 seconds
Started Jul 23 04:50:10 PM PDT 24
Finished Jul 23 05:30:54 PM PDT 24
Peak memory 286424 kb
Host smart-7e9a8bb8-1988-418c-ad4f-0adcd1fe5ac4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717403243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.1717403243
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.3034423721
Short name T316
Test name
Test status
Simulation time 42048118725 ps
CPU time 255.81 seconds
Started Jul 23 04:50:12 PM PDT 24
Finished Jul 23 04:54:34 PM PDT 24
Peak memory 248480 kb
Host smart-d0d5cfc4-95e0-48c0-97f0-6afbb3320ea2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034423721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3034423721
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3347346940
Short name T534
Test name
Test status
Simulation time 316528994 ps
CPU time 19 seconds
Started Jul 23 04:50:10 PM PDT 24
Finished Jul 23 04:50:34 PM PDT 24
Peak memory 248576 kb
Host smart-7467cf96-753b-45c5-abe5-e5e4bab26956
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33473
46940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3347346940
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3888238910
Short name T473
Test name
Test status
Simulation time 2458041349 ps
CPU time 38.47 seconds
Started Jul 23 04:50:11 PM PDT 24
Finished Jul 23 04:50:55 PM PDT 24
Peak memory 255972 kb
Host smart-12b789a5-f47e-4fae-85f4-7ec0b936bc1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38882
38910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3888238910
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2072139586
Short name T618
Test name
Test status
Simulation time 38998497 ps
CPU time 4.81 seconds
Started Jul 23 04:50:15 PM PDT 24
Finished Jul 23 04:50:28 PM PDT 24
Peak memory 248560 kb
Host smart-6f3b4233-4155-4210-ae81-93b163674c0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20721
39586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2072139586
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.2822058997
Short name T522
Test name
Test status
Simulation time 173437932 ps
CPU time 13.73 seconds
Started Jul 23 04:50:15 PM PDT 24
Finished Jul 23 04:50:38 PM PDT 24
Peak memory 254880 kb
Host smart-88e4aea6-38f0-48a6-8fca-c4653ed90baa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28220
58997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2822058997
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.1878498422
Short name T70
Test name
Test status
Simulation time 6746679860 ps
CPU time 447.53 seconds
Started Jul 23 04:50:12 PM PDT 24
Finished Jul 23 04:57:47 PM PDT 24
Peak memory 267076 kb
Host smart-8b97c8f1-087e-4f36-89d5-84dbd918d413
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878498422 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.1878498422
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.3095823089
Short name T211
Test name
Test status
Simulation time 50180552 ps
CPU time 2.54 seconds
Started Jul 23 04:50:11 PM PDT 24
Finished Jul 23 04:50:19 PM PDT 24
Peak memory 248864 kb
Host smart-c52f25cc-01c9-413c-af98-336252836d4f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3095823089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3095823089
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2786628945
Short name T674
Test name
Test status
Simulation time 18242461251 ps
CPU time 830.41 seconds
Started Jul 23 04:50:13 PM PDT 24
Finished Jul 23 05:04:11 PM PDT 24
Peak memory 272928 kb
Host smart-4a252e2b-4265-4c45-8fa0-1ea6d510bd64
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786628945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2786628945
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1636364109
Short name T239
Test name
Test status
Simulation time 675834115 ps
CPU time 15.94 seconds
Started Jul 23 04:50:12 PM PDT 24
Finished Jul 23 04:50:35 PM PDT 24
Peak memory 248528 kb
Host smart-3ed67ed9-e182-4f16-a6d9-c2d1afe88984
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1636364109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1636364109
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.3488524165
Short name T611
Test name
Test status
Simulation time 1971637258 ps
CPU time 79.51 seconds
Started Jul 23 04:50:11 PM PDT 24
Finished Jul 23 04:51:37 PM PDT 24
Peak memory 256628 kb
Host smart-ec70f305-1478-4fe2-a446-88cb743febbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34885
24165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3488524165
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.602480679
Short name T434
Test name
Test status
Simulation time 1404309220 ps
CPU time 29.71 seconds
Started Jul 23 04:50:11 PM PDT 24
Finished Jul 23 04:50:47 PM PDT 24
Peak memory 248520 kb
Host smart-0781e316-0218-470d-8eae-74e4b2e1da97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60248
0679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.602480679
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.4118040240
Short name T583
Test name
Test status
Simulation time 254824891685 ps
CPU time 1803.47 seconds
Started Jul 23 04:50:13 PM PDT 24
Finished Jul 23 05:20:24 PM PDT 24
Peak memory 271080 kb
Host smart-526d8f29-1c3a-4e8a-a522-03089baccdfa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4118040240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.4118040240
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.2685409502
Short name T298
Test name
Test status
Simulation time 6827941304 ps
CPU time 75.35 seconds
Started Jul 23 04:50:12 PM PDT 24
Finished Jul 23 04:51:35 PM PDT 24
Peak memory 255348 kb
Host smart-24ee1d36-4818-4d4f-98e7-b58b3a3b1e1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685409502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.2685409502
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2552756167
Short name T446
Test name
Test status
Simulation time 1195439378 ps
CPU time 32.58 seconds
Started Jul 23 04:50:11 PM PDT 24
Finished Jul 23 04:50:49 PM PDT 24
Peak memory 255840 kb
Host smart-3575b4b0-2be9-4dc3-8d7e-6518c07ce417
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25527
56167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2552756167
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2994996843
Short name T110
Test name
Test status
Simulation time 949610107 ps
CPU time 56.54 seconds
Started Jul 23 04:50:10 PM PDT 24
Finished Jul 23 04:51:11 PM PDT 24
Peak memory 248036 kb
Host smart-127e4bad-25fb-4749-8967-599873173daf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29949
96843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2994996843
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.1704459428
Short name T281
Test name
Test status
Simulation time 1530878704 ps
CPU time 26.52 seconds
Started Jul 23 04:50:11 PM PDT 24
Finished Jul 23 04:50:45 PM PDT 24
Peak memory 256044 kb
Host smart-e3fcdb2c-d00f-4a38-8dc0-521e0bbef6bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17044
59428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1704459428
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.4097659113
Short name T620
Test name
Test status
Simulation time 872897640 ps
CPU time 37.82 seconds
Started Jul 23 04:50:10 PM PDT 24
Finished Jul 23 04:50:52 PM PDT 24
Peak memory 256684 kb
Host smart-bbcc9bd1-54d9-4256-863f-7f2a7539d432
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40976
59113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.4097659113
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.377554878
Short name T644
Test name
Test status
Simulation time 16309131081 ps
CPU time 1427.38 seconds
Started Jul 23 04:50:12 PM PDT 24
Finished Jul 23 05:14:07 PM PDT 24
Peak memory 288852 kb
Host smart-5558cfe5-0f1f-47d8-ad8b-ff3b3cc11926
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377554878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_hand
ler_stress_all.377554878
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3916903865
Short name T209
Test name
Test status
Simulation time 43427795 ps
CPU time 2.52 seconds
Started Jul 23 04:50:21 PM PDT 24
Finished Jul 23 04:50:36 PM PDT 24
Peak memory 248840 kb
Host smart-e8ef1c37-5119-4205-8e57-2375322292b0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3916903865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3916903865
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1375402689
Short name T639
Test name
Test status
Simulation time 208746721593 ps
CPU time 3111.67 seconds
Started Jul 23 04:50:22 PM PDT 24
Finished Jul 23 05:42:27 PM PDT 24
Peak memory 287564 kb
Host smart-58499d50-e740-4e81-b926-f30e7e66c18d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375402689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1375402689
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2704708500
Short name T529
Test name
Test status
Simulation time 236045587 ps
CPU time 13.37 seconds
Started Jul 23 04:50:28 PM PDT 24
Finished Jul 23 04:50:57 PM PDT 24
Peak memory 248412 kb
Host smart-ca950f78-a0e2-4716-b6f3-77f7536a5b1c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2704708500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2704708500
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.126786838
Short name T427
Test name
Test status
Simulation time 21943233058 ps
CPU time 300.7 seconds
Started Jul 23 04:50:21 PM PDT 24
Finished Jul 23 04:55:34 PM PDT 24
Peak memory 256856 kb
Host smart-46b55f0c-fc93-4526-88cb-0b94daff3676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12678
6838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.126786838
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.171382534
Short name T489
Test name
Test status
Simulation time 2633823602 ps
CPU time 21.27 seconds
Started Jul 23 04:50:14 PM PDT 24
Finished Jul 23 04:50:44 PM PDT 24
Peak memory 248320 kb
Host smart-cac7e348-9e17-4a78-90cc-626766c80649
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17138
2534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.171382534
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1304286351
Short name T334
Test name
Test status
Simulation time 66948308476 ps
CPU time 2099.6 seconds
Started Jul 23 04:50:21 PM PDT 24
Finished Jul 23 05:25:34 PM PDT 24
Peak memory 273128 kb
Host smart-1feb62d5-1869-47f0-a533-82837675d0fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304286351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1304286351
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2169102062
Short name T422
Test name
Test status
Simulation time 52480096814 ps
CPU time 1248.63 seconds
Started Jul 23 04:50:25 PM PDT 24
Finished Jul 23 05:11:28 PM PDT 24
Peak memory 289328 kb
Host smart-b3dc030f-b16a-4cd4-920c-670ab9439326
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169102062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2169102062
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2256851257
Short name T602
Test name
Test status
Simulation time 17850179515 ps
CPU time 187.85 seconds
Started Jul 23 04:50:20 PM PDT 24
Finished Jul 23 04:53:39 PM PDT 24
Peak memory 248616 kb
Host smart-bf240ab3-205f-4e75-a6c1-99f0babc2bf9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256851257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2256851257
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.2856853407
Short name T498
Test name
Test status
Simulation time 454540370 ps
CPU time 26.57 seconds
Started Jul 23 04:50:14 PM PDT 24
Finished Jul 23 04:50:49 PM PDT 24
Peak memory 248548 kb
Host smart-8c825e6d-f0a5-4551-979b-0d9c4d3cfbea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28568
53407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.2856853407
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2391067974
Short name T361
Test name
Test status
Simulation time 54195861 ps
CPU time 4.47 seconds
Started Jul 23 04:50:09 PM PDT 24
Finished Jul 23 04:50:15 PM PDT 24
Peak memory 248816 kb
Host smart-2f324e32-b864-4999-b0f0-de8176f54a5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23910
67974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2391067974
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.2617911551
Short name T177
Test name
Test status
Simulation time 1159581504 ps
CPU time 68.58 seconds
Started Jul 23 04:50:20 PM PDT 24
Finished Jul 23 04:51:41 PM PDT 24
Peak memory 256684 kb
Host smart-6c63fd11-8a4d-4c86-9c6e-6845910f4d12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26179
11551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.2617911551
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.996511648
Short name T215
Test name
Test status
Simulation time 5051706626 ps
CPU time 50.04 seconds
Started Jul 23 04:50:12 PM PDT 24
Finished Jul 23 04:51:09 PM PDT 24
Peak memory 256808 kb
Host smart-02fea59c-f8ce-41fc-b992-eb397102f16b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99651
1648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.996511648
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1951173397
Short name T415
Test name
Test status
Simulation time 44357716456 ps
CPU time 983.37 seconds
Started Jul 23 04:50:21 PM PDT 24
Finished Jul 23 05:06:58 PM PDT 24
Peak memory 288376 kb
Host smart-7c0f5cc3-c630-4459-a167-d34b98b4ab42
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951173397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1951173397
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.1303983186
Short name T582
Test name
Test status
Simulation time 137969659932 ps
CPU time 3768.62 seconds
Started Jul 23 04:50:24 PM PDT 24
Finished Jul 23 05:53:27 PM PDT 24
Peak memory 301496 kb
Host smart-92470867-5158-4341-b897-d64045ef004c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303983186 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.1303983186
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.616536905
Short name T199
Test name
Test status
Simulation time 164414841 ps
CPU time 3.74 seconds
Started Jul 23 04:50:21 PM PDT 24
Finished Jul 23 04:50:38 PM PDT 24
Peak memory 248768 kb
Host smart-3e0ddc0f-465a-4f2f-811c-d27ac9409580
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=616536905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.616536905
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2432180476
Short name T707
Test name
Test status
Simulation time 109189334230 ps
CPU time 1598.99 seconds
Started Jul 23 04:50:24 PM PDT 24
Finished Jul 23 05:17:18 PM PDT 24
Peak memory 272660 kb
Host smart-6f75f918-82cd-476b-90ee-3f5e2f2709e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432180476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2432180476
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.3378773523
Short name T518
Test name
Test status
Simulation time 4747226159 ps
CPU time 52.02 seconds
Started Jul 23 04:50:23 PM PDT 24
Finished Jul 23 04:51:29 PM PDT 24
Peak memory 248524 kb
Host smart-3b48da5a-5498-4b0a-8aa2-8b34b2ffc259
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3378773523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.3378773523
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.2198078227
Short name T359
Test name
Test status
Simulation time 102243512 ps
CPU time 10.58 seconds
Started Jul 23 04:50:22 PM PDT 24
Finished Jul 23 04:50:46 PM PDT 24
Peak memory 254600 kb
Host smart-1c1baa59-c296-4687-82cf-832030c09d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21980
78227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.2198078227
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.3165597630
Short name T71
Test name
Test status
Simulation time 291971668 ps
CPU time 29.12 seconds
Started Jul 23 04:50:24 PM PDT 24
Finished Jul 23 04:51:08 PM PDT 24
Peak memory 256592 kb
Host smart-71fca04e-7d2a-4111-b1f6-649f985a6756
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31655
97630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.3165597630
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1624270091
Short name T519
Test name
Test status
Simulation time 27800498464 ps
CPU time 1826.62 seconds
Started Jul 23 04:50:24 PM PDT 24
Finished Jul 23 05:21:05 PM PDT 24
Peak memory 273152 kb
Host smart-6c649973-2426-4a3d-8eda-1ec6734bfc21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624270091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1624270091
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1520119371
Short name T315
Test name
Test status
Simulation time 15902890591 ps
CPU time 342.48 seconds
Started Jul 23 04:50:30 PM PDT 24
Finished Jul 23 04:56:29 PM PDT 24
Peak memory 248580 kb
Host smart-e2ace848-bf55-41ee-8038-947240582965
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1520119371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1520119371
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3831472758
Short name T408
Test name
Test status
Simulation time 82729926 ps
CPU time 5.29 seconds
Started Jul 23 04:50:23 PM PDT 24
Finished Jul 23 04:50:42 PM PDT 24
Peak memory 240376 kb
Host smart-099015e5-6412-4f38-b11c-d46cd81c7917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38314
72758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3831472758
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.840518633
Short name T610
Test name
Test status
Simulation time 1654800049 ps
CPU time 17.88 seconds
Started Jul 23 04:50:30 PM PDT 24
Finished Jul 23 04:51:04 PM PDT 24
Peak memory 248184 kb
Host smart-e9a95ed5-1954-4eb6-9b66-f83bb7de9533
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84051
8633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.840518633
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.2327293190
Short name T230
Test name
Test status
Simulation time 66902518 ps
CPU time 5.48 seconds
Started Jul 23 04:50:22 PM PDT 24
Finished Jul 23 04:50:40 PM PDT 24
Peak memory 240320 kb
Host smart-d0a796cb-f493-4514-9a0a-5117584b9642
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23272
93190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.2327293190
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.58317817
Short name T517
Test name
Test status
Simulation time 783012436 ps
CPU time 38.22 seconds
Started Jul 23 04:50:21 PM PDT 24
Finished Jul 23 04:51:12 PM PDT 24
Peak memory 256748 kb
Host smart-2385f8d0-8fec-4574-854f-c355d1b35743
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58317
817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.58317817
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.2317386082
Short name T88
Test name
Test status
Simulation time 59119271094 ps
CPU time 1412.2 seconds
Started Jul 23 04:50:29 PM PDT 24
Finished Jul 23 05:14:17 PM PDT 24
Peak memory 289268 kb
Host smart-232627ac-354d-44ff-ad7a-a5bdfeb788b0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317386082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.2317386082
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1827788853
Short name T201
Test name
Test status
Simulation time 33335589 ps
CPU time 3.24 seconds
Started Jul 23 04:50:26 PM PDT 24
Finished Jul 23 04:50:43 PM PDT 24
Peak memory 248812 kb
Host smart-71024ce1-8e1f-4214-b77a-e48111bd8a89
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1827788853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1827788853
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.805808993
Short name T666
Test name
Test status
Simulation time 87403785344 ps
CPU time 966.45 seconds
Started Jul 23 04:50:24 PM PDT 24
Finished Jul 23 05:06:45 PM PDT 24
Peak memory 273456 kb
Host smart-cd8b4930-4b7f-4bff-a922-698b2f4e3c2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805808993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.805808993
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.4043718162
Short name T524
Test name
Test status
Simulation time 1038334289 ps
CPU time 13.02 seconds
Started Jul 23 04:50:22 PM PDT 24
Finished Jul 23 04:50:48 PM PDT 24
Peak memory 248528 kb
Host smart-b1531b96-be0c-4ed6-913e-88af2f4989dd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4043718162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.4043718162
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3472858424
Short name T229
Test name
Test status
Simulation time 106587736 ps
CPU time 12.59 seconds
Started Jul 23 04:50:20 PM PDT 24
Finished Jul 23 04:50:45 PM PDT 24
Peak memory 256280 kb
Host smart-4f1d1b78-f4fa-458a-8185-b7da4deba465
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34728
58424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3472858424
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.1810306011
Short name T504
Test name
Test status
Simulation time 257192379 ps
CPU time 25.13 seconds
Started Jul 23 04:50:29 PM PDT 24
Finished Jul 23 04:51:10 PM PDT 24
Peak memory 248560 kb
Host smart-23661093-4bab-47a4-b4d0-9211b401caa8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18103
06011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.1810306011
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3014277674
Short name T345
Test name
Test status
Simulation time 331695114294 ps
CPU time 3032.05 seconds
Started Jul 23 04:50:26 PM PDT 24
Finished Jul 23 05:41:12 PM PDT 24
Peak memory 289448 kb
Host smart-4a7b0044-9a0e-4dce-bbb4-8150d1c9d3e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014277674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3014277674
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2052995245
Short name T492
Test name
Test status
Simulation time 70324366988 ps
CPU time 2366.09 seconds
Started Jul 23 04:50:22 PM PDT 24
Finished Jul 23 05:30:01 PM PDT 24
Peak memory 288616 kb
Host smart-4f51ee6b-2526-4961-b8bb-1809cc2a0b73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052995245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2052995245
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1609453986
Short name T651
Test name
Test status
Simulation time 11374958602 ps
CPU time 116.59 seconds
Started Jul 23 04:50:21 PM PDT 24
Finished Jul 23 04:52:31 PM PDT 24
Peak memory 248576 kb
Host smart-e8331d04-7647-4738-942c-6e6bfb9fcb2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609453986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1609453986
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3507226957
Short name T655
Test name
Test status
Simulation time 2537427970 ps
CPU time 54.39 seconds
Started Jul 23 04:50:21 PM PDT 24
Finished Jul 23 04:51:28 PM PDT 24
Peak memory 256584 kb
Host smart-3e8c408a-db7d-43d0-ba2f-6fad5f118765
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35072
26957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3507226957
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.2363859752
Short name T706
Test name
Test status
Simulation time 2182854804 ps
CPU time 37.61 seconds
Started Jul 23 04:50:23 PM PDT 24
Finished Jul 23 04:51:16 PM PDT 24
Peak memory 255924 kb
Host smart-49db9ce6-05c8-40aa-9789-bbf852ba2770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23638
59752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.2363859752
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.218973504
Short name T278
Test name
Test status
Simulation time 1385379221 ps
CPU time 70.48 seconds
Started Jul 23 04:50:23 PM PDT 24
Finished Jul 23 04:51:48 PM PDT 24
Peak memory 248424 kb
Host smart-cc787656-4f19-454b-8fd7-f27bf139a2b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21897
3504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.218973504
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.726271242
Short name T520
Test name
Test status
Simulation time 101524186 ps
CPU time 3.36 seconds
Started Jul 23 04:50:24 PM PDT 24
Finished Jul 23 04:50:42 PM PDT 24
Peak memory 250560 kb
Host smart-57161baf-1f2e-4dda-9028-902d34db00d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72627
1242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.726271242
Directory /workspace/9.alert_handler_smoke/latest
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