Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T19,T43
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13058	0	0
DisabledNoTrigBkwd_A	2147483647	725609	0	0
DisabledNoTrigFwd_A	2147483647	1693045005	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13058	0	0
T2	3241	865	0	0
T5	264068	0	0	0
T6	188416	0	0	0
T7	223047	0	0	0
T19	2260	381	0	0
T20	200082	0	0	0
T21	90548	0	0	0
T22	7536	0	0	0
T23	190756	0	0	0
T24	67218	0	0	0
T43	1390	633	0	0
T109	0	338	0	0
T193	0	1327	0	0
T194	0	624	0	0
T195	0	1134	0	0
T196	0	469	0	0
T197	0	321	0	0
T198	0	330	0	0
T199	3229	740	0	0
T200	0	906	0	0
T201	0	238	0	0
T202	0	790	0	0
T203	0	947	0	0
T204	0	730	0	0
T205	0	1074	0	0
T206	0	236	0	0
T207	0	680	0	0
T208	0	295	0	0
T209	126906	0	0	0
T210	315596	0	0	0
T211	76015	0	0	0
T212	262731	0	0	0
T213	112698	0	0	0
T214	335176	0	0	0
T215	37876	0	0	0
T216	340136	0	0	0
T217	58118	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	725609	0	0
T1	1696522	1167	0	0
T2	9723	27	0	0
T3	3762940	399	0	0
T4	1621652	23	0	0
T5	528136	11171	0	0
T6	188416	0	0	0
T7	0	2318	0	0
T8	0	25	0	0
T14	0	1024	0	0
T19	4520	24	0	0
T20	400164	1429	0	0
T21	181096	118	0	0
T22	15072	0	0	0
T23	381512	19	0	0
T24	67218	8	0	0
T43	0	8	0	0
T44	0	3879	0	0
T45	0	21	0	0
T46	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1693045005	0	0
T1	3393044	1697275	0	0
T2	12964	8232	0	0
T3	3762940	2262344	0	0
T4	1621652	1615307	0	0
T5	528136	2416	0	0
T19	4520	2416	0	0
T20	400164	1024041	0	0
T21	181096	55114	0	0
T22	15072	13162	0	0
T23	381512	353283	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T199,T200,T204
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	735290138	2376	0	0
DisabledNoTrigBkwd_A	735290138	212826	0	0
DisabledNoTrigFwd_A	735290138	380892324	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	2376	0	0
T199	3229	740	0	0
T200	0	906	0	0
T204	0	730	0	0
T209	126906	0	0	0
T210	315596	0	0	0
T211	76015	0	0	0
T212	262731	0	0	0
T213	112698	0	0	0
T214	335176	0	0	0
T215	37876	0	0	0
T216	340136	0	0	0
T217	58118	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	212826	0	0
T1	848261	568	0	0
T2	3241	0	0	0
T3	940735	240	0	0
T4	405413	2	0	0
T5	132034	2088	0	0
T7	0	8	0	0
T19	1130	0	0	0
T20	100041	914	0	0
T21	45274	2	0	0
T22	3768	0	0	0
T23	95378	19	0	0
T24	0	5	0	0
T44	0	995	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	380892324	0	0
T1	848261	5859	0	0
T2	3241	2034	0	0
T3	940735	192827	0	0
T4	405413	403157	0	0
T5	132034	598	0	0
T19	1130	598	0	0
T20	100041	50797	0	0
T21	45274	5797	0	0
T22	3768	3685	0	0
T23	95378	67302	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T3,T4,T19

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T19,T193,T196
1	1	Covered	T3,T4,T19

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T3,T19,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T19

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	735290138	3262	0	0
DisabledNoTrigBkwd_A	735290138	164276	0	0
DisabledNoTrigFwd_A	735290138	456071259	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	3262	0	0
T5	132034	0	0	0
T6	94208	0	0	0
T7	223047	0	0	0
T19	1130	381	0	0
T20	100041	0	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	67218	0	0	0
T43	1390	0	0	0
T193	0	1327	0	0
T196	0	469	0	0
T202	0	790	0	0
T208	0	295	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	164276	0	0
T3	940735	3	0	0
T4	405413	11	0	0
T5	132034	2003	0	0
T6	94208	0	0	0
T8	0	7	0	0
T14	0	591	0	0
T19	1130	24	0	0
T20	100041	106	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	67218	0	0	0
T44	0	501	0	0
T45	0	1	0	0
T46	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	456071259	0	0
T1	848261	844139	0	0
T2	3241	2047	0	0
T3	940735	843748	0	0
T4	405413	403705	0	0
T5	132034	602	0	0
T19	1130	602	0	0
T20	100041	393283	0	0
T21	45274	2034	0	0
T22	3768	3685	0	0
T23	95378	95327	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T109,T195
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	735290138	5597	0	0
DisabledNoTrigBkwd_A	735290138	192801	0	0
DisabledNoTrigFwd_A	735290138	414381564	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	5597	0	0
T2	3241	865	0	0
T3	940735	0	0	0
T4	405413	0	0	0
T5	132034	0	0	0
T6	94208	0	0	0
T19	1130	0	0	0
T20	100041	0	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T109	0	338	0	0
T195	0	1134	0	0
T197	0	321	0	0
T201	0	238	0	0
T203	0	947	0	0
T205	0	1074	0	0
T207	0	680	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	192801	0	0
T2	3241	27	0	0
T3	940735	45	0	0
T4	405413	9	0	0
T5	132034	1743	0	0
T6	94208	0	0	0
T7	0	636	0	0
T8	0	18	0	0
T14	0	433	0	0
T19	1130	0	0	0
T20	100041	97	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T44	0	1999	0	0
T45	0	20	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	414381564	0	0
T1	848261	840938	0	0
T2	3241	2068	0	0
T3	940735	682208	0	0
T4	405413	403704	0	0
T5	132034	606	0	0
T19	1130	606	0	0
T20	100041	375031	0	0
T21	45274	45213	0	0
T22	3768	2107	0	0
T23	95378	95327	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T3,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T43,T194,T198
1	1	Covered	T1,T3,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	735290138	1823	0	0
DisabledNoTrigBkwd_A	735290138	155706	0	0
DisabledNoTrigFwd_A	735290138	441699858	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	1823	0	0
T8	136347	0	0	0
T14	486628	0	0	0
T43	1390	633	0	0
T44	794646	0	0	0
T45	17058	0	0	0
T46	24416	0	0	0
T65	58889	0	0	0
T66	16713	0	0	0
T75	66463	0	0	0
T81	13163	0	0	0
T194	0	624	0	0
T198	0	330	0	0
T206	0	236	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	155706	0	0
T1	848261	599	0	0
T2	3241	0	0	0
T3	940735	111	0	0
T4	405413	1	0	0
T5	132034	5337	0	0
T7	0	1674	0	0
T19	1130	0	0	0
T20	100041	312	0	0
T21	45274	116	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	0	3	0	0
T43	0	8	0	0
T44	0	384	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	441699858	0	0
T1	848261	6339	0	0
T2	3241	2083	0	0
T3	940735	543561	0	0
T4	405413	404741	0	0
T5	132034	610	0	0
T19	1130	610	0	0
T20	100041	204930	0	0
T21	45274	2070	0	0
T22	3768	3685	0	0
T23	95378	95327	0	0