Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	93.33	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.26	100.00	95.56	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T3,T4,T20
1	1	1	Covered	T3,T4,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T3,T24,T14
1	0	Covered	T23,T14,T18

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T23,T14,T18

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T25,T26
1	1	Covered	T3,T24,T14

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T2,T3,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T4,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T20

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T3,T4,T5

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T3,T4,T5
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T20,T27,T28
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T20,T29,T30
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T3,T5,T20
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T3,T5,T23
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T3,T4,T20
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T3,T4,T5
TimeoutSt->Phase0St	172	Covered	T3,T23,T24

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T23,T24
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T20,T27,T28
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T29,T30,T31
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T5,T20
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T3,T5,T23
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T4,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	883	0	0
CheckAccumTrig0_A	2147483647	2319	0	0
CheckAccumTrig1_A	2147483647	125	0	0
CheckClr_A	2147483647	1087	0	0
CheckEn_A	2147483647	1293601162	0	0
CheckPhase0_A	2147483647	2659	0	0
CheckPhase1_A	2147483647	2609	0	0
CheckPhase2_A	2147483647	2555	0	0
CheckPhase3_A	2147483647	2514	0	0
CheckTimeout0_A	2147483647	4327	0	0
CheckTimeoutSt1_A	2147483647	485438	0	0
CheckTimeoutSt2_A	2147483647	3941	0	0
CheckTimeoutStTrig_A	2147483647	258	0	0
ErrorStAllEscAsserted_A	2147483647	4401	0	0
ErrorStIsTerminal_A	2147483647	3681	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	883	0	0
T11	235572	158	0	0
T12	0	167	0	0
T13	0	137	0	0
T32	0	237	0	0
T33	0	184	0	0
T34	106204	0	0	0
T35	36848	0	0	0
T36	1974020	0	0	0
T37	303456	0	0	0
T38	1014724	0	0	0
T39	252972	0	0	0
T40	1191696	0	0	0
T41	683456	0	0	0
T42	493868	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2319	0	0
T1	1696522	2	0	0
T2	9723	1	0	0
T3	3762940	17	0	0
T4	1621652	3	0	0
T5	528136	6	0	0
T6	188416	0	0	0
T7	0	7	0	0
T8	0	2	0	0
T14	0	18	0	0
T19	4520	1	0	0
T20	400164	20	0	0
T21	181096	2	0	0
T22	15072	0	0	0
T23	381512	2	0	0
T24	67218	2	0	0
T43	0	1	0	0
T44	0	20	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	125	0	0
T6	94208	0	0	0
T7	223047	0	0	0
T14	486628	1	0	0
T18	503931	1	0	0
T23	95378	1	0	0
T24	67218	0	0	0
T39	0	1	0	0
T43	1390	0	0	0
T44	794646	0	0	0
T45	17058	0	0	0
T48	0	1	0	0
T49	449315	1	0	0
T50	61015	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	7	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	58889	0	0	0
T66	16713	0	0	0
T67	593597	0	0	0
T68	106641	0	0	0
T69	92831	0	0	0
T70	614416	0	0	0
T71	203972	0	0	0
T72	195945	0	0	0
T73	169052	0	0	0
T74	4285	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1087	0	0
T3	2822205	6	0	0
T4	1216239	1	0	0
T5	396102	1	0	0
T6	282624	0	0	0
T7	0	1	0	0
T8	136347	0	0	0
T14	486628	11	0	0
T19	3390	0	0	0
T20	300123	9	0	0
T21	135822	1	0	0
T22	11304	0	0	0
T23	286134	3	0	0
T24	201654	1	0	0
T25	0	1	0	0
T27	0	1	0	0
T30	0	1	0	0
T44	794646	3	0	0
T45	17058	0	0	0
T46	24416	3	0	0
T47	253411	0	0	0
T65	58889	0	0	0
T66	16713	2	0	0
T75	66463	2	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	2	0	0
T79	0	7	0	0
T80	0	1	0	0
T81	13163	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1293601162	0	0
T1	3393044	1694709	0	0
T2	12964	8232	0	0
T3	3762940	2097190	0	0
T4	1621652	430086	0	0
T5	528136	2416	0	0
T19	4520	2416	0	0
T20	400164	805659	0	0
T21	181096	55113	0	0
T22	15072	13159	0	0
T23	381512	353279	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2659	0	0
T1	1696522	2	0	0
T2	9723	1	0	0
T3	3762940	22	0	0
T4	1621652	4	0	0
T5	528136	6	0	0
T6	188416	0	0	0
T7	0	7	0	0
T8	0	1	0	0
T14	0	18	0	0
T19	4520	1	0	0
T20	400164	19	0	0
T21	181096	2	0	0
T22	15072	0	0	0
T23	381512	3	0	0
T24	67218	3	0	0
T43	0	1	0	0
T44	0	20	0	0
T45	0	2	0	0
T66	0	2	0	0
T75	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2609	0	0
T1	1696522	2	0	0
T2	9723	1	0	0
T3	3762940	21	0	0
T4	1621652	4	0	0
T5	528136	6	0	0
T6	188416	0	0	0
T7	0	7	0	0
T8	0	1	0	0
T14	0	18	0	0
T19	4520	1	0	0
T20	400164	18	0	0
T21	181096	2	0	0
T22	15072	0	0	0
T23	381512	3	0	0
T24	67218	3	0	0
T43	0	1	0	0
T44	0	20	0	0
T45	0	2	0	0
T66	0	2	0	0
T75	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2555	0	0
T1	1696522	2	0	0
T2	9723	1	0	0
T3	3762940	20	0	0
T4	1621652	4	0	0
T5	528136	5	0	0
T6	188416	0	0	0
T7	0	6	0	0
T8	0	1	0	0
T14	0	18	0	0
T19	4520	1	0	0
T20	400164	16	0	0
T21	181096	2	0	0
T22	15072	0	0	0
T23	381512	2	0	0
T24	67218	3	0	0
T43	0	1	0	0
T44	0	18	0	0
T45	0	2	0	0
T66	0	2	0	0
T75	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2514	0	0
T1	1696522	2	0	0
T2	9723	1	0	0
T3	3762940	19	0	0
T4	1621652	4	0	0
T5	528136	4	0	0
T6	188416	0	0	0
T7	0	6	0	0
T8	0	1	0	0
T14	0	18	0	0
T19	4520	1	0	0
T20	400164	16	0	0
T21	181096	2	0	0
T22	15072	0	0	0
T23	381512	1	0	0
T24	67218	3	0	0
T43	0	1	0	0
T44	0	18	0	0
T45	0	2	0	0
T66	0	2	0	0
T75	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4327	0	0
T3	3762940	23	0	0
T4	1621652	2	0	0
T5	528136	1	0	0
T6	376832	15	0	0
T14	0	6	0	0
T18	0	5	0	0
T19	4520	0	0	0
T20	400164	2	0	0
T21	181096	0	0	0
T22	15072	1	0	0
T23	381512	1	0	0
T24	268872	2	0	0
T27	0	4	0	0
T44	0	7	0	0
T45	0	5	0	0
T46	0	9	0	0
T66	0	6	0	0
T75	0	10	0	0
T76	0	1	0	0
T81	0	4	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	485438	0	0
T3	3762940	5019	0	0
T4	1621652	173	0	0
T5	528136	115	0	0
T6	376832	2260	0	0
T14	0	730	0	0
T17	0	149	0	0
T18	0	703	0	0
T19	4520	0	0	0
T20	400164	138	0	0
T21	181096	0	0	0
T22	15072	135	0	0
T23	381512	0	0	0
T24	268872	737	0	0
T27	0	1577	0	0
T44	0	504	0	0
T45	0	1133	0	0
T46	0	3598	0	0
T66	0	1258	0	0
T75	0	1034	0	0
T76	0	154	0	0
T81	0	188	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3941	0	0
T3	3762940	14	0	0
T4	1621652	1	0	0
T5	528136	1	0	0
T6	376832	10	0	0
T14	0	3	0	0
T17	0	1	0	0
T18	0	4	0	0
T19	4520	0	0	0
T20	400164	2	0	0
T21	181096	0	0	0
T22	15072	1	0	0
T23	381512	0	0	0
T24	268872	1	0	0
T27	0	2	0	0
T44	0	4	0	0
T45	0	1	0	0
T46	0	6	0	0
T48	0	4	0	0
T66	0	2	0	0
T75	0	6	0	0
T76	0	1	0	0
T79	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	258	0	0
T3	2822205	3	0	0
T4	1216239	0	0	0
T5	396102	0	0	0
T6	282624	0	0	0
T8	136347	0	0	0
T14	486628	1	0	0
T15	224500	0	0	0
T19	3390	0	0	0
T20	300123	0	0	0
T21	135822	0	0	0
T22	11304	0	0	0
T23	286134	0	0	0
T24	201654	1	0	0
T25	0	1	0	0
T27	0	1	0	0
T45	17058	1	0	0
T46	24416	3	0	0
T47	253411	0	0	0
T48	0	3	0	0
T52	0	2	0	0
T65	58889	0	0	0
T66	16713	2	0	0
T75	66463	3	0	0
T76	0	1	0	0
T81	13163	1	0	0
T83	0	2	0	0
T84	0	1	0	0
T85	0	4	0	0
T86	0	1	0	0
T87	0	3	0	0
T88	0	3	0	0
T89	0	6	0	0
T90	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4401	0	0
T11	235572	687	0	0
T12	0	763	0	0
T13	0	751	0	0
T32	0	1442	0	0
T33	0	758	0	0
T34	106204	0	0	0
T35	36848	0	0	0
T36	1974020	0	0	0
T37	303456	0	0	0
T38	1014724	0	0	0
T39	252972	0	0	0
T40	1191696	0	0	0
T41	683456	0	0	0
T42	493868	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3681	0	0
T11	235572	567	0	0
T12	0	643	0	0
T13	0	631	0	0
T32	0	1202	0	0
T33	0	638	0	0
T34	106204	0	0	0
T35	36848	0	0	0
T36	1974020	0	0	0
T37	303456	0	0	0
T38	1014724	0	0	0
T39	252972	0	0	0
T40	1191696	0	0	0
T41	683456	0	0	0
T42	493868	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3393044	3392688	0	0
T2	12964	12712	0	0
T3	3762940	3760048	0	0
T4	1621652	1621628	0	0
T5	528136	528116	0	0
T19	4520	4276	0	0
T20	400164	400128	0	0
T21	181096	180852	0	0
T22	15072	14740	0	0
T23	381512	381308	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3393044	3392688	0	0
T2	12964	12712	0	0
T3	3762940	3760048	0	0
T4	1621652	1621628	0	0
T5	528136	528116	0	0
T19	4520	4276	0	0
T20	400164	400128	0	0
T21	181096	180852	0	0
T22	15072	14740	0	0
T23	381512	381308	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T3,T20,T21
1	1	0	Covered	T3,T20,T22
1	1	1	Covered	T3,T5,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T5,T20
0	1	Covered	T3,T24,T75
1	0	Covered	T23,T14,T50

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T5,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T23,T14,T50

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T20
1	0	Not Covered
1	1	Covered	T3,T24,T75

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T20,T21

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T5,T23

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T20
1	Covered	T1,T4,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T20,T24

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T20,T23

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T5,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T4
Phase1St	198	Covered	T1,T3,T4
Phase2St	215	Covered	T1,T3,T4
Phase3St	233	Covered	T1,T3,T4
TerminalSt	249	Covered	T1,T3,T4
TimeoutSt	159	Covered	T3,T5,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T3,T4
IdleSt->TimeoutSt	159	Covered	T3,T5,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T28,T91,T87
Phase0St->Phase1St	198	Covered	T1,T3,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T31,T92,T50
Phase1St->Phase2St	215	Covered	T1,T3,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T5,T20,T23
Phase2St->Phase3St	233	Covered	T1,T3,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T23,T92,T68
Phase3St->TerminalSt	249	Covered	T1,T3,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T20,T21
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T5,T20
TimeoutSt->Phase0St	172	Covered	T3,T23,T24

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T23,T24
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T28,T91,T71
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T31,T92,T50
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T20,T23
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T23,T92,T68
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T20,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	735290138	232	0	0
CheckAccumTrig0_A	735290138	850	0	0
CheckAccumTrig1_A	735290138	56	0	0
CheckClr_A	735290138	430	0	0
CheckEn_A	735097377	264250821	0	0
CheckPhase0_A	735290138	962	0	0
CheckPhase1_A	735290138	947	0	0
CheckPhase2_A	735290138	918	0	0
CheckPhase3_A	735290138	897	0	0
CheckTimeout0_A	735290138	1323	0	0
CheckTimeoutSt1_A	735290138	157969	0	0
CheckTimeoutSt2_A	735290138	1193	0	0
CheckTimeoutStTrig_A	735290138	74	0	0
ErrorStAllEscAsserted_A	735290138	1101	0	0
ErrorStIsTerminal_A	735290138	921	0	0
EscStateOut_A	735095636	735029897	0	0
u_state_regs_A	735290138	735148206	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	232	0	0
T11	58893	24	0	0
T12	0	39	0	0
T13	0	28	0	0
T32	0	84	0	0
T33	0	57	0	0
T34	26551	0	0	0
T35	9212	0	0	0
T36	493505	0	0	0
T37	75864	0	0	0
T38	253681	0	0	0
T39	63243	0	0	0
T40	297924	0	0	0
T41	170864	0	0	0
T42	123467	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	850	0	0
T1	848261	1	0	0
T2	3241	0	0	0
T3	940735	6	0	0
T4	405413	1	0	0
T5	132034	2	0	0
T7	0	2	0	0
T19	1130	0	0	0
T20	100041	10	0	0
T21	45274	1	0	0
T22	3768	0	0	0
T23	95378	2	0	0
T24	0	1	0	0
T44	0	9	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	56	0	0
T6	94208	0	0	0
T7	223047	0	0	0
T14	486628	1	0	0
T23	95378	1	0	0
T24	67218	0	0	0
T39	0	1	0	0
T43	1390	0	0	0
T44	794646	0	0	0
T45	17058	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	4	0	0
T65	58889	0	0	0
T66	16713	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	430	0	0
T3	940735	1	0	0
T4	405413	0	0	0
T5	132034	1	0	0
T6	94208	0	0	0
T7	0	1	0	0
T19	1130	0	0	0
T20	100041	7	0	0
T21	45274	1	0	0
T22	3768	0	0	0
T23	95378	3	0	0
T24	67218	1	0	0
T44	0	2	0	0
T46	0	3	0	0
T77	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735097377	264250821	0	0
T1	848261	3295	0	0
T2	3241	2034	0	0
T3	940735	127522	0	0
T4	405413	3091	0	0
T5	132034	598	0	0
T19	1130	598	0	0
T20	100041	28595	0	0
T21	45274	5797	0	0
T22	3768	3684	0	0
T23	95378	67301	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	962	0	0
T1	848261	1	0	0
T2	3241	0	0	0
T3	940735	8	0	0
T4	405413	1	0	0
T5	132034	2	0	0
T7	0	2	0	0
T19	1130	0	0	0
T20	100041	10	0	0
T21	45274	1	0	0
T22	3768	0	0	0
T23	95378	3	0	0
T24	0	2	0	0
T44	0	9	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	947	0	0
T1	848261	1	0	0
T2	3241	0	0	0
T3	940735	8	0	0
T4	405413	1	0	0
T5	132034	2	0	0
T7	0	2	0	0
T19	1130	0	0	0
T20	100041	10	0	0
T21	45274	1	0	0
T22	3768	0	0	0
T23	95378	3	0	0
T24	0	2	0	0
T44	0	9	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	918	0	0
T1	848261	1	0	0
T2	3241	0	0	0
T3	940735	8	0	0
T4	405413	1	0	0
T5	132034	1	0	0
T7	0	2	0	0
T19	1130	0	0	0
T20	100041	8	0	0
T21	45274	1	0	0
T22	3768	0	0	0
T23	95378	2	0	0
T24	0	2	0	0
T44	0	8	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	897	0	0
T1	848261	1	0	0
T2	3241	0	0	0
T3	940735	8	0	0
T4	405413	1	0	0
T5	132034	1	0	0
T7	0	2	0	0
T19	1130	0	0	0
T20	100041	8	0	0
T21	45274	1	0	0
T22	3768	0	0	0
T23	95378	1	0	0
T24	0	2	0	0
T44	0	8	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	1323	0	0
T3	940735	8	0	0
T4	405413	0	0	0
T5	132034	1	0	0
T6	94208	0	0	0
T14	0	3	0	0
T19	1130	0	0	0
T20	100041	1	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	1	0	0
T24	67218	2	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	9	0	0
T75	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	157969	0	0
T3	940735	1983	0	0
T4	405413	0	0	0
T5	132034	115	0	0
T6	94208	0	0	0
T14	0	275	0	0
T17	0	149	0	0
T19	1130	0	0	0
T20	100041	64	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	67218	737	0	0
T44	0	247	0	0
T45	0	451	0	0
T46	0	3598	0	0
T75	0	43	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	1193	0	0
T3	940735	6	0	0
T4	405413	0	0	0
T5	132034	1	0	0
T6	94208	0	0	0
T14	0	2	0	0
T17	0	1	0	0
T19	1130	0	0	0
T20	100041	1	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	67218	1	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	6	0	0
T82	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	74	0	0
T3	940735	2	0	0
T4	405413	0	0	0
T5	132034	0	0	0
T6	94208	0	0	0
T19	1130	0	0	0
T20	100041	0	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	67218	1	0	0
T46	0	3	0	0
T75	0	1	0	0
T83	0	1	0	0
T85	0	1	0	0
T87	0	2	0	0
T88	0	2	0	0
T89	0	6	0	0
T90	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	1101	0	0
T11	58893	168	0	0
T12	0	181	0	0
T13	0	188	0	0
T32	0	351	0	0
T33	0	213	0	0
T34	26551	0	0	0
T35	9212	0	0	0
T36	493505	0	0	0
T37	75864	0	0	0
T38	253681	0	0	0
T39	63243	0	0	0
T40	297924	0	0	0
T41	170864	0	0	0
T42	123467	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	921	0	0
T11	58893	138	0	0
T12	0	151	0	0
T13	0	158	0	0
T32	0	291	0	0
T33	0	183	0	0
T34	26551	0	0	0
T35	9212	0	0	0
T36	493505	0	0	0
T37	75864	0	0	0
T38	253681	0	0	0
T39	63243	0	0	0
T40	297924	0	0	0
T41	170864	0	0	0
T42	123467	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735095636	735029897	0	0
T1	848261	848172	0	0
T2	3241	3178	0	0
T3	940735	940012	0	0
T4	405413	405407	0	0
T5	132034	132029	0	0
T19	1130	1069	0	0
T20	100041	100032	0	0
T21	45274	45213	0	0
T22	3768	3685	0	0
T23	95378	95327	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	735148206	0	0
T1	848261	848172	0	0
T2	3241	3178	0	0
T3	940735	940012	0	0
T4	405413	405407	0	0
T5	132034	132029	0	0
T19	1130	1069	0	0
T20	100041	100032	0	0
T21	45274	45213	0	0
T22	3768	3685	0	0
T23	95378	95327	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T4,T19
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T19

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T3,T4,T19

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T19,T20,T21
1	1	0	Covered	T3,T20,T22
1	1	1	Covered	T3,T6,T14

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T14
0	1	Covered	T14,T45,T66
1	0	Covered	T49,T54,T57

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T6,T14
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T49,T54,T57

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T14
1	0	Not Covered
1	1	Covered	T14,T45,T66

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T5,T20
1	Covered	T4,T19,T20

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T19
1	Covered	T5,T14,T45

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T19
1	Covered	T20,T14,T66

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T19,T5
1	Covered	T3,T20,T44

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T4,T19,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T19,T5,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T19,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T19,T20,T44

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T3,T4,T19
Phase1St	198	Covered	T3,T4,T19
Phase2St	215	Covered	T3,T4,T19
Phase3St	233	Covered	T3,T4,T19
TerminalSt	249	Covered	T3,T4,T19
TimeoutSt	159	Covered	T3,T6,T14

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T3,T4,T19
IdleSt->TimeoutSt	159	Covered	T3,T6,T14
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T27,T57,T93
Phase0St->Phase1St	198	Covered	T3,T4,T19
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T30,T88,T94
Phase1St->Phase2St	215	Covered	T3,T4,T19
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T95,T96
Phase2St->Phase3St	233	Covered	T3,T4,T19
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T49,T97,T98
Phase3St->TerminalSt	249	Covered	T3,T4,T19
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T20,T44
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T6,T14
TimeoutSt->Phase0St	172	Covered	T14,T45,T66

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T19
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T14
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T14,T45,T66
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T14
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T14
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T27,T57,T99
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T3,T4,T19
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T30,T88,T94
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T3,T4,T19
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T95,T96
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T3,T4,T19
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T49,T97,T98
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T3,T4,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T44,T14,T66
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T3,T4,T19
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	735290138	234	0	0
CheckAccumTrig0_A	735290138	482	0	0
CheckAccumTrig1_A	735290138	26	0	0
CheckClr_A	735290138	223	0	0
CheckEn_A	735097377	361417637	0	0
CheckPhase0_A	735290138	558	0	0
CheckPhase1_A	735290138	550	0	0
CheckPhase2_A	735290138	548	0	0
CheckPhase3_A	735290138	543	0	0
CheckTimeout0_A	735290138	1290	0	0
CheckTimeoutSt1_A	735290138	129144	0	0
CheckTimeoutSt2_A	735290138	1206	0	0
CheckTimeoutStTrig_A	735290138	57	0	0
ErrorStAllEscAsserted_A	735290138	1110	0	0
ErrorStIsTerminal_A	735290138	930	0	0
EscStateOut_A	735095636	735029897	0	0
u_state_regs_A	735290138	735148206	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	234	0	0
T11	58893	43	0	0
T12	0	41	0	0
T13	0	44	0	0
T32	0	59	0	0
T33	0	47	0	0
T34	26551	0	0	0
T35	9212	0	0	0
T36	493505	0	0	0
T37	75864	0	0	0
T38	253681	0	0	0
T39	63243	0	0	0
T40	297924	0	0	0
T41	170864	0	0	0
T42	123467	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	482	0	0
T3	940735	1	0	0
T4	405413	1	0	0
T5	132034	1	0	0
T6	94208	0	0	0
T8	0	1	0	0
T14	0	9	0	0
T19	1130	1	0	0
T20	100041	4	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	67218	0	0	0
T44	0	3	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	26	0	0
T49	449315	1	0	0
T50	61015	0	0	0
T54	0	1	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T67	593597	0	0	0
T68	106641	0	0	0
T69	92831	0	0	0
T70	614416	0	0	0
T71	203972	0	0	0
T72	195945	0	0	0
T73	169052	0	0	0
T74	4285	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	223	0	0
T8	136347	0	0	0
T14	486628	6	0	0
T25	0	1	0	0
T27	0	1	0	0
T30	0	1	0	0
T44	794646	1	0	0
T45	17058	0	0	0
T46	24416	0	0	0
T47	253411	0	0	0
T65	58889	0	0	0
T66	16713	2	0	0
T75	66463	0	0	0
T76	0	1	0	0
T78	0	2	0	0
T79	0	3	0	0
T80	0	1	0	0
T81	13163	0	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735097377	361417637	0	0
T1	848261	844138	0	0
T2	3241	2047	0	0
T3	940735	748259	0	0
T4	405413	3109	0	0
T5	132034	602	0	0
T19	1130	602	0	0
T20	100041	200925	0	0
T21	45274	2034	0	0
T22	3768	3684	0	0
T23	95378	95326	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	558	0	0
T3	940735	1	0	0
T4	405413	1	0	0
T5	132034	1	0	0
T6	94208	0	0	0
T8	0	1	0	0
T14	0	10	0	0
T19	1130	1	0	0
T20	100041	4	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	67218	0	0	0
T44	0	3	0	0
T45	0	1	0	0
T66	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	550	0	0
T3	940735	1	0	0
T4	405413	1	0	0
T5	132034	1	0	0
T6	94208	0	0	0
T8	0	1	0	0
T14	0	10	0	0
T19	1130	1	0	0
T20	100041	4	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	67218	0	0	0
T44	0	3	0	0
T45	0	1	0	0
T66	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	548	0	0
T3	940735	1	0	0
T4	405413	1	0	0
T5	132034	1	0	0
T6	94208	0	0	0
T8	0	1	0	0
T14	0	10	0	0
T19	1130	1	0	0
T20	100041	4	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	67218	0	0	0
T44	0	3	0	0
T45	0	1	0	0
T66	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	543	0	0
T3	940735	1	0	0
T4	405413	1	0	0
T5	132034	1	0	0
T6	94208	0	0	0
T8	0	1	0	0
T14	0	10	0	0
T19	1130	1	0	0
T20	100041	4	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	67218	0	0	0
T44	0	3	0	0
T45	0	1	0	0
T66	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	1290	0	0
T3	940735	5	0	0
T4	405413	0	0	0
T5	132034	0	0	0
T6	94208	7	0	0
T14	0	2	0	0
T18	0	1	0	0
T19	1130	0	0	0
T20	100041	0	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	67218	0	0	0
T27	0	2	0	0
T45	0	1	0	0
T66	0	4	0	0
T75	0	5	0	0
T76	0	1	0	0
T81	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	129144	0	0
T3	940735	729	0	0
T4	405413	0	0	0
T5	132034	0	0	0
T6	94208	1044	0	0
T14	0	282	0	0
T18	0	144	0	0
T19	1130	0	0	0
T20	100041	0	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	67218	0	0	0
T27	0	763	0	0
T45	0	211	0	0
T66	0	1036	0	0
T75	0	620	0	0
T76	0	154	0	0
T81	0	39	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	1206	0	0
T3	940735	5	0	0
T4	405413	0	0	0
T5	132034	0	0	0
T6	94208	7	0	0
T14	0	1	0	0
T18	0	1	0	0
T19	1130	0	0	0
T20	100041	0	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	67218	0	0	0
T27	0	1	0	0
T66	0	2	0	0
T75	0	5	0	0
T76	0	1	0	0
T79	0	1	0	0
T81	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	57	0	0
T8	136347	0	0	0
T14	486628	1	0	0
T15	224500	0	0	0
T27	0	1	0	0
T45	17058	1	0	0
T46	24416	0	0	0
T47	253411	0	0	0
T52	0	2	0	0
T65	58889	0	0	0
T66	16713	2	0	0
T75	66463	0	0	0
T81	13163	0	0	0
T83	0	1	0	0
T84	0	1	0	0
T86	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	1110	0	0
T11	58893	160	0	0
T12	0	202	0	0
T13	0	196	0	0
T32	0	363	0	0
T33	0	189	0	0
T34	26551	0	0	0
T35	9212	0	0	0
T36	493505	0	0	0
T37	75864	0	0	0
T38	253681	0	0	0
T39	63243	0	0	0
T40	297924	0	0	0
T41	170864	0	0	0
T42	123467	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	930	0	0
T11	58893	130	0	0
T12	0	172	0	0
T13	0	166	0	0
T32	0	303	0	0
T33	0	159	0	0
T34	26551	0	0	0
T35	9212	0	0	0
T36	493505	0	0	0
T37	75864	0	0	0
T38	253681	0	0	0
T39	63243	0	0	0
T40	297924	0	0	0
T41	170864	0	0	0
T42	123467	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735095636	735029897	0	0
T1	848261	848172	0	0
T2	3241	3178	0	0
T3	940735	940012	0	0
T4	405413	405407	0	0
T5	132034	132029	0	0
T19	1130	1069	0	0
T20	100041	100032	0	0
T21	45274	45213	0	0
T22	3768	3685	0	0
T23	95378	95327	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	735148206	0	0
T1	848261	848172	0	0
T2	3241	3178	0	0
T3	940735	940012	0	0
T4	405413	405407	0	0
T5	132034	132029	0	0
T19	1130	1069	0	0
T20	100041	100032	0	0
T21	45274	45213	0	0
T22	3768	3685	0	0
T23	95378	95327	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T2,T3,T20
1	1	0	Covered	T3,T4,T20
1	1	1	Covered	T3,T4,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T20
0	1	Covered	T3,T75,T81
1	0	Covered	T18,T48,T100

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T4,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T18,T48,T100

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T20
1	0	Covered	T26
1	1	Covered	T3,T75,T81

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T2,T20,T7

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T20
1	Covered	T3,T4,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T44,T14,T75

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T4
1	Covered	T3,T14,T75

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T5,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T2,T3,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T4
Phase1St	198	Covered	T2,T3,T4
Phase2St	215	Covered	T2,T3,T4
Phase3St	233	Covered	T2,T3,T4
TerminalSt	249	Covered	T2,T3,T4
TimeoutSt	159	Covered	T3,T4,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T2,T3,T4
IdleSt->TimeoutSt	159	Covered	T3,T4,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T20,T101,T58
Phase0St->Phase1St	198	Covered	T2,T3,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T20,T29,T49
Phase1St->Phase2St	215	Covered	T2,T3,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T3,T85,T97
Phase2St->Phase3St	233	Covered	T2,T3,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T79,T49,T52
Phase3St->TerminalSt	249	Covered	T2,T3,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T4,T20
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T4,T20
TimeoutSt->Phase0St	172	Covered	T3,T75,T81

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T75,T81
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T20,T101,T96
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T29,T102,T103
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T3,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T3,T85,T97
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T3,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T79,T49,T52
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T3,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T4,T20
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	735290138	240	0	0
CheckAccumTrig0_A	735290138	503	0	0
CheckAccumTrig1_A	735290138	19	0	0
CheckClr_A	735290138	200	0	0
CheckEn_A	735097377	319104007	0	0
CheckPhase0_A	735290138	568	0	0
CheckPhase1_A	735290138	554	0	0
CheckPhase2_A	735290138	547	0	0
CheckPhase3_A	735290138	542	0	0
CheckTimeout0_A	735290138	849	0	0
CheckTimeoutSt1_A	735290138	95946	0	0
CheckTimeoutSt2_A	735290138	773	0	0
CheckTimeoutStTrig_A	735290138	55	0	0
ErrorStAllEscAsserted_A	735290138	1128	0	0
ErrorStIsTerminal_A	735290138	948	0	0
EscStateOut_A	735095636	735029897	0	0
u_state_regs_A	735290138	735148206	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	240	0	0
T11	58893	57	0	0
T12	0	38	0	0
T13	0	49	0	0
T32	0	55	0	0
T33	0	41	0	0
T34	26551	0	0	0
T35	9212	0	0	0
T36	493505	0	0	0
T37	75864	0	0	0
T38	253681	0	0	0
T39	63243	0	0	0
T40	297924	0	0	0
T41	170864	0	0	0
T42	123467	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	503	0	0
T2	3241	1	0	0
T3	940735	6	0	0
T4	405413	1	0	0
T5	132034	1	0	0
T6	94208	0	0	0
T7	0	1	0	0
T8	0	1	0	0
T14	0	8	0	0
T19	1130	0	0	0
T20	100041	4	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T44	0	3	0	0
T45	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	19	0	0
T9	667823	0	0	0
T18	503931	1	0	0
T29	3785	0	0	0
T48	84125	1	0	0
T57	0	1	0	0
T76	598954	0	0	0
T77	18540	0	0	0
T93	0	1	0	0
T100	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T109	2571	0	0	0
T110	287437	0	0	0
T111	159656	0	0	0
T112	269106	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	200	0	0
T3	940735	5	0	0
T4	405413	1	0	0
T5	132034	0	0	0
T6	94208	0	0	0
T14	0	5	0	0
T19	1130	0	0	0
T20	100041	2	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	67218	0	0	0
T29	0	1	0	0
T31	0	3	0	0
T48	0	5	0	0
T75	0	2	0	0
T79	0	4	0	0
T113	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735097377	319104007	0	0
T1	848261	840937	0	0
T2	3241	2068	0	0
T3	940735	682202	0	0
T4	405413	403704	0	0
T5	132034	606	0	0
T19	1130	606	0	0
T20	100041	371212	0	0
T21	45274	45212	0	0
T22	3768	2107	0	0
T23	95378	95326	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	568	0	0
T2	3241	1	0	0
T3	940735	7	0	0
T4	405413	1	0	0
T5	132034	1	0	0
T6	94208	0	0	0
T7	0	1	0	0
T14	0	8	0	0
T19	1130	0	0	0
T20	100041	3	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T44	0	3	0	0
T45	0	1	0	0
T75	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	554	0	0
T2	3241	1	0	0
T3	940735	7	0	0
T4	405413	1	0	0
T5	132034	1	0	0
T6	94208	0	0	0
T7	0	1	0	0
T14	0	8	0	0
T19	1130	0	0	0
T20	100041	2	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T44	0	3	0	0
T45	0	1	0	0
T75	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	547	0	0
T2	3241	1	0	0
T3	940735	6	0	0
T4	405413	1	0	0
T5	132034	1	0	0
T6	94208	0	0	0
T7	0	1	0	0
T14	0	8	0	0
T19	1130	0	0	0
T20	100041	2	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T44	0	3	0	0
T45	0	1	0	0
T75	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	542	0	0
T2	3241	1	0	0
T3	940735	6	0	0
T4	405413	1	0	0
T5	132034	1	0	0
T6	94208	0	0	0
T7	0	1	0	0
T14	0	8	0	0
T19	1130	0	0	0
T20	100041	2	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T44	0	3	0	0
T45	0	1	0	0
T75	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	849	0	0
T3	940735	4	0	0
T4	405413	1	0	0
T5	132034	0	0	0
T6	94208	3	0	0
T18	0	4	0	0
T19	1130	0	0	0
T20	100041	1	0	0
T21	45274	0	0	0
T22	3768	1	0	0
T23	95378	0	0	0
T24	67218	0	0	0
T27	0	1	0	0
T44	0	1	0	0
T75	0	3	0	0
T81	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	95946	0	0
T3	940735	1422	0	0
T4	405413	171	0	0
T5	132034	0	0	0
T6	94208	497	0	0
T18	0	559	0	0
T19	1130	0	0	0
T20	100041	74	0	0
T21	45274	0	0	0
T22	3768	135	0	0
T23	95378	0	0	0
T24	67218	0	0	0
T27	0	751	0	0
T44	0	63	0	0
T75	0	246	0	0
T81	0	35	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	773	0	0
T3	940735	3	0	0
T4	405413	1	0	0
T5	132034	0	0	0
T6	94208	3	0	0
T18	0	3	0	0
T19	1130	0	0	0
T20	100041	1	0	0
T21	45274	0	0	0
T22	3768	1	0	0
T23	95378	0	0	0
T24	67218	0	0	0
T27	0	1	0	0
T44	0	1	0	0
T48	0	4	0	0
T75	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	55	0	0
T3	940735	1	0	0
T4	405413	0	0	0
T5	132034	0	0	0
T6	94208	0	0	0
T19	1130	0	0	0
T20	100041	0	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	67218	0	0	0
T25	0	1	0	0
T28	0	1	0	0
T48	0	3	0	0
T75	0	2	0	0
T76	0	1	0	0
T81	0	1	0	0
T85	0	3	0	0
T114	0	1	0	0
T115	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	1128	0	0
T11	58893	191	0	0
T12	0	188	0	0
T13	0	193	0	0
T32	0	384	0	0
T33	0	172	0	0
T34	26551	0	0	0
T35	9212	0	0	0
T36	493505	0	0	0
T37	75864	0	0	0
T38	253681	0	0	0
T39	63243	0	0	0
T40	297924	0	0	0
T41	170864	0	0	0
T42	123467	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	948	0	0
T11	58893	161	0	0
T12	0	158	0	0
T13	0	163	0	0
T32	0	324	0	0
T33	0	142	0	0
T34	26551	0	0	0
T35	9212	0	0	0
T36	493505	0	0	0
T37	75864	0	0	0
T38	253681	0	0	0
T39	63243	0	0	0
T40	297924	0	0	0
T41	170864	0	0	0
T42	123467	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735095636	735029897	0	0
T1	848261	848172	0	0
T2	3241	3178	0	0
T3	940735	940012	0	0
T4	405413	405407	0	0
T5	132034	132029	0	0
T19	1130	1069	0	0
T20	100041	100032	0	0
T21	45274	45213	0	0
T22	3768	3685	0	0
T23	95378	95327	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	735148206	0	0
T1	848261	848172	0	0
T2	3241	3178	0	0
T3	940735	940012	0	0
T4	405413	405407	0	0
T5	132034	132029	0	0
T19	1130	1069	0	0
T20	100041	100032	0	0
T21	45274	45213	0	0
T22	3768	3685	0	0
T23	95378	95327	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T4,T5
1	0	1	Covered	T1,T3,T20
1	1	0	Covered	T3,T20,T22
1	1	1	Covered	T3,T4,T6

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T6
0	1	Covered	T3,T14,T66
1	0	Covered	T4,T45,T76

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T4,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T45,T76

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T25
1	1	Covered	T3,T14,T66

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T20,T7

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T4
1	Covered	T3,T24,T8

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T4,T5,T14

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T3,T4,T5
1	Covered	T1,T3,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T11,T12,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T5,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T5,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T3,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T11,T12,T13
1	0	Covered	T1,T3,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T11,T12,T13
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T4
Phase1St	198	Covered	T1,T3,T4
Phase2St	215	Covered	T1,T3,T4
Phase3St	233	Covered	T1,T3,T4
TerminalSt	249	Covered	T1,T3,T4
TimeoutSt	159	Covered	T3,T4,T6

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T11,T12,T13
IdleSt->Phase0St	152	Covered	T1,T3,T5
IdleSt->TimeoutSt	159	Covered	T3,T4,T6
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T116,T57,T117
Phase0St->Phase1St	198	Covered	T1,T3,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T3,T100,T85
Phase1St->Phase2St	215	Covered	T1,T3,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T7,T44,T118
Phase2St->Phase3St	233	Covered	T1,T3,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T3,T5,T119
Phase3St->TerminalSt	249	Covered	T1,T3,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T20,T24
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T6,T44
TimeoutSt->Phase0St	172	Covered	T3,T4,T14

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T6
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T14
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T6
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T6,T44
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T116,T57,T117
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T3,T100,T85
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T7,T44,T118
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T3,T5,T119
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T24,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T11,T12,T13

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T13
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	735290138	177	0	0
CheckAccumTrig0_A	735290138	484	0	0
CheckAccumTrig1_A	735290138	24	0	0
CheckClr_A	735290138	234	0	0
CheckEn_A	735097377	348828697	0	0
CheckPhase0_A	735290138	571	0	0
CheckPhase1_A	735290138	558	0	0
CheckPhase2_A	735290138	542	0	0
CheckPhase3_A	735290138	532	0	0
CheckTimeout0_A	735290138	865	0	0
CheckTimeoutSt1_A	735290138	102379	0	0
CheckTimeoutSt2_A	735290138	769	0	0
CheckTimeoutStTrig_A	735290138	72	0	0
ErrorStAllEscAsserted_A	735290138	1062	0	0
ErrorStIsTerminal_A	735290138	882	0	0
EscStateOut_A	735095636	735029897	0	0
u_state_regs_A	735290138	735148206	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	177	0	0
T11	58893	34	0	0
T12	0	49	0	0
T13	0	16	0	0
T32	0	39	0	0
T33	0	39	0	0
T34	26551	0	0	0
T35	9212	0	0	0
T36	493505	0	0	0
T37	75864	0	0	0
T38	253681	0	0	0
T39	63243	0	0	0
T40	297924	0	0	0
T41	170864	0	0	0
T42	123467	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	484	0	0
T1	848261	1	0	0
T2	3241	0	0	0
T3	940735	4	0	0
T4	405413	0	0	0
T5	132034	2	0	0
T7	0	4	0	0
T14	0	1	0	0
T19	1130	0	0	0
T20	100041	2	0	0
T21	45274	1	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	0	1	0	0
T43	0	1	0	0
T44	0	5	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	24	0	0
T4	405413	1	0	0
T5	132034	0	0	0
T6	94208	0	0	0
T7	223047	0	0	0
T19	1130	0	0	0
T20	100041	0	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	67218	0	0	0
T28	0	1	0	0
T31	0	1	0	0
T45	0	1	0	0
T52	0	1	0	0
T76	0	1	0	0
T79	0	1	0	0
T100	0	1	0	0
T120	0	1	0	0
T121	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	234	0	0
T3	940735	4	0	0
T4	405413	0	0	0
T5	132034	1	0	0
T6	94208	0	0	0
T7	0	3	0	0
T16	0	1	0	0
T19	1130	0	0	0
T20	100041	0	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	67218	1	0	0
T44	0	3	0	0
T45	0	1	0	0
T46	0	1	0	0
T66	0	1	0	0
T112	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735097377	348828697	0	0
T1	848261	6339	0	0
T2	3241	2083	0	0
T3	940735	539207	0	0
T4	405413	20182	0	0
T5	132034	610	0	0
T19	1130	610	0	0
T20	100041	204927	0	0
T21	45274	2070	0	0
T22	3768	3684	0	0
T23	95378	95326	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	571	0	0
T1	848261	1	0	0
T2	3241	0	0	0
T3	940735	6	0	0
T4	405413	1	0	0
T5	132034	2	0	0
T7	0	4	0	0
T19	1130	0	0	0
T20	100041	2	0	0
T21	45274	1	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	0	1	0	0
T43	0	1	0	0
T44	0	5	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	558	0	0
T1	848261	1	0	0
T2	3241	0	0	0
T3	940735	5	0	0
T4	405413	1	0	0
T5	132034	2	0	0
T7	0	4	0	0
T19	1130	0	0	0
T20	100041	2	0	0
T21	45274	1	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	0	1	0	0
T43	0	1	0	0
T44	0	5	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	542	0	0
T1	848261	1	0	0
T2	3241	0	0	0
T3	940735	5	0	0
T4	405413	1	0	0
T5	132034	2	0	0
T7	0	3	0	0
T19	1130	0	0	0
T20	100041	2	0	0
T21	45274	1	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	0	1	0	0
T43	0	1	0	0
T44	0	4	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	532	0	0
T1	848261	1	0	0
T2	3241	0	0	0
T3	940735	4	0	0
T4	405413	1	0	0
T5	132034	1	0	0
T7	0	3	0	0
T19	1130	0	0	0
T20	100041	2	0	0
T21	45274	1	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	0	1	0	0
T43	0	1	0	0
T44	0	4	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	865	0	0
T3	940735	6	0	0
T4	405413	1	0	0
T5	132034	0	0	0
T6	94208	5	0	0
T14	0	1	0	0
T19	1130	0	0	0
T20	100041	0	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	67218	0	0	0
T27	0	1	0	0
T44	0	3	0	0
T45	0	3	0	0
T66	0	2	0	0
T75	0	1	0	0
T81	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	102379	0	0
T3	940735	885	0	0
T4	405413	2	0	0
T5	132034	0	0	0
T6	94208	719	0	0
T14	0	173	0	0
T19	1130	0	0	0
T20	100041	0	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	67218	0	0	0
T27	0	63	0	0
T44	0	194	0	0
T45	0	471	0	0
T66	0	222	0	0
T75	0	125	0	0
T81	0	114	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	769	0	0
T3	940735	4	0	0
T4	405413	0	0	0
T5	132034	0	0	0
T6	94208	5	0	0
T19	1130	0	0	0
T20	100041	0	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	67218	0	0	0
T31	0	2	0	0
T44	0	3	0	0
T45	0	2	0	0
T66	0	1	0	0
T75	0	1	0	0
T81	0	2	0	0
T82	0	1	0	0
T122	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	72	0	0
T3	940735	2	0	0
T4	405413	0	0	0
T5	132034	0	0	0
T6	94208	0	0	0
T14	0	1	0	0
T19	1130	0	0	0
T20	100041	0	0	0
T21	45274	0	0	0
T22	3768	0	0	0
T23	95378	0	0	0
T24	67218	0	0	0
T27	0	1	0	0
T31	0	2	0	0
T66	0	1	0	0
T76	0	1	0	0
T83	0	1	0	0
T85	0	2	0	0
T100	0	4	0	0
T123	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	1062	0	0
T11	58893	168	0	0
T12	0	192	0	0
T13	0	174	0	0
T32	0	344	0	0
T33	0	184	0	0
T34	26551	0	0	0
T35	9212	0	0	0
T36	493505	0	0	0
T37	75864	0	0	0
T38	253681	0	0	0
T39	63243	0	0	0
T40	297924	0	0	0
T41	170864	0	0	0
T42	123467	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	882	0	0
T11	58893	138	0	0
T12	0	162	0	0
T13	0	144	0	0
T32	0	284	0	0
T33	0	154	0	0
T34	26551	0	0	0
T35	9212	0	0	0
T36	493505	0	0	0
T37	75864	0	0	0
T38	253681	0	0	0
T39	63243	0	0	0
T40	297924	0	0	0
T41	170864	0	0	0
T42	123467	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735095636	735029897	0	0
T1	848261	848172	0	0
T2	3241	3178	0	0
T3	940735	940012	0	0
T4	405413	405407	0	0
T5	132034	132029	0	0
T19	1130	1069	0	0
T20	100041	100032	0	0
T21	45274	45213	0	0
T22	3768	3685	0	0
T23	95378	95327	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	735290138	735148206	0	0
T1	848261	848172	0	0
T2	3241	3178	0	0
T3	940735	940012	0	0
T4	405413	405407	0	0
T5	132034	132029	0	0
T19	1130	1069	0	0
T20	100041	100032	0	0
T21	45274	45213	0	0
T22	3768	3685	0	0
T23	95378	95327	0	0