Module Definition
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Module Instance : tb.dut.u_ping_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_prim_double_lfsr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_ping_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_prim_double_lfsr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_lfsr
TotalCoveredPercent
Totals 5 5 100.00
Total Bits 134 134 100.00
Total Bits 0->1 67 67 100.00
Total Bits 1->0 67 67 100.00

Ports 5 5 100.00
Port Bits 134 134 100.00
Port Bits 0->1 67 67 100.00
Port Bits 1->0 67 67 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T20,T44 Yes T1,T2,T3 INPUT
seed_en_i Unreachable Unreachable Unreachable INPUT
seed_i[31:0] Unreachable Unreachable Unreachable INPUT
lfsr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
entropy_i[31:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
state_o[31:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT

Toggle Coverage for Instance : tb.dut.u_ping_timer.u_prim_double_lfsr.gen_double_lfsr[0].u_prim_lfsr
TotalCoveredPercent
Totals 5 5 100.00
Total Bits 134 134 100.00
Total Bits 0->1 67 67 100.00
Total Bits 1->0 67 67 100.00

Ports 5 5 100.00
Port Bits 134 134 100.00
Port Bits 0->1 67 67 100.00
Port Bits 1->0 67 67 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T20,T44 Yes T1,T2,T3 INPUT
seed_en_i Unreachable Unreachable Unreachable INPUT
seed_i[31:0] Unreachable Unreachable Unreachable INPUT
lfsr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
entropy_i[31:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
state_o[31:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT

Toggle Coverage for Instance : tb.dut.u_ping_timer.u_prim_double_lfsr.gen_double_lfsr[1].u_prim_lfsr
TotalCoveredPercent
Totals 5 5 100.00
Total Bits 134 134 100.00
Total Bits 0->1 67 67 100.00
Total Bits 1->0 67 67 100.00

Ports 5 5 100.00
Port Bits 134 134 100.00
Port Bits 0->1 67 67 100.00
Port Bits 1->0 67 67 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T3,T20,T44 Yes T1,T2,T3 INPUT
seed_en_i Unreachable Unreachable Unreachable INPUT
seed_i[31:0] Unreachable Unreachable Unreachable INPUT
lfsr_en_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
entropy_i[31:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
state_o[31:0] Yes Yes T1,T3,T4 Yes T1,T2,T3 OUTPUT

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