Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	112484	1			T5	3259		T29	20		T18	1
class_i[0x1]	27797	1			T25	4		T26	105		T18	1
class_i[0x2]	29872	1			T6	6		T5	45		T26	7
class_i[0x3]	79350	1			T3	10		T20	2402		T5	56

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	64518	1			T3	2		T6	5		T20	587
alert[0x1]	61835	1			T3	2		T6	1		T20	570
alert[0x2]	62142	1			T3	3		T20	620		T5	786
alert[0x3]	61008	1			T3	3		T20	625		T5	836

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

249245

1

T6

6

T20

2402

T5

3360

esc_ping_fail

258

1

T3

10

T18

5

T19

6

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	64449	1			T6	5		T20	587		T5	856
esc_integrity_fail	alert[0x1]	61764	1			T6	1		T20	570		T5	882
esc_integrity_fail	alert[0x2]	62082	1			T20	620		T5	786		T26	3
esc_integrity_fail	alert[0x3]	60950	1			T20	625		T5	836		T26	5
esc_ping_fail	alert[0x0]	69	1			T3	2		T18	1		T19	1
esc_ping_fail	alert[0x1]	71	1			T3	2		T18	2		T19	3
esc_ping_fail	alert[0x2]	60	1			T3	3		T18	1		T19	2
esc_ping_fail	alert[0x3]	58	1			T3	3		T18	1		T289	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	112422	1			T5	3259		T29	20		T30	6
esc_integrity_fail	class_i[0x1]	27764	1			T25	4		T26	105		T30	1
esc_integrity_fail	class_i[0x2]	29789	1			T6	6		T5	45		T26	7
esc_integrity_fail	class_i[0x3]	79270	1			T20	2402		T5	56		T26	3
esc_ping_fail	class_i[0x0]	62	1			T18	1		T19	5		T290	9
esc_ping_fail	class_i[0x1]	33	1			T18	1		T311	1		T302	1
esc_ping_fail	class_i[0x2]	83	1			T18	3		T19	1		T289	9
esc_ping_fail	class_i[0x3]	80	1			T3	10		T280	5		T299	5