Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	671291291	0	0	626
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	671291291	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	671291291	671132237	0	0
tb.dut.CheckAccuCntDw	0	0	626	626	0	0
tb.dut.CheckEscCntDw	0	0	626	626	0	0
tb.dut.CheckNAlerts	0	0	626	626	0	0
tb.dut.CheckNClasses	0	0	626	626	0	0
tb.dut.CheckNEscSev	0	0	626	626	0	0
tb.dut.CrashdumpKnownO_A	0	0	671291291	671132237	0	0
tb.dut.EdnKnownO_A	0	0	671291291	671132237	0	0
tb.dut.EscPKnownO_A	0	0	671291291	671132237	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	671291291	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	671291291	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	671291291	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	671291291	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	671291291	70	0	0
tb.dut.IrqAKnownO_A	0	0	671291291	671132237	0	0
tb.dut.IrqBKnownO_A	0	0	671291291	671132237	0	0
tb.dut.IrqCKnownO_A	0	0	671291291	671132237	0	0
tb.dut.IrqDKnownO_A	0	0	671291291	671132237	0	0
tb.dut.TlAReadyKnownO_A	0	0	671291291	671132237	0	0
tb.dut.TlDValidKnownO_A	0	0	671291291	671132237	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	696202567	3288565	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	696202567	12361	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	696202567	12592	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	696202567	12664	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	696202567	12861	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	696202567	12853	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	696202567	12520	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	696202567	12414	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	696202567	12447	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	696202567	12664	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	696202567	12778	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	696202567	12472	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	696202567	12655	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	696202567	12634	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	696202567	12927	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	696202567	12868	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	696202567	12524	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	696202567	12914	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	696202567	12676	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	696202567	12898	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	696202567	12960	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	696202567	12777	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	696202567	12702	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	696202567	12963	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	696202567	12940	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	696202567	12430	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	696202567	12758	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	696202567	12743	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	696202567	12715	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	696202567	12641	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	696202567	12779	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	696202567	12518	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	696202567	12724	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	696202567	12702	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	696202567	12708	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	696202567	12827	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	696202567	12902	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	696202567	12662	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	696202567	12652	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	696202567	12786	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	696202567	12664	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	696202567	12429	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	696202567	12538	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	696202567	12729	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	696202567	12728	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	696202567	12908	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	696202567	13194	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	696202567	13098	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	696202567	12532	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	696202567	12557	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	696202567	12385	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	696202567	12783	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	696202567	12733	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	696202567	12805	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	696202567	12565	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	696202567	13034	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	696202567	12916	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	696202567	12868	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	696202567	12842	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	696202567	12769	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	696202567	12862	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	696202567	12644	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	696202567	12851	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	696202567	12673	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	696202567	12922	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	696202567	12834	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	696202567	13051	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	696202567	12659	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	696202567	12817	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	696202567	12806	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	696202567	23672	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	696202567	12535	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	696202567	12463	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	696202567	12889	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	696202567	12538	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	696202567	12803	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	696202567	12512	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	696202567	12637	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	696202567	12758	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	671291291	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	671291291	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	671291291	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	671291291	3433	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	671291291	281938	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	671291291	347240903	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	671291291	209	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	671291291	895	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	671291291	50	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	671291291	477	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	671148474	258052543	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	671291291	1000	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	671291291	976	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	671291291	953	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	671291291	929	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	671291291	2210	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	671291291	188373	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	671291291	2086	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	671291291	73	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	671291291	1135	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	671291291	925	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	671147307	671077984	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	671291291	671132237	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	671291291	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	671291291	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	671291291	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	671291291	5826	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	671291291	181467	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	671291291	380401164	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	671291291	228	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	671291291	459	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	671291291	18	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	671291291	198	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	671148474	291570933	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	671291291	542	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	671291291	529	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	671291291	518	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	671291291	512	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	671291291	1251	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	671291291	123726	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	671291291	1154	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	671291291	77	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	671291291	1115	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	671291291	905	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	671147307	671077984	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	671291291	671132237	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	671291291	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	671291291	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	671291291	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	671291291	1719	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	671291291	175217	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	671291291	399470712	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	671291291	180	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	671291291	522	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	671291291	23	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	671291291	264	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	671148474	323935301	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	671291291	610	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	671291291	599	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	671291291	587	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	671291291	573	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	671291291	1040	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	671291291	104546	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	671291291	941	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	671291291	76	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	671291291	1122	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	671291291	912	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	671147307	671077984	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	671291291	671132237	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	671291291	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	671291291	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	671291291	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	671291291	3242	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	671291291	193003	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	671291291	379706276	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	671291291	198	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	671291291	480	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	671291291	24	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	671291291	192	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	671148474	290421465	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	671291291	548	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	671291291	542	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	671291291	531	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	671291291	522	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	671291291	1323	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	671291291	141076	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	671291291	1242	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	671291291	56	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	671291291	1114	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	671291291	904	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	671147307	671077984	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	626	626	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	671291291	671132237	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	696202567	134027440	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	696202567	695522325	0	0
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