Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	73	1			T15	1		T29	1		T31	2
class_index[0x1]	77	1			T5	1		T25	5		T42	1
class_index[0x2]	76	1			T5	1		T42	1		T63	1
class_index[0x3]	56	1			T29	1		T60	1		T32	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	130	1			T15	1		T5	2		T25	5
intr_timeout_cnt[1]	49	1			T29	1		T31	2		T67	1
intr_timeout_cnt[2]	28	1			T75	1		T68	3		T76	2
intr_timeout_cnt[3]	15	1			T32	2		T79	3		T174	1
intr_timeout_cnt[4]	15	1			T78	1		T234	1		T82	1
intr_timeout_cnt[5]	14	1			T42	1		T72	1		T104	1
intr_timeout_cnt[6]	10	1			T42	1		T29	2		T111	1
intr_timeout_cnt[7]	8	1			T84	1		T111	1		T235	1
intr_timeout_cnt[8]	3	1			T105	1		T84	1		T236	1
intr_timeout_cnt[9]	10	1			T54	1		T235	1		T237	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[8]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	40	1			T15	1		T29	1		T32	3
class_index[0x0]	intr_timeout_cnt[1]	11	1			T31	2		T81	2		T238	1
class_index[0x0]	intr_timeout_cnt[2]	8	1			T84	1		T111	1		T237	1
class_index[0x0]	intr_timeout_cnt[3]	2	1			T32	2		-	-		-	-
class_index[0x0]	intr_timeout_cnt[4]	5	1			T235	1		T239	1		T240	1
class_index[0x0]	intr_timeout_cnt[5]	2	1			T241	1		T27	1		-	-
class_index[0x0]	intr_timeout_cnt[6]	2	1			T111	1		T242	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	1	1			T236	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T235	1		T228	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	36	1			T5	1		T25	5		T29	1
class_index[0x1]	intr_timeout_cnt[1]	13	1			T29	1		T111	1		T243	1
class_index[0x1]	intr_timeout_cnt[2]	8	1			T76	1		T244	2		T237	1
class_index[0x1]	intr_timeout_cnt[3]	5	1			T79	3		T174	1		T27	1
class_index[0x1]	intr_timeout_cnt[4]	2	1			T82	1		T236	1		-	-
class_index[0x1]	intr_timeout_cnt[5]	2	1			T55	1		T245	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	3	1			T42	1		T29	1		T246	1
class_index[0x1]	intr_timeout_cnt[7]	3	1			T84	1		T247	2		-	-
class_index[0x1]	intr_timeout_cnt[9]	5	1			T54	1		T91	1		T248	1
class_index[0x2]	intr_timeout_cnt[0]	31	1			T5	1		T63	1		T39	1
class_index[0x2]	intr_timeout_cnt[1]	14	1			T110	3		T249	1		T250	1
class_index[0x2]	intr_timeout_cnt[2]	9	1			T68	3		T220	1		T112	1
class_index[0x2]	intr_timeout_cnt[3]	6	1			T103	1		T228	1		T251	1
class_index[0x2]	intr_timeout_cnt[4]	3	1			T78	1		T234	1		T252	1
class_index[0x2]	intr_timeout_cnt[5]	6	1			T42	1		T72	1		T253	1
class_index[0x2]	intr_timeout_cnt[6]	2	1			T112	1		T254	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	2	1			T235	1		T239	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	1	1			T84	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	2	1			T237	1		T255	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	23	1			T60	1		T32	1		T46	1
class_index[0x3]	intr_timeout_cnt[1]	11	1			T67	1		T54	2		T56	1
class_index[0x3]	intr_timeout_cnt[2]	3	1			T75	1		T76	1		T175	1
class_index[0x3]	intr_timeout_cnt[3]	2	1			T244	1		T236	1		-	-
class_index[0x3]	intr_timeout_cnt[4]	5	1			T220	1		T103	1		T112	1
class_index[0x3]	intr_timeout_cnt[5]	4	1			T104	1		T84	1		T103	1
class_index[0x3]	intr_timeout_cnt[6]	3	1			T29	1		T55	1		T252	1
class_index[0x3]	intr_timeout_cnt[7]	3	1			T111	1		T247	2		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T105	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T256	1		-	-		-	-