Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	357343	1			T3	51		T6	1421		T10	31
all_values[1]	357343	1			T3	51		T6	1421		T10	31
all_values[2]	357343	1			T3	51		T6	1421		T10	31
all_values[3]	357343	1			T3	51		T6	1421		T10	31

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

710471

1

T6

2882

T10

46

T11

3287

auto[1]

718901

1

T3

204

T6

2802

T10

78

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

861991

1

T3

179

T6

2866

T10

66

auto[1]

567381

1

T3

25

T6

2818

T10

58

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	102189	1			T6	349		T10	5		T11	400
all_values[0]	auto[0]	auto[1]	75548	1			T6	338		T10	5		T11	399
all_values[0]	auto[1]	auto[0]	103674	1			T3	50		T6	368		T10	11
all_values[0]	auto[1]	auto[1]	75932	1			T3	1		T6	366		T10	10
all_values[1]	auto[0]	auto[0]	109737	1			T6	378		T10	8		T11	425
all_values[1]	auto[0]	auto[1]	67836	1			T6	375		T10	8		T11	425
all_values[1]	auto[1]	auto[0]	111494	1			T3	37		T6	335		T10	8
all_values[1]	auto[1]	auto[1]	68276	1			T3	14		T6	333		T10	7
all_values[2]	auto[0]	auto[0]	108805	1			T6	362		T10	3		T11	442
all_values[2]	auto[0]	auto[1]	69419	1			T6	358		T10	3		T11	378
all_values[2]	auto[1]	auto[0]	109636	1			T3	51		T6	355		T10	14
all_values[2]	auto[1]	auto[1]	69483	1			T6	346		T10	11		T11	400
all_values[3]	auto[0]	auto[0]	106973	1			T6	366		T10	7		T11	413
all_values[3]	auto[0]	auto[1]	69964	1			T6	356		T10	7		T11	405
all_values[3]	auto[1]	auto[0]	109483	1			T3	41		T6	353		T10	10
all_values[3]	auto[1]	auto[1]	70923	1			T3	10		T6	346		T10	7