Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	357343	1			T3	51		T6	1421		T10	31
all_pins[1]	357343	1			T3	51		T6	1421		T10	31
all_pins[2]	357343	1			T3	51		T6	1421		T10	31
all_pins[3]	357343	1			T3	51		T6	1421		T10	31

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1144758	1			T3	179		T6	4293		T10	89
values[0x1]	284614	1			T3	25		T6	1391		T10	35
transitions[0x0=>0x1]	190444	1			T3	24		T6	887		T10	17
transitions[0x1=>0x0]	190663	1			T3	25		T6	887		T10	18

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	281411	1			T3	50		T6	1055		T10	21
all_pins[0]	values[0x1]	75932	1			T3	1		T6	366		T10	10
all_pins[0]	transitions[0x0=>0x1]	75300	1			T6	366		T10	9		T11	434
all_pins[0]	transitions[0x1=>0x0]	70510	1			T3	10		T6	346		T10	7
all_pins[1]	values[0x0]	289067	1			T3	37		T6	1088		T10	24
all_pins[1]	values[0x1]	68276	1			T3	14		T6	333		T10	7
all_pins[1]	transitions[0x0=>0x1]	37126	1			T3	14		T6	160		T10	2
all_pins[1]	transitions[0x1=>0x0]	44782	1			T3	1		T6	193		T10	5
all_pins[2]	values[0x0]	287860	1			T3	51		T6	1075		T10	20
all_pins[2]	values[0x1]	69483	1			T6	346		T10	11		T11	400
all_pins[2]	transitions[0x0=>0x1]	38526	1			T6	177		T10	4		T11	207
all_pins[2]	transitions[0x1=>0x0]	37319	1			T3	14		T6	164		T11	215
all_pins[3]	values[0x0]	286420	1			T3	41		T6	1075		T10	24
all_pins[3]	values[0x1]	70923	1			T3	10		T6	346		T10	7
all_pins[3]	transitions[0x0=>0x1]	39492	1			T3	10		T6	184		T10	2
all_pins[3]	transitions[0x1=>0x0]	38052	1			T6	184		T10	6		T11	193