Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 24 0 24 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 4 0 4 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 24 0 24 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 272 1 T152 4 T153 7 T154 7
all_values[1] 272 1 T152 4 T153 7 T154 7
all_values[2] 272 1 T152 4 T153 7 T154 7
all_values[3] 272 1 T152 4 T153 7 T154 7



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 612 1 T152 6 T153 17 T154 17
auto[1] 476 1 T152 10 T153 11 T154 11



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 418 1 T152 5 T153 15 T154 15
auto[1] 670 1 T152 11 T153 13 T154 13



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 637 1 T152 7 T153 16 T154 17
auto[1] 451 1 T152 9 T153 12 T154 11



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 24 0 24 100.00
Automatically Generated Cross Bins 24 0 24 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 71 1 T153 4 T154 2 T231 1
all_values[0] auto[0] auto[0] auto[1] 32 1 T152 1 T154 1 T230 1
all_values[0] auto[0] auto[1] auto[0] 34 1 T153 2 T154 1 T230 1
all_values[0] auto[0] auto[1] auto[1] 26 1 T230 2 T231 1 T349 1
all_values[0] auto[1] auto[0] auto[1] 64 1 T152 1 T153 1 T230 1
all_values[0] auto[1] auto[1] auto[1] 45 1 T152 2 T154 3 T230 2
all_values[1] auto[0] auto[0] auto[0] 44 1 T153 1 T154 1 T230 2
all_values[1] auto[0] auto[0] auto[1] 31 1 T154 1 T350 1 T351 2
all_values[1] auto[0] auto[1] auto[0] 44 1 T153 1 T154 1 T231 1
all_values[1] auto[0] auto[1] auto[1] 28 1 T152 1 T230 1 T352 2
all_values[1] auto[1] auto[0] auto[1] 65 1 T152 1 T153 2 T154 4
all_values[1] auto[1] auto[1] auto[1] 60 1 T152 2 T153 3 T230 1
all_values[2] auto[0] auto[0] auto[0] 67 1 T153 6 T154 2 T230 4
all_values[2] auto[0] auto[0] auto[1] 30 1 T231 2 T353 3 T354 3
all_values[2] auto[0] auto[1] auto[0] 46 1 T152 2 T154 2 T231 3
all_values[2] auto[0] auto[1] auto[1] 18 1 T350 1 T349 1 T355 1
all_values[2] auto[1] auto[0] auto[1] 68 1 T152 2 T153 1 T154 1
all_values[2] auto[1] auto[1] auto[1] 43 1 T154 2 T230 2 T350 4
all_values[3] auto[0] auto[0] auto[0] 60 1 T152 1 T154 4 T230 2
all_values[3] auto[0] auto[0] auto[1] 26 1 T230 1 T349 1 T353 2
all_values[3] auto[0] auto[1] auto[0] 52 1 T152 2 T153 1 T154 2
all_values[3] auto[0] auto[1] auto[1] 28 1 T153 1 T231 3 T356 1
all_values[3] auto[1] auto[0] auto[1] 54 1 T153 2 T154 1 T230 2
all_values[3] auto[1] auto[1] auto[1] 52 1 T152 1 T153 3 T230 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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