Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	91036	1			T6	947		T11	917		T14	1699
accum_cnt_1000	222217	1			T6	1091		T11	1318		T12	3
accum_cnt_100	29450	1			T6	62		T11	69		T12	17
accum_cnt_50	75130	1			T6	60		T10	28		T11	51
accum_cnt_10	178641	1			T3	32		T6	16		T10	49
accum_cnt_0	410816	1			T3	120		T6	2176		T10	15

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	263968	1			T3	38		T6	1088		T10	23
class_index[0x1]	263968	1			T3	38		T6	1088		T10	23
class_index[0x2]	263968	1			T3	38		T6	1088		T10	23
class_index[0x3]	263968	1			T3	38		T6	1088		T10	23

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	25450	1			T6	470		T11	577		T14	515
class_index[0x0]	accum_cnt_1000	59719	1			T6	550		T11	518		T14	756
class_index[0x0]	accum_cnt_100	7870	1			T6	29		T11	28		T22	7
class_index[0x0]	accum_cnt_50	23536	1			T6	32		T10	4		T11	19
class_index[0x0]	accum_cnt_10	43531	1			T6	7		T10	15		T11	5
class_index[0x0]	accum_cnt_0	84203	1			T3	38		T10	4		T15	3
class_index[0x1]	accum_cnt_2000	23494	1			T14	595		T21	98		T5	449
class_index[0x1]	accum_cnt_1000	53128	1			T12	3		T14	531		T28	51
class_index[0x1]	accum_cnt_100	6869	1			T12	17		T14	34		T28	19
class_index[0x1]	accum_cnt_50	13209	1			T10	16		T12	14		T13	22
class_index[0x1]	accum_cnt_10	52375	1			T3	32		T10	6		T11	1226
class_index[0x1]	accum_cnt_0	104719	1			T3	6		T6	1088		T10	1
class_index[0x2]	accum_cnt_2000	19390	1			T11	340		T21	306		T29	186
class_index[0x2]	accum_cnt_1000	52719	1			T11	800		T28	57		T17	667
class_index[0x2]	accum_cnt_100	8153	1			T11	41		T28	14		T17	90
class_index[0x2]	accum_cnt_50	15988	1			T11	32		T28	10		T20	689
class_index[0x2]	accum_cnt_10	47113	1			T10	17		T11	11		T14	1
class_index[0x2]	accum_cnt_0	112849	1			T3	38		T6	1088		T10	6
class_index[0x3]	accum_cnt_2000	22702	1			T6	477		T14	589		T20	207
class_index[0x3]	accum_cnt_1000	56651	1			T6	541		T14	505		T20	208
class_index[0x3]	accum_cnt_100	6558	1			T6	33		T14	32		T20	10
class_index[0x3]	accum_cnt_50	22397	1			T6	28		T10	8		T14	18
class_index[0x3]	accum_cnt_10	35622	1			T6	9		T10	11		T14	6
class_index[0x3]	accum_cnt_0	109045	1			T3	38		T10	4		T11	1226