Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	8259	1			T6	21		T20	15		T29	33
alert[0x1]	5930	1			T20	291		T5	263		T43	1
alert[0x2]	7999	1			T6	67		T20	36		T5	788
alert[0x3]	8011	1			T29	21		T72	55		T30	2
alert[0x4]	4984	1			T3	2		T6	30		T26	1258
alert[0x5]	12826	1			T6	1195		T20	2		T5	354
alert[0x6]	18985	1			T3	1		T6	2		T20	79
alert[0x7]	7923	1			T6	852		T289	1		T290	2
alert[0x8]	8452	1			T20	239		T5	658		T26	22
alert[0x9]	5739	1			T20	12		T30	3		T32	39
alert[0xa]	5745	1			T3	1		T6	569		T26	24
alert[0xb]	11213	1			T3	1		T26	15		T29	69
alert[0xc]	6851	1			T3	1		T5	43		T26	80
alert[0xd]	9269	1			T5	33		T30	2		T289	1
alert[0xe]	5442	1			T20	13		T5	395		T26	154
alert[0xf]	5436	1			T6	15		T20	65		T30	1
alert[0x10]	9592	1			T5	24		T26	277		T18	1
alert[0x11]	3899	1			T3	1		T20	72		T26	84
alert[0x12]	3901	1			T25	1		T18	1		T30	2
alert[0x13]	11639	1			T6	33		T32	6		T291	1
alert[0x14]	6829	1			T6	1206		T20	1553		T32	14
alert[0x15]	4754	1			T5	217		T26	31		T18	1
alert[0x16]	4714	1			T20	62		T5	28		T29	18
alert[0x17]	3038	1			T3	2		T6	7		T20	30
alert[0x18]	7511	1			T6	27		T5	152		T26	596
alert[0x19]	9716	1			T6	412		T5	462		T26	4243
alert[0x1a]	6849	1			T3	1		T6	102		T20	25
alert[0x1b]	3780	1			T30	5		T225	4		T32	33
alert[0x1c]	11330	1			T5	759		T26	254		T289	2
alert[0x1d]	4789	1			T20	1661		T5	93		T289	1
alert[0x1e]	15226	1			T3	1		T32	70		T66	26
alert[0x1f]	12084	1			T6	297		T20	8		T17	1
alert[0x20]	9857	1			T30	15		T104	2		T66	32
alert[0x21]	3051	1			T26	2		T29	2		T290	1
alert[0x22]	10355	1			T6	205		T5	441		T26	29
alert[0x23]	5687	1			T3	1		T6	269		T20	44
alert[0x24]	7764	1			T6	36		T5	16		T29	10
alert[0x25]	15536	1			T20	43		T5	643		T26	310
alert[0x26]	7527	1			T3	1		T5	674		T30	8
alert[0x27]	1942	1			T20	4		T18	1		T19	1
alert[0x28]	4956	1			T3	1		T6	29		T17	1
alert[0x29]	2962	1			T6	247		T20	25		T5	64
alert[0x2a]	5707	1			T29	20		T30	15		T289	1
alert[0x2b]	14449	1			T20	11		T5	712		T29	8
alert[0x2c]	5261	1			T6	166		T32	14		T66	2181
alert[0x2d]	8816	1			T20	3677		T26	39		T290	1
alert[0x2e]	5305	1			T26	542		T18	1		T30	72
alert[0x2f]	9191	1			T6	886		T20	15		T16	1
alert[0x30]	6061	1			T6	447		T290	1		T32	11
alert[0x31]	3397	1			T3	1		T5	99		T18	1
alert[0x32]	7041	1			T20	1		T5	83		T72	2
alert[0x33]	3905	1			T20	91		T26	364		T289	2
alert[0x34]	8035	1			T6	22		T20	4581		T5	39
alert[0x35]	12000	1			T29	37		T18	1		T30	1
alert[0x36]	4486	1			T6	38		T20	215		T19	1
alert[0x37]	12808	1			T26	23		T30	125		T291	1
alert[0x38]	7018	1			T20	184		T26	15		T29	9
alert[0x39]	6209	1			T20	529		T5	86		T19	1
alert[0x3a]	4875	1			T6	51		T20	14		T30	7
alert[0x3b]	5324	1			T26	26		T29	1		T19	1
alert[0x3c]	4503	1			T29	4		T289	1		T66	3205
alert[0x3d]	2701	1			T20	27		T290	1		T32	71
alert[0x3e]	5041	1			T5	1173		T26	92		T225	3
alert[0x3f]	6471	1			T20	17		T5	81		T25	1
alert[0x40]	7501	1			T6	255		T20	82		T5	1069

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	134226	1			T3	1		T6	13		T5	9655
class_i[0x1]	118616	1			T3	14		T6	7456		T20	13723
class_i[0x2]	129113	1			T17	2		T26	14480		T29	172
class_i[0x3]	96502	1			T6	17		T72	88		T30	709

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

477836

1

T6

7486

T20

13723

T5

9750

alert_ping_fail

621

1

T3

15

T16

1

T17

2

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	8248	1			T6	21		T20	15		T29	33
alert_integrity_fail	alert[0x1]	5912	1			T20	291		T5	263		T29	1
alert_integrity_fail	alert[0x2]	7995	1			T6	67		T20	36		T5	788
alert_integrity_fail	alert[0x3]	8003	1			T29	21		T72	55		T30	2
alert_integrity_fail	alert[0x4]	4969	1			T6	30		T26	1258		T225	32
alert_integrity_fail	alert[0x5]	12821	1			T6	1195		T20	2		T5	354
alert_integrity_fail	alert[0x6]	18974	1			T6	2		T20	79		T5	6
alert_integrity_fail	alert[0x7]	7911	1			T6	852		T66	18		T45	6
alert_integrity_fail	alert[0x8]	8436	1			T20	239		T5	658		T26	22
alert_integrity_fail	alert[0x9]	5728	1			T20	12		T30	3		T32	39
alert_integrity_fail	alert[0xa]	5734	1			T6	569		T26	24		T29	5
alert_integrity_fail	alert[0xb]	11205	1			T26	15		T29	69		T30	392
alert_integrity_fail	alert[0xc]	6842	1			T5	43		T26	80		T45	255
alert_integrity_fail	alert[0xd]	9264	1			T5	33		T30	2		T68	46
alert_integrity_fail	alert[0xe]	5435	1			T20	13		T5	395		T26	154
alert_integrity_fail	alert[0xf]	5434	1			T6	15		T20	65		T30	1
alert_integrity_fail	alert[0x10]	9577	1			T5	24		T26	277		T30	24
alert_integrity_fail	alert[0x11]	3892	1			T20	72		T26	84		T76	9
alert_integrity_fail	alert[0x12]	3891	1			T25	1		T30	2		T225	1
alert_integrity_fail	alert[0x13]	11627	1			T6	33		T32	6		T66	38
alert_integrity_fail	alert[0x14]	6816	1			T6	1206		T20	1553		T32	14
alert_integrity_fail	alert[0x15]	4738	1			T5	217		T26	31		T45	52
alert_integrity_fail	alert[0x16]	4702	1			T20	62		T5	28		T29	18
alert_integrity_fail	alert[0x17]	3031	1			T6	7		T20	30		T225	1
alert_integrity_fail	alert[0x18]	7498	1			T6	27		T5	152		T26	596
alert_integrity_fail	alert[0x19]	9711	1			T6	412		T5	462		T26	4243
alert_integrity_fail	alert[0x1a]	6841	1			T6	102		T20	25		T5	18
alert_integrity_fail	alert[0x1b]	3777	1			T30	5		T225	4		T32	33
alert_integrity_fail	alert[0x1c]	11317	1			T5	759		T26	254		T66	12
alert_integrity_fail	alert[0x1d]	4779	1			T20	1661		T5	93		T68	147
alert_integrity_fail	alert[0x1e]	15215	1			T32	70		T66	26		T68	9339
alert_integrity_fail	alert[0x1f]	12074	1			T6	297		T20	8		T26	539
alert_integrity_fail	alert[0x20]	9842	1			T30	15		T104	2		T66	32
alert_integrity_fail	alert[0x21]	3041	1			T26	2		T29	2		T66	170
alert_integrity_fail	alert[0x22]	10335	1			T6	205		T5	441		T26	29
alert_integrity_fail	alert[0x23]	5679	1			T6	269		T20	44		T5	114
alert_integrity_fail	alert[0x24]	7763	1			T6	36		T5	16		T29	10
alert_integrity_fail	alert[0x25]	15527	1			T20	43		T5	643		T26	310
alert_integrity_fail	alert[0x26]	7516	1			T5	674		T30	8		T32	630
alert_integrity_fail	alert[0x27]	1937	1			T20	4		T32	22		T66	10
alert_integrity_fail	alert[0x28]	4946	1			T6	29		T26	366		T225	31
alert_integrity_fail	alert[0x29]	2948	1			T6	247		T20	25		T5	64
alert_integrity_fail	alert[0x2a]	5699	1			T29	20		T30	15		T225	69
alert_integrity_fail	alert[0x2b]	14437	1			T20	11		T5	712		T29	8
alert_integrity_fail	alert[0x2c]	5247	1			T6	166		T32	14		T66	2181
alert_integrity_fail	alert[0x2d]	8803	1			T20	3677		T26	39		T32	5
alert_integrity_fail	alert[0x2e]	5295	1			T26	542		T30	72		T32	30
alert_integrity_fail	alert[0x2f]	9177	1			T6	886		T20	15		T5	163
alert_integrity_fail	alert[0x30]	6055	1			T6	447		T32	11		T89	32
alert_integrity_fail	alert[0x31]	3385	1			T5	99		T30	2		T225	21
alert_integrity_fail	alert[0x32]	7032	1			T20	1		T5	83		T72	2
alert_integrity_fail	alert[0x33]	3895	1			T20	91		T26	364		T48	15
alert_integrity_fail	alert[0x34]	8024	1			T6	22		T20	4581		T5	39
alert_integrity_fail	alert[0x35]	11992	1			T29	37		T30	1		T225	3
alert_integrity_fail	alert[0x36]	4482	1			T6	38		T20	215		T32	245
alert_integrity_fail	alert[0x37]	12799	1			T26	23		T30	125		T68	573
alert_integrity_fail	alert[0x38]	7010	1			T20	184		T26	15		T29	9
alert_integrity_fail	alert[0x39]	6202	1			T20	529		T5	86		T225	6
alert_integrity_fail	alert[0x3a]	4872	1			T6	51		T20	14		T30	7
alert_integrity_fail	alert[0x3b]	5312	1			T26	26		T29	1		T32	114
alert_integrity_fail	alert[0x3c]	4497	1			T29	4		T66	3205		T47	16
alert_integrity_fail	alert[0x3d]	2694	1			T20	27		T32	71		T45	21
alert_integrity_fail	alert[0x3e]	5032	1			T5	1173		T26	92		T225	3
alert_integrity_fail	alert[0x3f]	6468	1			T20	17		T5	81		T25	1
alert_integrity_fail	alert[0x40]	7496	1			T6	255		T20	82		T5	1069
alert_ping_fail	alert[0x0]	11	1			T289	1		T292	1		T293	1
alert_ping_fail	alert[0x1]	18	1			T43	1		T288	1		T280	1
alert_ping_fail	alert[0x2]	4	1			T18	1		T19	1		T294	1
alert_ping_fail	alert[0x3]	8	1			T295	1		T296	2		T297	1
alert_ping_fail	alert[0x4]	15	1			T3	2		T43	1		T291	1
alert_ping_fail	alert[0x5]	5	1			T18	1		T19	1		T298	1
alert_ping_fail	alert[0x6]	11	1			T3	1		T18	1		T88	1
alert_ping_fail	alert[0x7]	12	1			T289	1		T290	2		T291	1
alert_ping_fail	alert[0x8]	16	1			T288	1		T280	2		T299	1
alert_ping_fail	alert[0x9]	11	1			T298	1		T300	1		T301	1
alert_ping_fail	alert[0xa]	11	1			T3	1		T19	1		T289	1
alert_ping_fail	alert[0xb]	8	1			T3	1		T18	2		T19	1
alert_ping_fail	alert[0xc]	9	1			T3	1		T18	1		T19	1
alert_ping_fail	alert[0xd]	5	1			T289	1		T290	1		T302	1
alert_ping_fail	alert[0xe]	7	1			T280	2		T299	1		T293	1
alert_ping_fail	alert[0xf]	2	1			T303	1		T304	1		-	-
alert_ping_fail	alert[0x10]	15	1			T18	1		T19	1		T289	1
alert_ping_fail	alert[0x11]	7	1			T3	1		T19	1		T295	1
alert_ping_fail	alert[0x12]	10	1			T18	1		T88	2		T299	1
alert_ping_fail	alert[0x13]	12	1			T291	1		T302	1		T305	1
alert_ping_fail	alert[0x14]	13	1			T306	1		T180	1		T97	1
alert_ping_fail	alert[0x15]	16	1			T18	1		T290	1		T259	1
alert_ping_fail	alert[0x16]	12	1			T290	1		T280	1		T299	1
alert_ping_fail	alert[0x17]	7	1			T3	2		T280	1		T307	1
alert_ping_fail	alert[0x18]	13	1			T18	1		T291	1		T305	1
alert_ping_fail	alert[0x19]	5	1			T289	1		T301	1		T294	1
alert_ping_fail	alert[0x1a]	8	1			T3	1		T18	2		T88	1
alert_ping_fail	alert[0x1b]	3	1			T280	1		T308	1		T309	1
alert_ping_fail	alert[0x1c]	13	1			T289	2		T88	1		T310	1
alert_ping_fail	alert[0x1d]	10	1			T289	1		T290	1		T260	2
alert_ping_fail	alert[0x1e]	11	1			T3	1		T88	1		T280	1
alert_ping_fail	alert[0x1f]	10	1			T17	1		T299	1		T295	1
alert_ping_fail	alert[0x20]	15	1			T259	2		T280	2		T302	1
alert_ping_fail	alert[0x21]	10	1			T290	1		T311	1		T312	1
alert_ping_fail	alert[0x22]	20	1			T280	3		T293	1		T298	1
alert_ping_fail	alert[0x23]	8	1			T3	1		T292	1		T313	1
alert_ping_fail	alert[0x24]	1	1			T280	1		-	-		-	-
alert_ping_fail	alert[0x25]	9	1			T18	1		T289	1		T291	1
alert_ping_fail	alert[0x26]	11	1			T3	1		T88	1		T302	1
alert_ping_fail	alert[0x27]	5	1			T18	1		T19	1		T305	1
alert_ping_fail	alert[0x28]	10	1			T3	1		T17	1		T19	1
alert_ping_fail	alert[0x29]	14	1			T289	2		T291	1		T88	2
alert_ping_fail	alert[0x2a]	8	1			T289	1		T88	2		T292	1
alert_ping_fail	alert[0x2b]	12	1			T314	1		T296	1		T305	1
alert_ping_fail	alert[0x2c]	14	1			T315	1		T316	1		T307	2
alert_ping_fail	alert[0x2d]	13	1			T290	1		T291	1		T88	1
alert_ping_fail	alert[0x2e]	10	1			T18	1		T19	1		T88	4
alert_ping_fail	alert[0x2f]	14	1			T16	1		T18	2		T289	1
alert_ping_fail	alert[0x30]	6	1			T290	1		T293	1		T308	1
alert_ping_fail	alert[0x31]	12	1			T3	1		T18	1		T19	1
alert_ping_fail	alert[0x32]	9	1			T290	1		T88	1		T302	1
alert_ping_fail	alert[0x33]	10	1			T289	2		T299	1		T313	1
alert_ping_fail	alert[0x34]	11	1			T302	1		T296	2		T317	1
alert_ping_fail	alert[0x35]	8	1			T18	1		T289	1		T291	1
alert_ping_fail	alert[0x36]	4	1			T19	1		T312	1		T318	1
alert_ping_fail	alert[0x37]	9	1			T291	1		T88	1		T295	1
alert_ping_fail	alert[0x38]	8	1			T290	1		T314	1		T296	1
alert_ping_fail	alert[0x39]	7	1			T19	1		T280	1		T312	1
alert_ping_fail	alert[0x3a]	3	1			T290	1		T319	1		T320	1
alert_ping_fail	alert[0x3b]	12	1			T19	1		T299	1		T302	1
alert_ping_fail	alert[0x3c]	6	1			T289	1		T314	1		T300	1
alert_ping_fail	alert[0x3d]	7	1			T290	1		T302	1		T298	1
alert_ping_fail	alert[0x3e]	9	1			T290	1		T280	1		T302	1
alert_ping_fail	alert[0x3f]	3	1			T293	1		T313	1		T321	1
alert_ping_fail	alert[0x40]	5	1			T88	1		T299	1		T322	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	134095	1			T6	13		T5	9655		T25	2
alert_integrity_fail	class_i[0x1]	118445	1			T6	7456		T20	13723		T5	95
alert_integrity_fail	class_i[0x2]	128975	1			T26	14480		T29	172		T32	1032
alert_integrity_fail	class_i[0x3]	96321	1			T6	17		T72	88		T30	709
alert_ping_fail	class_i[0x0]	131	1			T3	1		T43	2		T18	18
alert_ping_fail	class_i[0x1]	171	1			T3	14		T16	1		T19	13
alert_ping_fail	class_i[0x2]	138	1			T17	2		T18	1		T290	1
alert_ping_fail	class_i[0x3]	181	1			T19	1		T88	2		T280	21