Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.26 99.99 98.74 97.09 100.00 100.00 99.38 99.60


Total test records in report: 831
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T775 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2150082544 Jul 25 05:11:00 PM PDT 24 Jul 25 05:11:09 PM PDT 24 261405113 ps
T363 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.826461053 Jul 25 05:11:38 PM PDT 24 Jul 25 05:18:53 PM PDT 24 118115407279 ps
T776 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3486997445 Jul 25 05:11:38 PM PDT 24 Jul 25 05:11:44 PM PDT 24 37070509 ps
T777 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.662487479 Jul 25 05:11:48 PM PDT 24 Jul 25 05:11:49 PM PDT 24 6616993 ps
T778 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2029064369 Jul 25 05:10:58 PM PDT 24 Jul 25 05:12:15 PM PDT 24 2130579866 ps
T779 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.280212927 Jul 25 05:11:47 PM PDT 24 Jul 25 05:11:48 PM PDT 24 15728120 ps
T140 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3370110823 Jul 25 05:11:09 PM PDT 24 Jul 25 05:29:36 PM PDT 24 25003797560 ps
T780 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.4162436408 Jul 25 05:11:48 PM PDT 24 Jul 25 05:11:49 PM PDT 24 14094211 ps
T781 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3540210367 Jul 25 05:11:30 PM PDT 24 Jul 25 05:11:42 PM PDT 24 86791651 ps
T782 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3999096144 Jul 25 05:11:45 PM PDT 24 Jul 25 05:11:46 PM PDT 24 10285776 ps
T783 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1284667020 Jul 25 05:17:10 PM PDT 24 Jul 25 05:17:16 PM PDT 24 41435280 ps
T784 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2874706296 Jul 25 05:11:23 PM PDT 24 Jul 25 05:11:24 PM PDT 24 25387853 ps
T785 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1420532519 Jul 25 05:11:45 PM PDT 24 Jul 25 05:11:47 PM PDT 24 8774808 ps
T786 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3181872351 Jul 25 05:11:08 PM PDT 24 Jul 25 05:11:13 PM PDT 24 114107860 ps
T162 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3823144209 Jul 25 05:11:20 PM PDT 24 Jul 25 05:11:25 PM PDT 24 68518571 ps
T142 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2872235591 Jul 25 05:11:11 PM PDT 24 Jul 25 05:17:33 PM PDT 24 8597094932 ps
T787 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.4109113425 Jul 25 05:11:51 PM PDT 24 Jul 25 05:11:52 PM PDT 24 17140442 ps
T788 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.738961675 Jul 25 05:11:09 PM PDT 24 Jul 25 05:11:50 PM PDT 24 2136377817 ps
T789 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.404819336 Jul 25 05:11:58 PM PDT 24 Jul 25 05:11:59 PM PDT 24 13226034 ps
T790 /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1184772852 Jul 25 05:10:56 PM PDT 24 Jul 25 05:11:02 PM PDT 24 66811381 ps
T791 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.295281934 Jul 25 05:11:29 PM PDT 24 Jul 25 05:14:47 PM PDT 24 16462349251 ps
T163 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1988260772 Jul 25 05:11:25 PM PDT 24 Jul 25 05:11:55 PM PDT 24 2133344341 ps
T159 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3889285908 Jul 25 05:11:07 PM PDT 24 Jul 25 05:11:10 PM PDT 24 141253762 ps
T792 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3026105985 Jul 25 05:11:23 PM PDT 24 Jul 25 05:11:26 PM PDT 24 20912507 ps
T793 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.197879064 Jul 25 05:11:16 PM PDT 24 Jul 25 05:11:21 PM PDT 24 505046346 ps
T794 /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3902653167 Jul 25 05:11:48 PM PDT 24 Jul 25 05:11:50 PM PDT 24 10691340 ps
T165 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2502470008 Jul 25 05:11:29 PM PDT 24 Jul 25 05:11:32 PM PDT 24 45568640 ps
T169 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.555659028 Jul 25 05:11:49 PM PDT 24 Jul 25 05:13:08 PM PDT 24 4719530746 ps
T795 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3855147966 Jul 25 05:11:10 PM PDT 24 Jul 25 05:11:18 PM PDT 24 77545140 ps
T796 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3149276086 Jul 25 05:11:27 PM PDT 24 Jul 25 05:11:29 PM PDT 24 9834345 ps
T797 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.4125787308 Jul 25 05:11:16 PM PDT 24 Jul 25 05:14:22 PM PDT 24 5717585513 ps
T798 /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3633769755 Jul 25 05:10:56 PM PDT 24 Jul 25 05:13:58 PM PDT 24 6533272769 ps
T145 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1823686369 Jul 25 05:10:48 PM PDT 24 Jul 25 05:19:46 PM PDT 24 6328002579 ps
T141 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.296549164 Jul 25 05:10:56 PM PDT 24 Jul 25 05:22:21 PM PDT 24 52643479118 ps
T166 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.4128990330 Jul 25 05:11:10 PM PDT 24 Jul 25 05:11:53 PM PDT 24 2291926426 ps
T799 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1748980660 Jul 25 05:11:00 PM PDT 24 Jul 25 05:11:05 PM PDT 24 131587374 ps
T800 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2513830532 Jul 25 05:11:27 PM PDT 24 Jul 25 05:11:33 PM PDT 24 49700466 ps
T801 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.164932161 Jul 25 05:11:09 PM PDT 24 Jul 25 05:11:17 PM PDT 24 110102832 ps
T802 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2148417716 Jul 25 05:11:28 PM PDT 24 Jul 25 05:12:18 PM PDT 24 1379538479 ps
T803 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3714062779 Jul 25 05:11:16 PM PDT 24 Jul 25 05:11:53 PM PDT 24 6070328935 ps
T164 /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.4233484999 Jul 25 05:11:14 PM PDT 24 Jul 25 05:12:35 PM PDT 24 1221428748 ps
T146 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.4156446213 Jul 25 05:11:28 PM PDT 24 Jul 25 05:31:38 PM PDT 24 32970134193 ps
T804 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2209690432 Jul 25 05:11:29 PM PDT 24 Jul 25 05:11:34 PM PDT 24 69288290 ps
T805 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2373427983 Jul 25 05:11:42 PM PDT 24 Jul 25 05:11:49 PM PDT 24 147324767 ps
T167 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2516661897 Jul 25 05:11:00 PM PDT 24 Jul 25 05:11:03 PM PDT 24 77931210 ps
T806 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.374843399 Jul 25 05:10:46 PM PDT 24 Jul 25 05:10:50 PM PDT 24 23170286 ps
T807 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3300508587 Jul 25 05:11:45 PM PDT 24 Jul 25 05:11:47 PM PDT 24 11597642 ps
T155 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.4005503051 Jul 25 05:11:09 PM PDT 24 Jul 25 05:11:47 PM PDT 24 293986377 ps
T808 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.4091436444 Jul 25 05:11:37 PM PDT 24 Jul 25 05:11:39 PM PDT 24 32512550 ps
T809 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3487138637 Jul 25 05:11:47 PM PDT 24 Jul 25 05:11:49 PM PDT 24 13118433 ps
T810 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.901399038 Jul 25 05:10:59 PM PDT 24 Jul 25 05:11:19 PM PDT 24 491413596 ps
T811 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1546119731 Jul 25 05:11:38 PM PDT 24 Jul 25 05:11:40 PM PDT 24 13774529 ps
T812 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.566730662 Jul 25 05:11:50 PM PDT 24 Jul 25 05:11:58 PM PDT 24 115279802 ps
T813 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.395213486 Jul 25 05:10:59 PM PDT 24 Jul 25 05:14:16 PM PDT 24 1708593349 ps
T814 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1202245305 Jul 25 05:11:08 PM PDT 24 Jul 25 05:11:10 PM PDT 24 17529736 ps
T815 /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.1857082003 Jul 25 05:11:49 PM PDT 24 Jul 25 05:11:51 PM PDT 24 19200030 ps
T816 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1506199518 Jul 25 05:11:28 PM PDT 24 Jul 25 05:11:45 PM PDT 24 530609575 ps
T817 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1713971200 Jul 25 05:11:38 PM PDT 24 Jul 25 05:11:58 PM PDT 24 282427387 ps
T818 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2590001414 Jul 25 05:10:47 PM PDT 24 Jul 25 05:10:49 PM PDT 24 57297370 ps
T143 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2891835184 Jul 25 05:11:07 PM PDT 24 Jul 25 05:15:44 PM PDT 24 2571566297 ps
T819 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3275057416 Jul 25 05:11:17 PM PDT 24 Jul 25 05:11:22 PM PDT 24 46188643 ps
T820 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1448674791 Jul 25 05:11:47 PM PDT 24 Jul 25 05:11:48 PM PDT 24 12898653 ps
T821 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3846761348 Jul 25 05:11:21 PM PDT 24 Jul 25 05:12:54 PM PDT 24 821505098 ps
T168 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.357770284 Jul 25 05:11:16 PM PDT 24 Jul 25 05:11:53 PM PDT 24 1836519019 ps
T144 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2521338844 Jul 25 05:10:58 PM PDT 24 Jul 25 05:32:18 PM PDT 24 71237784980 ps
T822 /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.4216871147 Jul 25 05:11:01 PM PDT 24 Jul 25 05:17:53 PM PDT 24 23783989965 ps
T148 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.501483630 Jul 25 05:11:39 PM PDT 24 Jul 25 05:22:01 PM PDT 24 9313807165 ps
T147 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1974799252 Jul 25 05:10:55 PM PDT 24 Jul 25 05:20:38 PM PDT 24 30889959824 ps
T823 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.38266065 Jul 25 05:11:17 PM PDT 24 Jul 25 05:11:29 PM PDT 24 570102311 ps
T824 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.274440058 Jul 25 05:11:36 PM PDT 24 Jul 25 05:11:40 PM PDT 24 23786518 ps
T825 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3765799858 Jul 25 05:11:15 PM PDT 24 Jul 25 05:11:27 PM PDT 24 305943197 ps
T365 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3353380963 Jul 25 05:15:06 PM PDT 24 Jul 25 05:25:45 PM PDT 24 18122947446 ps
T364 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3263997416 Jul 25 05:10:57 PM PDT 24 Jul 25 05:29:23 PM PDT 24 249051585087 ps
T366 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.4070612610 Jul 25 05:11:26 PM PDT 24 Jul 25 05:19:53 PM PDT 24 24194542430 ps
T826 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.647823391 Jul 25 05:10:58 PM PDT 24 Jul 25 05:11:02 PM PDT 24 38995686 ps
T172 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3500602677 Jul 25 05:11:27 PM PDT 24 Jul 25 05:11:30 PM PDT 24 103741533 ps
T827 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.498851099 Jul 25 05:11:21 PM PDT 24 Jul 25 05:11:39 PM PDT 24 516890347 ps
T828 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1302494467 Jul 25 05:11:47 PM PDT 24 Jul 25 05:11:49 PM PDT 24 11307715 ps
T829 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3989127923 Jul 25 05:11:47 PM PDT 24 Jul 25 05:11:48 PM PDT 24 32541357 ps
T830 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2514524067 Jul 25 05:11:09 PM PDT 24 Jul 25 05:11:11 PM PDT 24 20810454 ps
T831 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.1225605383 Jul 25 05:11:29 PM PDT 24 Jul 25 05:11:30 PM PDT 24 7619416 ps

Test location /workspace/coverage/default/43.alert_handler_random_classes.3933512801
Short name T10
Test name
Test status
Simulation time 1667622191 ps
CPU time 39.74 seconds
Started Jul 25 05:34:23 PM PDT 24
Finished Jul 25 05:35:03 PM PDT 24
Peak memory 248884 kb
Host smart-e303de1b-f342-4284-a92a-11078da91a18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39335
12801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3933512801
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.1084446714
Short name T25
Test name
Test status
Simulation time 40601394976 ps
CPU time 639.29 seconds
Started Jul 25 05:30:09 PM PDT 24
Finished Jul 25 05:40:48 PM PDT 24
Peak memory 269176 kb
Host smart-dc1d33b8-d2ef-4079-89cd-6f2f6728026e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084446714 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.1084446714
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.3347578425
Short name T2
Test name
Test status
Simulation time 877596717 ps
CPU time 36.76 seconds
Started Jul 25 05:24:59 PM PDT 24
Finished Jul 25 05:25:36 PM PDT 24
Peak memory 248836 kb
Host smart-b4fad313-849c-4e64-912c-98754e408e5f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3347578425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.3347578425
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.3565501517
Short name T7
Test name
Test status
Simulation time 857712547 ps
CPU time 13.55 seconds
Started Jul 25 05:22:16 PM PDT 24
Finished Jul 25 05:22:30 PM PDT 24
Peak memory 278200 kb
Host smart-5c660162-e7fb-48ce-ae9e-627cd4da2f57
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3565501517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.3565501517
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.4244050148
Short name T150
Test name
Test status
Simulation time 936467139 ps
CPU time 72.46 seconds
Started Jul 25 05:11:08 PM PDT 24
Finished Jul 25 05:12:21 PM PDT 24
Peak memory 237448 kb
Host smart-0923fc66-1b99-4265-9f71-59467c14cc98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4244050148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.4244050148
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.3607597638
Short name T26
Test name
Test status
Simulation time 13463369257 ps
CPU time 1325.69 seconds
Started Jul 25 05:29:31 PM PDT 24
Finished Jul 25 05:51:37 PM PDT 24
Peak memory 289720 kb
Host smart-d61e00b4-0361-42a8-965a-0307e6694acd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607597638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.3607597638
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.4222133372
Short name T277
Test name
Test status
Simulation time 34474910142 ps
CPU time 4361.5 seconds
Started Jul 25 05:26:18 PM PDT 24
Finished Jul 25 06:39:00 PM PDT 24
Peak memory 354864 kb
Host smart-8a5e50b0-b769-401e-badc-7aeb67f71394
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222133372 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.4222133372
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.1160934906
Short name T32
Test name
Test status
Simulation time 319968147488 ps
CPU time 7315.18 seconds
Started Jul 25 05:27:50 PM PDT 24
Finished Jul 25 07:29:46 PM PDT 24
Peak memory 355516 kb
Host smart-1f57bad3-c1f3-499e-ab99-1300d5913f77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160934906 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.1160934906
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.973914757
Short name T118
Test name
Test status
Simulation time 3940417613 ps
CPU time 318.34 seconds
Started Jul 25 05:11:47 PM PDT 24
Finished Jul 25 05:17:06 PM PDT 24
Peak memory 265404 kb
Host smart-99ffa407-5861-47d2-9ed1-6aab2701e52a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=973914757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_erro
rs.973914757
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2051611972
Short name T20
Test name
Test status
Simulation time 164756790694 ps
CPU time 1428.59 seconds
Started Jul 25 05:33:01 PM PDT 24
Finished Jul 25 05:56:50 PM PDT 24
Peak memory 272964 kb
Host smart-6bf3962a-203e-450e-9c45-92d3cef32213
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051611972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2051611972
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1449170278
Short name T288
Test name
Test status
Simulation time 34364934911 ps
CPU time 2142.76 seconds
Started Jul 25 05:31:48 PM PDT 24
Finished Jul 25 06:07:31 PM PDT 24
Peak memory 283988 kb
Host smart-42576be0-968d-4c87-b2ed-42060c75b571
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449170278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1449170278
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.3362804140
Short name T115
Test name
Test status
Simulation time 5922457286 ps
CPU time 472.87 seconds
Started Jul 25 05:11:27 PM PDT 24
Finished Jul 25 05:19:20 PM PDT 24
Peak memory 265492 kb
Host smart-8ac261a1-91b6-44b8-9c95-064f08a01cf4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362804140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3362804140
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.915414605
Short name T653
Test name
Test status
Simulation time 67919723230 ps
CPU time 2311.97 seconds
Started Jul 25 05:25:56 PM PDT 24
Finished Jul 25 06:04:29 PM PDT 24
Peak memory 288776 kb
Host smart-b980d48b-0b18-4704-a6e3-533d75700a96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915414605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.915414605
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1436297920
Short name T129
Test name
Test status
Simulation time 18050315242 ps
CPU time 350.27 seconds
Started Jul 25 05:11:06 PM PDT 24
Finished Jul 25 05:16:57 PM PDT 24
Peak memory 265416 kb
Host smart-38c2d52e-1e2d-4c6f-974f-abb2c959bcee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1436297920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1436297920
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.318306399
Short name T92
Test name
Test status
Simulation time 69077043107 ps
CPU time 2027.12 seconds
Started Jul 25 05:26:08 PM PDT 24
Finished Jul 25 05:59:56 PM PDT 24
Peak memory 288860 kb
Host smart-63eeb3dd-378e-4248-8aaf-c3d08a32fdad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318306399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.318306399
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.4010521476
Short name T29
Test name
Test status
Simulation time 75121141598 ps
CPU time 2571.92 seconds
Started Jul 25 05:21:19 PM PDT 24
Finished Jul 25 06:04:11 PM PDT 24
Peak memory 289180 kb
Host smart-6a383903-9281-4e61-b895-af96c574865e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010521476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.4010521476
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1607919369
Short name T127
Test name
Test status
Simulation time 103254616916 ps
CPU time 408.91 seconds
Started Jul 25 05:10:59 PM PDT 24
Finished Jul 25 05:17:48 PM PDT 24
Peak memory 273564 kb
Host smart-af3c75a5-a2af-4a74-b180-96eb99400ab7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1607919369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1607919369
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.575205508
Short name T260
Test name
Test status
Simulation time 110881061593 ps
CPU time 1637.49 seconds
Started Jul 25 05:24:22 PM PDT 24
Finished Jul 25 05:51:40 PM PDT 24
Peak memory 272736 kb
Host smart-30f8bb07-fc34-46d0-8cca-32f7fc2e99ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575205508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.575205508
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.1275783244
Short name T18
Test name
Test status
Simulation time 12642105093 ps
CPU time 527.21 seconds
Started Jul 25 05:21:37 PM PDT 24
Finished Jul 25 05:30:24 PM PDT 24
Peak memory 248748 kb
Host smart-9e81e5e6-0fcd-4bb4-b91d-6f3be880c08c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275783244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.1275783244
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.4081340252
Short name T231
Test name
Test status
Simulation time 25550214 ps
CPU time 1.47 seconds
Started Jul 25 05:10:59 PM PDT 24
Finished Jul 25 05:11:00 PM PDT 24
Peak memory 237484 kb
Host smart-9593cdd5-cd1c-4166-aeff-fddc2319f994
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4081340252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.4081340252
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3075385706
Short name T137
Test name
Test status
Simulation time 4291609848 ps
CPU time 687.59 seconds
Started Jul 25 05:11:16 PM PDT 24
Finished Jul 25 05:22:44 PM PDT 24
Peak memory 265392 kb
Host smart-2d4ea06d-baa5-4c1f-98b0-13558452afa8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075385706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3075385706
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.1577984121
Short name T323
Test name
Test status
Simulation time 33559485812 ps
CPU time 1857.26 seconds
Started Jul 25 05:21:39 PM PDT 24
Finished Jul 25 05:52:37 PM PDT 24
Peak memory 272900 kb
Host smart-b237ee9d-4d37-4f86-aae7-e0c1508ac367
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577984121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.1577984121
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1551910502
Short name T280
Test name
Test status
Simulation time 14795649022 ps
CPU time 555.91 seconds
Started Jul 25 05:23:01 PM PDT 24
Finished Jul 25 05:32:17 PM PDT 24
Peak memory 247728 kb
Host smart-901c710c-f527-4fbe-b3a4-24e9e25659ae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551910502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1551910502
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.3698541869
Short name T134
Test name
Test status
Simulation time 4573600677 ps
CPU time 606.27 seconds
Started Jul 25 05:11:20 PM PDT 24
Finished Jul 25 05:21:26 PM PDT 24
Peak memory 265320 kb
Host smart-3b7cd60a-b673-4a96-ac9c-62b80c9c0297
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698541869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.3698541869
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1650308703
Short name T125
Test name
Test status
Simulation time 24908127509 ps
CPU time 345.25 seconds
Started Jul 25 05:11:27 PM PDT 24
Finished Jul 25 05:17:12 PM PDT 24
Peak memory 265420 kb
Host smart-df6596e5-c35f-4b49-a1d7-7847c7cea73d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1650308703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1650308703
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.113852537
Short name T290
Test name
Test status
Simulation time 17345404507 ps
CPU time 491.43 seconds
Started Jul 25 05:23:43 PM PDT 24
Finished Jul 25 05:31:55 PM PDT 24
Peak memory 248864 kb
Host smart-47773743-c3ac-4730-a06a-8e58e879c9c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113852537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.113852537
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.1507714253
Short name T325
Test name
Test status
Simulation time 79251027168 ps
CPU time 2575.84 seconds
Started Jul 25 05:33:31 PM PDT 24
Finished Jul 25 06:16:28 PM PDT 24
Peak memory 288916 kb
Host smart-bdcff117-57d7-4a19-a57e-e85211678be2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507714253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1507714253
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.3299747308
Short name T315
Test name
Test status
Simulation time 38511437061 ps
CPU time 392.86 seconds
Started Jul 25 05:33:47 PM PDT 24
Finished Jul 25 05:40:20 PM PDT 24
Peak memory 255484 kb
Host smart-aca7075b-2232-4f25-8abf-0f5b4e1b52ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299747308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3299747308
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1024542119
Short name T13
Test name
Test status
Simulation time 1354033812 ps
CPU time 35.69 seconds
Started Jul 25 05:34:14 PM PDT 24
Finished Jul 25 05:34:50 PM PDT 24
Peak memory 248440 kb
Host smart-57b82ee4-7497-4e10-9703-93fad8c39676
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10245
42119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1024542119
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2521338844
Short name T144
Test name
Test status
Simulation time 71237784980 ps
CPU time 1280.62 seconds
Started Jul 25 05:10:58 PM PDT 24
Finished Jul 25 05:32:18 PM PDT 24
Peak memory 265388 kb
Host smart-29bec506-b0e7-4b10-b7c4-1686ca17bb93
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521338844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.2521338844
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.4164602912
Short name T112
Test name
Test status
Simulation time 73673405125 ps
CPU time 5894.85 seconds
Started Jul 25 05:22:31 PM PDT 24
Finished Jul 25 07:00:46 PM PDT 24
Peak memory 370068 kb
Host smart-81159e6e-97ae-4873-be14-f4803fc7abf7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164602912 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.4164602912
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3766109714
Short name T247
Test name
Test status
Simulation time 309101476463 ps
CPU time 4545.89 seconds
Started Jul 25 05:26:43 PM PDT 24
Finished Jul 25 06:42:29 PM PDT 24
Peak memory 305868 kb
Host smart-67fe6e9a-9c6c-423a-90ab-ea0d13234831
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766109714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3766109714
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3062282893
Short name T259
Test name
Test status
Simulation time 78386414346 ps
CPU time 2260.71 seconds
Started Jul 25 05:35:05 PM PDT 24
Finished Jul 25 06:12:46 PM PDT 24
Peak memory 273176 kb
Host smart-df373307-5efd-45dd-a8df-2d6e648afa2c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062282893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3062282893
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.1853697720
Short name T138
Test name
Test status
Simulation time 60844064741 ps
CPU time 723.53 seconds
Started Jul 25 05:11:08 PM PDT 24
Finished Jul 25 05:23:12 PM PDT 24
Peak memory 265448 kb
Host smart-90934371-813c-452c-98a3-84e7e7d085a6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853697720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.1853697720
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.248255176
Short name T302
Test name
Test status
Simulation time 7736010539 ps
CPU time 312.91 seconds
Started Jul 25 05:24:04 PM PDT 24
Finished Jul 25 05:29:17 PM PDT 24
Peak memory 247904 kb
Host smart-3c894c50-4bc1-48ec-a223-4a94c4086a7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248255176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.248255176
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.793159432
Short name T78
Test name
Test status
Simulation time 61982589612 ps
CPU time 3108.28 seconds
Started Jul 25 05:23:54 PM PDT 24
Finished Jul 25 06:15:43 PM PDT 24
Peak memory 320832 kb
Host smart-282b6f81-042b-4853-a1e1-ae294363907c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793159432 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.793159432
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3556663235
Short name T120
Test name
Test status
Simulation time 12247528157 ps
CPU time 338.76 seconds
Started Jul 25 05:11:09 PM PDT 24
Finished Jul 25 05:16:48 PM PDT 24
Peak memory 266468 kb
Host smart-efbeaf6b-2beb-4b23-b6a2-3c7860c1448a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3556663235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3556663235
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.4252392236
Short name T355
Test name
Test status
Simulation time 11505290 ps
CPU time 1.59 seconds
Started Jul 25 05:11:47 PM PDT 24
Finished Jul 25 05:11:48 PM PDT 24
Peak memory 237408 kb
Host smart-a30d2389-c9a0-428a-9635-db504f9737af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4252392236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.4252392236
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2490619155
Short name T43
Test name
Test status
Simulation time 79106915465 ps
CPU time 1266.99 seconds
Started Jul 25 05:24:54 PM PDT 24
Finished Jul 25 05:46:01 PM PDT 24
Peak memory 272668 kb
Host smart-783eea36-131b-4f48-a047-8784c1f34fb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490619155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2490619155
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3201101193
Short name T339
Test name
Test status
Simulation time 527584579660 ps
CPU time 2255.65 seconds
Started Jul 25 05:25:15 PM PDT 24
Finished Jul 25 06:02:51 PM PDT 24
Peak memory 282668 kb
Host smart-af072380-5677-4805-a201-1fe666ead42f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201101193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3201101193
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.348871897
Short name T84
Test name
Test status
Simulation time 100713194900 ps
CPU time 5183.26 seconds
Started Jul 25 05:36:06 PM PDT 24
Finished Jul 25 07:02:29 PM PDT 24
Peak memory 338604 kb
Host smart-af83064f-6b77-48d2-8642-4e29feabb8a4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348871897 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.348871897
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.2043360298
Short name T663
Test name
Test status
Simulation time 14136641143 ps
CPU time 569.8 seconds
Started Jul 25 05:24:56 PM PDT 24
Finished Jul 25 05:34:26 PM PDT 24
Peak memory 255648 kb
Host smart-d889ccff-8709-461d-b3e0-351dd6206bac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043360298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.2043360298
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.3813238809
Short name T244
Test name
Test status
Simulation time 30764962609 ps
CPU time 473.53 seconds
Started Jul 25 05:26:07 PM PDT 24
Finished Jul 25 05:34:01 PM PDT 24
Peak memory 255800 kb
Host smart-e44839db-fbc6-4709-b278-bf5e4ca9d84d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813238809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.3813238809
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1403151015
Short name T340
Test name
Test status
Simulation time 113897745380 ps
CPU time 1550.31 seconds
Started Jul 25 05:27:20 PM PDT 24
Finished Jul 25 05:53:10 PM PDT 24
Peak memory 273444 kb
Host smart-b472867a-69a2-4849-8f01-c0b64ce4215f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403151015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1403151015
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3353380963
Short name T365
Test name
Test status
Simulation time 18122947446 ps
CPU time 638.79 seconds
Started Jul 25 05:15:06 PM PDT 24
Finished Jul 25 05:25:45 PM PDT 24
Peak memory 265468 kb
Host smart-0c48c325-fd0b-4e47-beb7-c823f167e708
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353380963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3353380963
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2903325736
Short name T119
Test name
Test status
Simulation time 19131480522 ps
CPU time 363 seconds
Started Jul 25 05:10:57 PM PDT 24
Finished Jul 25 05:17:01 PM PDT 24
Peak memory 265440 kb
Host smart-2a7dcdfa-461c-4824-abdc-ff8f748faeb0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2903325736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2903325736
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.3920696163
Short name T319
Test name
Test status
Simulation time 14849364811 ps
CPU time 325.93 seconds
Started Jul 25 05:21:22 PM PDT 24
Finished Jul 25 05:26:48 PM PDT 24
Peak memory 248912 kb
Host smart-62e3bac8-3bda-42f0-88ef-9c22e8d84ea0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920696163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.3920696163
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.1144552606
Short name T245
Test name
Test status
Simulation time 71078141001 ps
CPU time 4816.64 seconds
Started Jul 25 05:28:18 PM PDT 24
Finished Jul 25 06:48:35 PM PDT 24
Peak memory 306320 kb
Host smart-1e58401d-0e5b-4154-9f84-6f53b6e7063b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144552606 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.1144552606
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.3416892273
Short name T235
Test name
Test status
Simulation time 699194769 ps
CPU time 49.87 seconds
Started Jul 25 05:32:55 PM PDT 24
Finished Jul 25 05:33:45 PM PDT 24
Peak memory 256128 kb
Host smart-b40af620-0c50-4aa4-820a-97faffc3f942
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34168
92273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.3416892273
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1057570850
Short name T160
Test name
Test status
Simulation time 41465449 ps
CPU time 3.69 seconds
Started Jul 25 05:11:00 PM PDT 24
Finished Jul 25 05:11:04 PM PDT 24
Peak memory 237448 kb
Host smart-f34134fe-25f1-47da-803f-432f94e10a9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1057570850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1057570850
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.2442803529
Short name T27
Test name
Test status
Simulation time 177389091016 ps
CPU time 1553.41 seconds
Started Jul 25 05:31:45 PM PDT 24
Finished Jul 25 05:57:39 PM PDT 24
Peak memory 288848 kb
Host smart-f2d3b3aa-cd7e-4b66-9e7a-67230545bce8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442803529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.2442803529
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.1920332163
Short name T197
Test name
Test status
Simulation time 61171214 ps
CPU time 2.95 seconds
Started Jul 25 05:21:20 PM PDT 24
Finished Jul 25 05:21:23 PM PDT 24
Peak memory 249176 kb
Host smart-b7184b03-4422-4224-814b-4605561bdb4f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1920332163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.1920332163
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1854694525
Short name T193
Test name
Test status
Simulation time 41207231 ps
CPU time 3.77 seconds
Started Jul 25 05:21:38 PM PDT 24
Finished Jul 25 05:21:42 PM PDT 24
Peak memory 249104 kb
Host smart-ec368137-56b6-4ee3-937e-c41e3aeabb40
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1854694525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1854694525
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.2646499078
Short name T206
Test name
Test status
Simulation time 32943778 ps
CPU time 3.6 seconds
Started Jul 25 05:23:55 PM PDT 24
Finished Jul 25 05:23:59 PM PDT 24
Peak memory 249176 kb
Host smart-740e277e-92a2-47b3-b086-4062a3c915e2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2646499078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2646499078
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.929569883
Short name T191
Test name
Test status
Simulation time 167069678 ps
CPU time 4.43 seconds
Started Jul 25 05:24:13 PM PDT 24
Finished Jul 25 05:24:17 PM PDT 24
Peak memory 249116 kb
Host smart-345e7130-f3a5-401c-9e5e-cd45a5c380c5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=929569883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.929569883
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3370110823
Short name T140
Test name
Test status
Simulation time 25003797560 ps
CPU time 1106.64 seconds
Started Jul 25 05:11:09 PM PDT 24
Finished Jul 25 05:29:36 PM PDT 24
Peak memory 265396 kb
Host smart-d286d623-493d-4377-9785-3f3c3e306d2a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370110823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3370110823
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.2071769331
Short name T286
Test name
Test status
Simulation time 82811583495 ps
CPU time 1602.24 seconds
Started Jul 25 05:21:29 PM PDT 24
Finished Jul 25 05:48:12 PM PDT 24
Peak memory 286848 kb
Host smart-4b2b5377-9802-4744-ad86-61c56a214e8c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071769331 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.2071769331
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3037355890
Short name T236
Test name
Test status
Simulation time 145432231166 ps
CPU time 2800.81 seconds
Started Jul 25 05:25:26 PM PDT 24
Finished Jul 25 06:12:07 PM PDT 24
Peak memory 289624 kb
Host smart-eebd8bac-f145-487b-b310-68c65e060e01
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037355890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3037355890
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3239006879
Short name T54
Test name
Test status
Simulation time 315465498066 ps
CPU time 2536.73 seconds
Started Jul 25 05:30:50 PM PDT 24
Finished Jul 25 06:13:07 PM PDT 24
Peak memory 289324 kb
Host smart-fd06496a-b7a6-4121-ab8a-51cbb79f6a33
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239006879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3239006879
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.3464782453
Short name T327
Test name
Test status
Simulation time 117045325157 ps
CPU time 2264.61 seconds
Started Jul 25 05:35:20 PM PDT 24
Finished Jul 25 06:13:05 PM PDT 24
Peak memory 287168 kb
Host smart-3e995460-9ab6-4ebf-9646-5f47f55ecf61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464782453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.3464782453
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.2572236506
Short name T105
Test name
Test status
Simulation time 2158778926 ps
CPU time 41.38 seconds
Started Jul 25 05:22:44 PM PDT 24
Finished Jul 25 05:23:25 PM PDT 24
Peak memory 248784 kb
Host smart-a464b767-0406-45b9-8606-c498787de60c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25722
36506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2572236506
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.1105496308
Short name T46
Test name
Test status
Simulation time 1048497350194 ps
CPU time 3168.61 seconds
Started Jul 25 05:23:36 PM PDT 24
Finished Jul 25 06:16:25 PM PDT 24
Peak memory 289712 kb
Host smart-81234ac4-6a4e-4dd7-b485-3aa7736d9e48
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105496308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.1105496308
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.4233484999
Short name T164
Test name
Test status
Simulation time 1221428748 ps
CPU time 81.21 seconds
Started Jul 25 05:11:14 PM PDT 24
Finished Jul 25 05:12:35 PM PDT 24
Peak memory 239952 kb
Host smart-1cc8b4bf-6743-445e-affc-980ee6f8ed13
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4233484999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.4233484999
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.1261458633
Short name T161
Test name
Test status
Simulation time 1303648511 ps
CPU time 45.06 seconds
Started Jul 25 05:11:26 PM PDT 24
Finished Jul 25 05:12:12 PM PDT 24
Peak memory 240416 kb
Host smart-26b6c1a9-79ff-4f16-9893-78607aa10db2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1261458633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.1261458633
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.4206538814
Short name T727
Test name
Test status
Simulation time 10262063 ps
CPU time 1.56 seconds
Started Jul 25 05:11:19 PM PDT 24
Finished Jul 25 05:11:21 PM PDT 24
Peak memory 235520 kb
Host smart-db521e5e-ea9f-4b10-b388-759502cdf141
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4206538814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.4206538814
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.2589075868
Short name T688
Test name
Test status
Simulation time 37638996578 ps
CPU time 1137.62 seconds
Started Jul 25 05:21:40 PM PDT 24
Finished Jul 25 05:40:37 PM PDT 24
Peak memory 289764 kb
Host smart-c831d99f-121f-4c9c-a357-8fccd26ad382
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589075868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.2589075868
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.708679057
Short name T242
Test name
Test status
Simulation time 557889522 ps
CPU time 34.32 seconds
Started Jul 25 05:21:32 PM PDT 24
Finished Jul 25 05:22:06 PM PDT 24
Peak memory 248360 kb
Host smart-ca012495-d461-49f2-b9f6-9f41cb75f930
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70867
9057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.708679057
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3752584269
Short name T181
Test name
Test status
Simulation time 99463093 ps
CPU time 6.77 seconds
Started Jul 25 05:21:28 PM PDT 24
Finished Jul 25 05:21:35 PM PDT 24
Peak memory 249112 kb
Host smart-bad492c7-2d18-46a7-9c4d-ceaa5dd7f306
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37525
84269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3752584269
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1081612095
Short name T330
Test name
Test status
Simulation time 14182317762 ps
CPU time 1536.32 seconds
Started Jul 25 05:24:04 PM PDT 24
Finished Jul 25 05:49:40 PM PDT 24
Peak memory 289144 kb
Host smart-30708fa9-ffe4-4c2c-abbf-c3c0ae49be11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081612095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1081612095
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.325007766
Short name T255
Test name
Test status
Simulation time 16080875614 ps
CPU time 1896.37 seconds
Started Jul 25 05:24:04 PM PDT 24
Finished Jul 25 05:55:41 PM PDT 24
Peak memory 289812 kb
Host smart-60c2574e-81d0-41ee-9b5b-9f97dbe9f6ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325007766 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.325007766
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.2867037943
Short name T76
Test name
Test status
Simulation time 164377795262 ps
CPU time 2853.26 seconds
Started Jul 25 05:24:14 PM PDT 24
Finished Jul 25 06:11:48 PM PDT 24
Peak memory 290052 kb
Host smart-8af9c9e2-169e-4a80-a30a-9deaa59751ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867037943 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.2867037943
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3849359180
Short name T19
Test name
Test status
Simulation time 8847376258 ps
CPU time 388.52 seconds
Started Jul 25 05:25:13 PM PDT 24
Finished Jul 25 05:31:42 PM PDT 24
Peak memory 255148 kb
Host smart-ed0160ec-85a7-4e8e-bc89-1bd6128df787
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849359180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3849359180
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1242353484
Short name T293
Test name
Test status
Simulation time 141386402837 ps
CPU time 369.82 seconds
Started Jul 25 05:26:45 PM PDT 24
Finished Jul 25 05:32:55 PM PDT 24
Peak memory 248916 kb
Host smart-94da1f8b-333e-419a-9c6a-2fb19d9e2685
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242353484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1242353484
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3780007536
Short name T94
Test name
Test status
Simulation time 16112657797 ps
CPU time 351.28 seconds
Started Jul 25 05:27:07 PM PDT 24
Finished Jul 25 05:32:59 PM PDT 24
Peak memory 265332 kb
Host smart-9d2aa6fd-2c2f-4cd7-a572-783989b2baf5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780007536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3780007536
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.23530444
Short name T252
Test name
Test status
Simulation time 58101483032 ps
CPU time 2674.32 seconds
Started Jul 25 05:28:27 PM PDT 24
Finished Jul 25 06:13:02 PM PDT 24
Peak memory 289172 kb
Host smart-e8a5a0d8-4e72-4566-b976-fff40e8ffcd8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23530444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_hand
ler_stress_all.23530444
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.3989346493
Short name T256
Test name
Test status
Simulation time 310441968720 ps
CPU time 5179.15 seconds
Started Jul 25 05:29:50 PM PDT 24
Finished Jul 25 06:56:09 PM PDT 24
Peak memory 300228 kb
Host smart-08679134-2113-4588-b5e3-2863aee77a6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989346493 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.3989346493
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.3867845297
Short name T234
Test name
Test status
Simulation time 456860729 ps
CPU time 11.77 seconds
Started Jul 25 05:21:59 PM PDT 24
Finished Jul 25 05:22:11 PM PDT 24
Peak memory 248828 kb
Host smart-eb957501-9df9-47d7-9f4a-8846a68bd028
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38678
45297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.3867845297
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.1413335538
Short name T266
Test name
Test status
Simulation time 551663161 ps
CPU time 32.99 seconds
Started Jul 25 05:32:40 PM PDT 24
Finished Jul 25 05:33:13 PM PDT 24
Peak memory 256332 kb
Host smart-7d506c37-f880-4742-acf5-a9bac1224b96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14133
35538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.1413335538
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.4045995707
Short name T303
Test name
Test status
Simulation time 32932343159 ps
CPU time 357.86 seconds
Started Jul 25 05:35:19 PM PDT 24
Finished Jul 25 05:41:17 PM PDT 24
Peak memory 248696 kb
Host smart-6c05ae3b-8c21-4bb3-9a2c-6b0a8fd933f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4045995707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.4045995707
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1823686369
Short name T145
Test name
Test status
Simulation time 6328002579 ps
CPU time 537.3 seconds
Started Jul 25 05:10:48 PM PDT 24
Finished Jul 25 05:19:46 PM PDT 24
Peak memory 265548 kb
Host smart-eacf57a1-73e1-4096-941a-55ba8c043997
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823686369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1823686369
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1370424233
Short name T158
Test name
Test status
Simulation time 4355201226 ps
CPU time 71.53 seconds
Started Jul 25 05:11:41 PM PDT 24
Finished Jul 25 05:12:53 PM PDT 24
Peak memory 240536 kb
Host smart-fdb35d27-353b-42f8-93d1-eb4caa962ba0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1370424233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1370424233
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.681802620
Short name T135
Test name
Test status
Simulation time 7786937813 ps
CPU time 271.18 seconds
Started Jul 25 05:10:46 PM PDT 24
Finished Jul 25 05:15:17 PM PDT 24
Peak memory 265500 kb
Host smart-37354441-167c-48ff-9e38-8f368fd9e5f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=681802620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_error
s.681802620
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.4269445020
Short name T157
Test name
Test status
Simulation time 635837156 ps
CPU time 25.24 seconds
Started Jul 25 05:11:42 PM PDT 24
Finished Jul 25 05:12:07 PM PDT 24
Peak memory 245728 kb
Host smart-9ceca0d6-0607-42c7-b579-bfa38691242e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4269445020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.4269445020
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.466716520
Short name T11
Test name
Test status
Simulation time 121555813515 ps
CPU time 2205.76 seconds
Started Jul 25 05:24:49 PM PDT 24
Finished Jul 25 06:01:36 PM PDT 24
Peak memory 287804 kb
Host smart-f2a8fe5f-4698-4b33-b02a-ca33280332c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466716520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.466716520
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2516661897
Short name T167
Test name
Test status
Simulation time 77931210 ps
CPU time 3.24 seconds
Started Jul 25 05:11:00 PM PDT 24
Finished Jul 25 05:11:03 PM PDT 24
Peak memory 237624 kb
Host smart-d80b5e0a-408f-4406-a3ce-7a6629cfb1ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2516661897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2516661897
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.3889285908
Short name T159
Test name
Test status
Simulation time 141253762 ps
CPU time 2.94 seconds
Started Jul 25 05:11:07 PM PDT 24
Finished Jul 25 05:11:10 PM PDT 24
Peak memory 237768 kb
Host smart-74f4a8c9-8e15-4223-9c91-343377b4d74d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3889285908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3889285908
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.4005503051
Short name T155
Test name
Test status
Simulation time 293986377 ps
CPU time 37.41 seconds
Started Jul 25 05:11:09 PM PDT 24
Finished Jul 25 05:11:47 PM PDT 24
Peak memory 237880 kb
Host smart-ff1e53ae-c028-477d-a136-81a52a4a84de
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4005503051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.4005503051
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1750340857
Short name T133
Test name
Test status
Simulation time 13068640847 ps
CPU time 158.16 seconds
Started Jul 25 05:11:31 PM PDT 24
Finished Jul 25 05:14:10 PM PDT 24
Peak memory 267400 kb
Host smart-8a8a55e1-14a1-4955-92f2-4fc53cd39c21
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1750340857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.1750340857
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2502470008
Short name T165
Test name
Test status
Simulation time 45568640 ps
CPU time 3.18 seconds
Started Jul 25 05:11:29 PM PDT 24
Finished Jul 25 05:11:32 PM PDT 24
Peak memory 237732 kb
Host smart-b6a23159-b49f-4335-9847-a07c91446eda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2502470008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2502470008
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.4277545303
Short name T122
Test name
Test status
Simulation time 6930324613 ps
CPU time 424.42 seconds
Started Jul 25 05:11:38 PM PDT 24
Finished Jul 25 05:18:43 PM PDT 24
Peak memory 273348 kb
Host smart-34c1a2a0-eae3-4bb6-bb37-eaf2650bf39e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4277545303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.4277545303
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.555659028
Short name T169
Test name
Test status
Simulation time 4719530746 ps
CPU time 79.19 seconds
Started Jul 25 05:11:49 PM PDT 24
Finished Jul 25 05:13:08 PM PDT 24
Peak memory 240544 kb
Host smart-1cc51047-365c-477c-865f-db836b1649c5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=555659028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.555659028
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.864370068
Short name T156
Test name
Test status
Simulation time 144119518 ps
CPU time 4.75 seconds
Started Jul 25 05:10:57 PM PDT 24
Finished Jul 25 05:11:02 PM PDT 24
Peak memory 236584 kb
Host smart-68a3380b-3e07-4abf-9e9e-a06aab937e30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=864370068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.864370068
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.357770284
Short name T168
Test name
Test status
Simulation time 1836519019 ps
CPU time 36.89 seconds
Started Jul 25 05:11:16 PM PDT 24
Finished Jul 25 05:11:53 PM PDT 24
Peak memory 240356 kb
Host smart-6d9c9396-b0ef-4525-87a9-18aff5804105
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=357770284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.357770284
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2510313889
Short name T151
Test name
Test status
Simulation time 3946038830 ps
CPU time 38.53 seconds
Started Jul 25 05:10:46 PM PDT 24
Finished Jul 25 05:11:25 PM PDT 24
Peak memory 237688 kb
Host smart-5d8b8398-bcca-4cbc-a30e-9fbc330ba2f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2510313889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.2510313889
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3823144209
Short name T162
Test name
Test status
Simulation time 68518571 ps
CPU time 4.77 seconds
Started Jul 25 05:11:20 PM PDT 24
Finished Jul 25 05:11:25 PM PDT 24
Peak memory 237768 kb
Host smart-24c3c736-b6ca-4f0f-8d9f-0ca55ca9979e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3823144209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3823144209
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.1183507141
Short name T149
Test name
Test status
Simulation time 38139394 ps
CPU time 2.26 seconds
Started Jul 25 05:11:20 PM PDT 24
Finished Jul 25 05:11:22 PM PDT 24
Peak memory 237476 kb
Host smart-be51a78f-5f54-4d85-a369-0db4bda3c851
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1183507141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.1183507141
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3500602677
Short name T172
Test name
Test status
Simulation time 103741533 ps
CPU time 2.66 seconds
Started Jul 25 05:11:27 PM PDT 24
Finished Jul 25 05:11:30 PM PDT 24
Peak memory 236612 kb
Host smart-88e87e7b-a2a1-4add-b7c6-6a4c501d5c97
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3500602677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3500602677
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.4128990330
Short name T166
Test name
Test status
Simulation time 2291926426 ps
CPU time 43.14 seconds
Started Jul 25 05:11:10 PM PDT 24
Finished Jul 25 05:11:53 PM PDT 24
Peak memory 237804 kb
Host smart-de8a7873-cc5b-4492-a336-5b4832cc314d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4128990330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.4128990330
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.3794150297
Short name T23
Test name
Test status
Simulation time 11130970270 ps
CPU time 1044.21 seconds
Started Jul 25 05:36:16 PM PDT 24
Finished Jul 25 05:53:41 PM PDT 24
Peak memory 290032 kb
Host smart-7974bf30-23a7-447f-b606-44071fa1a136
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794150297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.3794150297
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2600287084
Short name T726
Test name
Test status
Simulation time 1207298838 ps
CPU time 159.63 seconds
Started Jul 25 05:10:47 PM PDT 24
Finished Jul 25 05:13:27 PM PDT 24
Peak memory 241452 kb
Host smart-336e2cb6-c486-46db-ae1d-3b32233cf052
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2600287084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2600287084
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1573859540
Short name T742
Test name
Test status
Simulation time 17094066457 ps
CPU time 267.67 seconds
Started Jul 25 05:10:47 PM PDT 24
Finished Jul 25 05:15:15 PM PDT 24
Peak memory 237596 kb
Host smart-49d2e33b-97e0-41ba-b5ee-e0f5f5ab156d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1573859540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1573859540
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2076025270
Short name T774
Test name
Test status
Simulation time 421969071 ps
CPU time 10.78 seconds
Started Jul 25 05:10:47 PM PDT 24
Finished Jul 25 05:10:58 PM PDT 24
Peak memory 249052 kb
Host smart-d2044f4d-58e4-4f14-ab13-bb4b5e07bf75
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2076025270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2076025270
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.564541853
Short name T725
Test name
Test status
Simulation time 133881069 ps
CPU time 5.24 seconds
Started Jul 25 05:10:56 PM PDT 24
Finished Jul 25 05:11:01 PM PDT 24
Peak memory 248600 kb
Host smart-307894cf-c976-40fb-b38b-491fcbd3fcbe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564541853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.564541853
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.374843399
Short name T806
Test name
Test status
Simulation time 23170286 ps
CPU time 3.43 seconds
Started Jul 25 05:10:46 PM PDT 24
Finished Jul 25 05:10:50 PM PDT 24
Peak memory 237432 kb
Host smart-a8bf215a-56ed-40ce-b7ab-5528a08dab61
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=374843399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.374843399
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2590001414
Short name T818
Test name
Test status
Simulation time 57297370 ps
CPU time 1.42 seconds
Started Jul 25 05:10:47 PM PDT 24
Finished Jul 25 05:10:49 PM PDT 24
Peak memory 236496 kb
Host smart-bdeee7e2-94c9-4c58-ad7a-014c3dbc3458
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2590001414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2590001414
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.302260914
Short name T724
Test name
Test status
Simulation time 309458213 ps
CPU time 19.18 seconds
Started Jul 25 05:10:44 PM PDT 24
Finished Jul 25 05:11:03 PM PDT 24
Peak memory 244840 kb
Host smart-0e61379d-a478-4884-ad80-63162f545750
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=302260914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outs
tanding.302260914
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1738000920
Short name T756
Test name
Test status
Simulation time 989262191 ps
CPU time 18.43 seconds
Started Jul 25 05:10:47 PM PDT 24
Finished Jul 25 05:11:05 PM PDT 24
Peak memory 254320 kb
Host smart-abca9bf5-051d-4391-960d-e7d5fc4fae48
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1738000920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1738000920
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2138448611
Short name T759
Test name
Test status
Simulation time 3414659612 ps
CPU time 282.36 seconds
Started Jul 25 05:10:56 PM PDT 24
Finished Jul 25 05:15:39 PM PDT 24
Peak memory 241024 kb
Host smart-90969658-8780-4a86-80ed-6b2cd8c2814b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2138448611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2138448611
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.4216871147
Short name T822
Test name
Test status
Simulation time 23783989965 ps
CPU time 412.44 seconds
Started Jul 25 05:11:01 PM PDT 24
Finished Jul 25 05:17:53 PM PDT 24
Peak memory 237132 kb
Host smart-88e8acc6-c9e0-4147-a04a-1b6c91a60456
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4216871147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.4216871147
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1470060103
Short name T763
Test name
Test status
Simulation time 98159932 ps
CPU time 8.72 seconds
Started Jul 25 05:10:57 PM PDT 24
Finished Jul 25 05:11:06 PM PDT 24
Peak memory 249096 kb
Host smart-992ebea5-59b5-44c2-ad6a-5b6fa282dc7c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1470060103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1470060103
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3676362640
Short name T173
Test name
Test status
Simulation time 101026825 ps
CPU time 8.15 seconds
Started Jul 25 05:10:57 PM PDT 24
Finished Jul 25 05:11:06 PM PDT 24
Peak memory 239444 kb
Host smart-c49c7029-f88a-4b41-8001-023a8110c4ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3676362640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3676362640
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1748980660
Short name T799
Test name
Test status
Simulation time 131587374 ps
CPU time 5.16 seconds
Started Jul 25 05:11:00 PM PDT 24
Finished Jul 25 05:11:05 PM PDT 24
Peak memory 237472 kb
Host smart-8c5db576-5b52-46c7-b64d-a264f0139148
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1748980660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1748980660
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.822710
Short name T731
Test name
Test status
Simulation time 14864172 ps
CPU time 1.37 seconds
Started Jul 25 05:10:58 PM PDT 24
Finished Jul 25 05:10:59 PM PDT 24
Peak memory 237488 kb
Host smart-4b212872-b2ba-43df-aff0-605b1ca490d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=822710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.822710
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.901399038
Short name T810
Test name
Test status
Simulation time 491413596 ps
CPU time 19.86 seconds
Started Jul 25 05:10:59 PM PDT 24
Finished Jul 25 05:11:19 PM PDT 24
Peak memory 245688 kb
Host smart-73fe7f48-188a-4cc0-9976-540c6b5a779c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=901399038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outs
tanding.901399038
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.2340998734
Short name T718
Test name
Test status
Simulation time 1209267838 ps
CPU time 19.69 seconds
Started Jul 25 05:10:56 PM PDT 24
Finished Jul 25 05:11:16 PM PDT 24
Peak memory 248724 kb
Host smart-27d5a40f-cef2-4107-a357-d0bdc14f141c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2340998734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.2340998734
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2610255581
Short name T362
Test name
Test status
Simulation time 56703537 ps
CPU time 7.19 seconds
Started Jul 25 05:11:27 PM PDT 24
Finished Jul 25 05:11:34 PM PDT 24
Peak memory 251688 kb
Host smart-d38686be-9449-45e0-ae6e-ed972294f439
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610255581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2610255581
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1821154101
Short name T171
Test name
Test status
Simulation time 78228654 ps
CPU time 3.98 seconds
Started Jul 25 05:11:18 PM PDT 24
Finished Jul 25 05:11:22 PM PDT 24
Peak memory 237476 kb
Host smart-5dd49575-1c37-409b-a400-583296da7bb4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1821154101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1821154101
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.498851099
Short name T827
Test name
Test status
Simulation time 516890347 ps
CPU time 18.35 seconds
Started Jul 25 05:11:21 PM PDT 24
Finished Jul 25 05:11:39 PM PDT 24
Peak memory 244792 kb
Host smart-62f572ca-2433-45ad-a471-30f9e084e1c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=498851099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_out
standing.498851099
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.4125787308
Short name T797
Test name
Test status
Simulation time 5717585513 ps
CPU time 185.62 seconds
Started Jul 25 05:11:16 PM PDT 24
Finished Jul 25 05:14:22 PM PDT 24
Peak memory 265420 kb
Host smart-caac908e-eeb0-4509-9ca2-6abbdb171eaa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4125787308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.4125787308
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.38266065
Short name T823
Test name
Test status
Simulation time 570102311 ps
CPU time 12.01 seconds
Started Jul 25 05:11:17 PM PDT 24
Finished Jul 25 05:11:29 PM PDT 24
Peak memory 248948 kb
Host smart-f15f11ef-0ad5-4913-9d3a-61ae48a9f2bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=38266065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.38266065
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2617841285
Short name T233
Test name
Test status
Simulation time 677853692 ps
CPU time 42.04 seconds
Started Jul 25 05:11:19 PM PDT 24
Finished Jul 25 05:12:02 PM PDT 24
Peak memory 237548 kb
Host smart-637b79e3-7e49-45b9-ac42-2bcb5b5cc4e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2617841285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2617841285
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.281456039
Short name T735
Test name
Test status
Simulation time 35207738 ps
CPU time 5.17 seconds
Started Jul 25 05:11:16 PM PDT 24
Finished Jul 25 05:11:22 PM PDT 24
Peak memory 242228 kb
Host smart-4d0978f5-4a61-48ea-b56c-8088f897a6bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281456039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.alert_handler_csr_mem_rw_with_rand_reset.281456039
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3021745098
Short name T751
Test name
Test status
Simulation time 135748846 ps
CPU time 5.15 seconds
Started Jul 25 05:11:18 PM PDT 24
Finished Jul 25 05:11:23 PM PDT 24
Peak memory 237408 kb
Host smart-4a4b05d7-857f-4c03-82d0-086e71f3d130
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3021745098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.3021745098
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.1751948704
Short name T152
Test name
Test status
Simulation time 14926962 ps
CPU time 1.36 seconds
Started Jul 25 05:11:16 PM PDT 24
Finished Jul 25 05:11:18 PM PDT 24
Peak memory 235596 kb
Host smart-fcbb2574-6700-47c2-ad46-a6d17dc2e98c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1751948704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.1751948704
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2105972880
Short name T185
Test name
Test status
Simulation time 183325597 ps
CPU time 20.54 seconds
Started Jul 25 05:11:15 PM PDT 24
Finished Jul 25 05:11:36 PM PDT 24
Peak memory 248704 kb
Host smart-4f24d750-1883-409c-9e5e-72c55970190c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2105972880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2105972880
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.286892707
Short name T136
Test name
Test status
Simulation time 5579610469 ps
CPU time 124.87 seconds
Started Jul 25 05:11:22 PM PDT 24
Finished Jul 25 05:13:27 PM PDT 24
Peak memory 257116 kb
Host smart-b382d5b9-9219-4d18-a76f-983a52e1434d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=286892707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.286892707
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.1478911385
Short name T229
Test name
Test status
Simulation time 100294922 ps
CPU time 7.17 seconds
Started Jul 25 05:11:20 PM PDT 24
Finished Jul 25 05:11:27 PM PDT 24
Peak memory 248684 kb
Host smart-db936a33-e860-4ce1-9bbf-423ffeda563a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1478911385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1478911385
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3620256751
Short name T357
Test name
Test status
Simulation time 60341920 ps
CPU time 8.8 seconds
Started Jul 25 05:11:17 PM PDT 24
Finished Jul 25 05:11:26 PM PDT 24
Peak memory 249680 kb
Host smart-c9059879-535d-47cc-b7e5-5e06c29d79e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620256751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3620256751
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.3026105985
Short name T792
Test name
Test status
Simulation time 20912507 ps
CPU time 3.46 seconds
Started Jul 25 05:11:23 PM PDT 24
Finished Jul 25 05:11:26 PM PDT 24
Peak memory 237424 kb
Host smart-6445bda9-b3cb-49cc-b72f-62dc61add849
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3026105985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.3026105985
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2874706296
Short name T784
Test name
Test status
Simulation time 25387853 ps
CPU time 1.46 seconds
Started Jul 25 05:11:23 PM PDT 24
Finished Jul 25 05:11:24 PM PDT 24
Peak memory 236512 kb
Host smart-1351f050-c6c8-42dd-bd19-351ce7e6628d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2874706296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2874706296
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3714062779
Short name T803
Test name
Test status
Simulation time 6070328935 ps
CPU time 36.1 seconds
Started Jul 25 05:11:16 PM PDT 24
Finished Jul 25 05:11:53 PM PDT 24
Peak memory 245804 kb
Host smart-04022165-e5da-4731-be58-5e76cddf255b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3714062779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.3714062779
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.295281934
Short name T791
Test name
Test status
Simulation time 16462349251 ps
CPU time 198.19 seconds
Started Jul 25 05:11:29 PM PDT 24
Finished Jul 25 05:14:47 PM PDT 24
Peak memory 265372 kb
Host smart-54ca25c6-4d93-4382-ada5-878257068fa4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=295281934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_erro
rs.295281934
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2065936419
Short name T117
Test name
Test status
Simulation time 5638282146 ps
CPU time 297.46 seconds
Started Jul 25 05:11:18 PM PDT 24
Finished Jul 25 05:16:15 PM PDT 24
Peak memory 265652 kb
Host smart-911c1e96-5d51-4d91-9f93-da2b4d329d19
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065936419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2065936419
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2481923688
Short name T758
Test name
Test status
Simulation time 1462458753 ps
CPU time 26.04 seconds
Started Jul 25 05:11:18 PM PDT 24
Finished Jul 25 05:11:44 PM PDT 24
Peak memory 253172 kb
Host smart-dbc629e9-5a69-49a2-ac10-f601ba8fa53d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2481923688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2481923688
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3559181559
Short name T762
Test name
Test status
Simulation time 105982024 ps
CPU time 8.48 seconds
Started Jul 25 05:11:48 PM PDT 24
Finished Jul 25 05:11:56 PM PDT 24
Peak memory 252160 kb
Host smart-a9d9ea27-a523-45cf-b6bd-6219e2598a4c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559181559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.3559181559
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2264264201
Short name T359
Test name
Test status
Simulation time 315832178 ps
CPU time 5.13 seconds
Started Jul 25 05:11:29 PM PDT 24
Finished Jul 25 05:11:34 PM PDT 24
Peak memory 236608 kb
Host smart-46db605e-f6ba-442e-92b1-101ad70d9075
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2264264201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2264264201
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3149276086
Short name T796
Test name
Test status
Simulation time 9834345 ps
CPU time 1.61 seconds
Started Jul 25 05:11:27 PM PDT 24
Finished Jul 25 05:11:29 PM PDT 24
Peak memory 237488 kb
Host smart-36eca1c1-a133-4e05-bcb9-96e5c9b3cfb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3149276086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3149276086
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2148417716
Short name T802
Test name
Test status
Simulation time 1379538479 ps
CPU time 49.72 seconds
Started Jul 25 05:11:28 PM PDT 24
Finished Jul 25 05:12:18 PM PDT 24
Peak memory 245620 kb
Host smart-11ec7684-6386-4eb0-a6a9-b46606ecac51
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2148417716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2148417716
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1224709132
Short name T124
Test name
Test status
Simulation time 3773682836 ps
CPU time 155.35 seconds
Started Jul 25 05:11:16 PM PDT 24
Finished Jul 25 05:13:52 PM PDT 24
Peak memory 269084 kb
Host smart-fc5a717d-3fcb-47b3-9db3-e1d8c3949d23
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1224709132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1224709132
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.300748626
Short name T716
Test name
Test status
Simulation time 28558994 ps
CPU time 4.41 seconds
Started Jul 25 05:11:17 PM PDT 24
Finished Jul 25 05:11:22 PM PDT 24
Peak memory 251516 kb
Host smart-1b43b2bf-81c5-421e-9edd-a7b7c3d0f8df
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=300748626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.300748626
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.267560864
Short name T361
Test name
Test status
Simulation time 261681619 ps
CPU time 3.95 seconds
Started Jul 25 05:11:27 PM PDT 24
Finished Jul 25 05:11:31 PM PDT 24
Peak memory 240056 kb
Host smart-ab6cf76f-74cf-4321-af62-606b9ea2d31c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267560864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.alert_handler_csr_mem_rw_with_rand_reset.267560864
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2748827927
Short name T768
Test name
Test status
Simulation time 54123129 ps
CPU time 5.72 seconds
Started Jul 25 05:11:31 PM PDT 24
Finished Jul 25 05:11:37 PM PDT 24
Peak memory 237404 kb
Host smart-af10dcfd-18c1-43af-bc23-a9255de2708a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2748827927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2748827927
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.1225605383
Short name T831
Test name
Test status
Simulation time 7619416 ps
CPU time 1.32 seconds
Started Jul 25 05:11:29 PM PDT 24
Finished Jul 25 05:11:30 PM PDT 24
Peak memory 236608 kb
Host smart-6286ea03-5b8d-4c7d-b645-be4e299c0c9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1225605383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.1225605383
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.560618831
Short name T740
Test name
Test status
Simulation time 515961855 ps
CPU time 35.17 seconds
Started Jul 25 05:11:29 PM PDT 24
Finished Jul 25 05:12:04 PM PDT 24
Peak memory 245684 kb
Host smart-40c17ab5-a64f-4bd6-aefe-fbdde450173d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=560618831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.560618831
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.4156446213
Short name T146
Test name
Test status
Simulation time 32970134193 ps
CPU time 1209.44 seconds
Started Jul 25 05:11:28 PM PDT 24
Finished Jul 25 05:31:38 PM PDT 24
Peak memory 273200 kb
Host smart-2adbd559-8b60-40ee-a793-f0b7c012ed53
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156446213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.4156446213
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3465174604
Short name T738
Test name
Test status
Simulation time 741746850 ps
CPU time 9.44 seconds
Started Jul 25 05:11:48 PM PDT 24
Finished Jul 25 05:11:58 PM PDT 24
Peak memory 248524 kb
Host smart-d633c1d6-423b-4606-9ca7-fbee23a7a510
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3465174604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3465174604
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.1988260772
Short name T163
Test name
Test status
Simulation time 2133344341 ps
CPU time 30.01 seconds
Started Jul 25 05:11:25 PM PDT 24
Finished Jul 25 05:11:55 PM PDT 24
Peak memory 240376 kb
Host smart-65b1a85c-4193-41f3-8a8c-cd0153959163
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1988260772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1988260772
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2209690432
Short name T804
Test name
Test status
Simulation time 69288290 ps
CPU time 5.47 seconds
Started Jul 25 05:11:29 PM PDT 24
Finished Jul 25 05:11:34 PM PDT 24
Peak memory 248616 kb
Host smart-32ea498e-32a8-41db-bc1e-5081ce6603ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209690432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2209690432
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2513830532
Short name T800
Test name
Test status
Simulation time 49700466 ps
CPU time 5.53 seconds
Started Jul 25 05:11:27 PM PDT 24
Finished Jul 25 05:11:33 PM PDT 24
Peak memory 237516 kb
Host smart-322a0928-5436-42d1-9944-9f8c41ce3b6e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2513830532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2513830532
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.237946917
Short name T720
Test name
Test status
Simulation time 10288360 ps
CPU time 1.36 seconds
Started Jul 25 05:11:27 PM PDT 24
Finished Jul 25 05:11:28 PM PDT 24
Peak memory 237484 kb
Host smart-90831156-c26c-4e6c-95fc-c975d7184839
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=237946917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.237946917
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3540210367
Short name T781
Test name
Test status
Simulation time 86791651 ps
CPU time 11.66 seconds
Started Jul 25 05:11:30 PM PDT 24
Finished Jul 25 05:11:42 PM PDT 24
Peak memory 245660 kb
Host smart-c90274a1-7faa-43d7-b260-9f8299343330
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3540210367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.3540210367
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.4070612610
Short name T366
Test name
Test status
Simulation time 24194542430 ps
CPU time 507.02 seconds
Started Jul 25 05:11:26 PM PDT 24
Finished Jul 25 05:19:53 PM PDT 24
Peak memory 269460 kb
Host smart-e090f473-0407-43c8-bbc2-928ef11b2ea6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070612610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.4070612610
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1506199518
Short name T816
Test name
Test status
Simulation time 530609575 ps
CPU time 17.1 seconds
Started Jul 25 05:11:28 PM PDT 24
Finished Jul 25 05:11:45 PM PDT 24
Peak memory 248052 kb
Host smart-2ce617f2-a168-4be4-a6cd-8ff02c4e7e09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1506199518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1506199518
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3486997445
Short name T776
Test name
Test status
Simulation time 37070509 ps
CPU time 6.13 seconds
Started Jul 25 05:11:38 PM PDT 24
Finished Jul 25 05:11:44 PM PDT 24
Peak memory 248836 kb
Host smart-a79610cd-76a1-45f6-8028-a0b252986ec7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486997445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.3486997445
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.3313887897
Short name T739
Test name
Test status
Simulation time 347405150 ps
CPU time 7.96 seconds
Started Jul 25 05:11:29 PM PDT 24
Finished Jul 25 05:11:37 PM PDT 24
Peak memory 240404 kb
Host smart-d79771d5-a1cf-41b6-840f-dd5a8a7beee7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3313887897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.3313887897
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.2824840576
Short name T766
Test name
Test status
Simulation time 14066120 ps
CPU time 1.4 seconds
Started Jul 25 05:11:48 PM PDT 24
Finished Jul 25 05:11:49 PM PDT 24
Peak memory 236572 kb
Host smart-185b2594-e649-497b-ab52-01d05da74936
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2824840576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.2824840576
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1876125278
Short name T753
Test name
Test status
Simulation time 655267387 ps
CPU time 42.25 seconds
Started Jul 25 05:11:37 PM PDT 24
Finished Jul 25 05:12:20 PM PDT 24
Peak memory 245676 kb
Host smart-07f664b4-2579-46f0-84db-04a528a8305f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1876125278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1876125278
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1098774492
Short name T730
Test name
Test status
Simulation time 1033821357 ps
CPU time 19.34 seconds
Started Jul 25 05:11:30 PM PDT 24
Finished Jul 25 05:11:50 PM PDT 24
Peak memory 255596 kb
Host smart-7b3c7d6a-c83d-46bb-839f-16b6a2d047c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1098774492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1098774492
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.2465915277
Short name T190
Test name
Test status
Simulation time 286759905 ps
CPU time 6.74 seconds
Started Jul 25 05:11:39 PM PDT 24
Finished Jul 25 05:11:46 PM PDT 24
Peak memory 240840 kb
Host smart-0901c0a3-2f5c-4488-ad79-d92262242aaa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465915277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.2465915277
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.566730662
Short name T812
Test name
Test status
Simulation time 115279802 ps
CPU time 7.89 seconds
Started Jul 25 05:11:50 PM PDT 24
Finished Jul 25 05:11:58 PM PDT 24
Peak memory 240416 kb
Host smart-29d83e2a-086c-473c-9cfb-599c41a3c5e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=566730662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.566730662
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.1549457332
Short name T757
Test name
Test status
Simulation time 27815427 ps
CPU time 1.26 seconds
Started Jul 25 05:11:50 PM PDT 24
Finished Jul 25 05:11:52 PM PDT 24
Peak memory 236476 kb
Host smart-5ff2dca4-f383-479e-86e8-4df313d3685c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1549457332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.1549457332
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.495193823
Short name T186
Test name
Test status
Simulation time 348475757 ps
CPU time 25.97 seconds
Started Jul 25 05:11:39 PM PDT 24
Finished Jul 25 05:12:06 PM PDT 24
Peak memory 240392 kb
Host smart-10713699-2ae8-480d-ad02-47b6f75307cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=495193823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out
standing.495193823
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3886841876
Short name T126
Test name
Test status
Simulation time 7575193516 ps
CPU time 480.31 seconds
Started Jul 25 05:11:36 PM PDT 24
Finished Jul 25 05:19:37 PM PDT 24
Peak memory 265652 kb
Host smart-a14525fd-8118-443d-a8c3-c426f258b2c7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886841876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3886841876
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2028918807
Short name T719
Test name
Test status
Simulation time 2362013217 ps
CPU time 16.56 seconds
Started Jul 25 05:11:42 PM PDT 24
Finished Jul 25 05:11:58 PM PDT 24
Peak memory 254740 kb
Host smart-1b39e32a-2748-474a-a886-1d26aa020a03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2028918807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2028918807
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2373427983
Short name T805
Test name
Test status
Simulation time 147324767 ps
CPU time 6.65 seconds
Started Jul 25 05:11:42 PM PDT 24
Finished Jul 25 05:11:49 PM PDT 24
Peak memory 240324 kb
Host smart-f8436095-444a-4b75-b2cc-b881ebed4e75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373427983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.2373427983
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.274440058
Short name T824
Test name
Test status
Simulation time 23786518 ps
CPU time 3.57 seconds
Started Jul 25 05:11:36 PM PDT 24
Finished Jul 25 05:11:40 PM PDT 24
Peak memory 237412 kb
Host smart-71136739-5f6f-46e3-b53c-0ce8206338a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=274440058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.274440058
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.1857082003
Short name T815
Test name
Test status
Simulation time 19200030 ps
CPU time 1.42 seconds
Started Jul 25 05:11:49 PM PDT 24
Finished Jul 25 05:11:51 PM PDT 24
Peak memory 236500 kb
Host smart-0dd9572f-59c5-4cd2-9d9a-ce8f14715414
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1857082003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.1857082003
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2741119471
Short name T747
Test name
Test status
Simulation time 693677164 ps
CPU time 20.9 seconds
Started Jul 25 05:11:37 PM PDT 24
Finished Jul 25 05:11:58 PM PDT 24
Peak memory 248692 kb
Host smart-6d61757c-f670-492c-9d56-99e1cc6ced3e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2741119471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.2741119471
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.1779540320
Short name T128
Test name
Test status
Simulation time 7990951933 ps
CPU time 208.83 seconds
Started Jul 25 05:11:37 PM PDT 24
Finished Jul 25 05:15:06 PM PDT 24
Peak memory 265384 kb
Host smart-3747fe3e-51cc-4a31-9e8a-50d351f6db16
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1779540320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.1779540320
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.826461053
Short name T363
Test name
Test status
Simulation time 118115407279 ps
CPU time 434.89 seconds
Started Jul 25 05:11:38 PM PDT 24
Finished Jul 25 05:18:53 PM PDT 24
Peak memory 268820 kb
Host smart-48fe62e2-bdff-4d39-bbe6-9e9ec286dc65
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826461053 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.826461053
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1713971200
Short name T817
Test name
Test status
Simulation time 282427387 ps
CPU time 19.66 seconds
Started Jul 25 05:11:38 PM PDT 24
Finished Jul 25 05:11:58 PM PDT 24
Peak memory 254368 kb
Host smart-e348ac2f-568c-4d3c-80e2-d97795b91a10
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1713971200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1713971200
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2985871036
Short name T358
Test name
Test status
Simulation time 556714166 ps
CPU time 11.97 seconds
Started Jul 25 05:11:48 PM PDT 24
Finished Jul 25 05:12:00 PM PDT 24
Peak memory 256752 kb
Host smart-dbbddb1c-ec71-4ab9-b6fc-588a3f949b80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985871036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2985871036
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1369989084
Short name T743
Test name
Test status
Simulation time 415708167 ps
CPU time 7.67 seconds
Started Jul 25 05:11:36 PM PDT 24
Finished Jul 25 05:11:44 PM PDT 24
Peak memory 236612 kb
Host smart-38419383-41dd-4edc-891c-6c84dcc16248
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1369989084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1369989084
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.4091436444
Short name T808
Test name
Test status
Simulation time 32512550 ps
CPU time 1.36 seconds
Started Jul 25 05:11:37 PM PDT 24
Finished Jul 25 05:11:39 PM PDT 24
Peak memory 236508 kb
Host smart-8b3359db-1757-4bd1-9b9b-d04a232a3f3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4091436444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.4091436444
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.409575866
Short name T749
Test name
Test status
Simulation time 319141353 ps
CPU time 22.13 seconds
Started Jul 25 05:11:48 PM PDT 24
Finished Jul 25 05:12:11 PM PDT 24
Peak memory 245676 kb
Host smart-48496d86-f64a-483e-8e25-35cddc92f22e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=409575866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_out
standing.409575866
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3733114456
Short name T116
Test name
Test status
Simulation time 4072814376 ps
CPU time 310.28 seconds
Started Jul 25 05:11:40 PM PDT 24
Finished Jul 25 05:16:50 PM PDT 24
Peak memory 265448 kb
Host smart-0c8ab91d-c8cd-402b-a7a3-ea56b47f7cfb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3733114456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3733114456
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.501483630
Short name T148
Test name
Test status
Simulation time 9313807165 ps
CPU time 622.43 seconds
Started Jul 25 05:11:39 PM PDT 24
Finished Jul 25 05:22:01 PM PDT 24
Peak memory 265520 kb
Host smart-d05bec72-9709-4526-b923-ef270a9cdb63
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501483630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.501483630
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.1279370548
Short name T714
Test name
Test status
Simulation time 5652605704 ps
CPU time 26.68 seconds
Started Jul 25 05:11:42 PM PDT 24
Finished Jul 25 05:12:09 PM PDT 24
Peak memory 254824 kb
Host smart-1cd73eab-c594-406a-97ce-d01eaadfc536
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1279370548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.1279370548
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2029064369
Short name T778
Test name
Test status
Simulation time 2130579866 ps
CPU time 77.19 seconds
Started Jul 25 05:10:58 PM PDT 24
Finished Jul 25 05:12:15 PM PDT 24
Peak memory 240420 kb
Host smart-fe169a66-fc60-493a-baa6-723516d21c44
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2029064369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.2029064369
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.395213486
Short name T813
Test name
Test status
Simulation time 1708593349 ps
CPU time 197.35 seconds
Started Jul 25 05:10:59 PM PDT 24
Finished Jul 25 05:14:16 PM PDT 24
Peak memory 236556 kb
Host smart-7b5e0734-c9dd-4d23-bace-bbf9e717a908
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=395213486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.395213486
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.647823391
Short name T826
Test name
Test status
Simulation time 38995686 ps
CPU time 3.59 seconds
Started Jul 25 05:10:58 PM PDT 24
Finished Jul 25 05:11:02 PM PDT 24
Peak memory 248640 kb
Host smart-b809e350-45a9-4b41-82c9-2c14b37ed1d8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=647823391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.647823391
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1449926610
Short name T770
Test name
Test status
Simulation time 101648518 ps
CPU time 9.12 seconds
Started Jul 25 05:10:58 PM PDT 24
Finished Jul 25 05:11:07 PM PDT 24
Peak memory 240368 kb
Host smart-293712b4-887b-42f6-a4fd-b0f5166e64da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449926610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1449926610
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.420665449
Short name T772
Test name
Test status
Simulation time 149306103 ps
CPU time 5.37 seconds
Started Jul 25 05:10:56 PM PDT 24
Finished Jul 25 05:11:01 PM PDT 24
Peak memory 240424 kb
Host smart-69d779a2-7996-41c9-911f-8bf42db6f42f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=420665449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.420665449
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3902475628
Short name T154
Test name
Test status
Simulation time 17122128 ps
CPU time 1.76 seconds
Started Jul 25 05:10:59 PM PDT 24
Finished Jul 25 05:11:01 PM PDT 24
Peak memory 237476 kb
Host smart-14301418-17c9-4ac9-9d84-d2461fe117f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3902475628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3902475628
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3397756262
Short name T765
Test name
Test status
Simulation time 581788208 ps
CPU time 32.62 seconds
Started Jul 25 05:10:56 PM PDT 24
Finished Jul 25 05:11:28 PM PDT 24
Peak memory 244776 kb
Host smart-529a8aa4-1437-4bc7-a243-c9c46d31cc78
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3397756262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3397756262
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2778832950
Short name T131
Test name
Test status
Simulation time 3375322585 ps
CPU time 195.26 seconds
Started Jul 25 05:10:58 PM PDT 24
Finished Jul 25 05:14:14 PM PDT 24
Peak memory 265448 kb
Host smart-78e7f88f-baea-403c-ac73-5e80a19ce0b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2778832950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2778832950
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.296549164
Short name T141
Test name
Test status
Simulation time 52643479118 ps
CPU time 683.93 seconds
Started Jul 25 05:10:56 PM PDT 24
Finished Jul 25 05:22:21 PM PDT 24
Peak memory 265488 kb
Host smart-163dc846-355c-497e-a66f-90480e76c064
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296549164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.296549164
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2150082544
Short name T775
Test name
Test status
Simulation time 261405113 ps
CPU time 9.06 seconds
Started Jul 25 05:11:00 PM PDT 24
Finished Jul 25 05:11:09 PM PDT 24
Peak memory 248096 kb
Host smart-46633153-9fcc-443f-8f33-2f2d7e754c68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2150082544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2150082544
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.4109113425
Short name T787
Test name
Test status
Simulation time 17140442 ps
CPU time 1.33 seconds
Started Jul 25 05:11:51 PM PDT 24
Finished Jul 25 05:11:52 PM PDT 24
Peak memory 235588 kb
Host smart-cce84029-b618-47c1-9436-c93a9a3bab3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4109113425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.4109113425
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1546119731
Short name T811
Test name
Test status
Simulation time 13774529 ps
CPU time 1.36 seconds
Started Jul 25 05:11:38 PM PDT 24
Finished Jul 25 05:11:40 PM PDT 24
Peak memory 237452 kb
Host smart-c204c24f-0660-4837-a235-f20de67ef525
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1546119731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1546119731
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.2298173637
Short name T744
Test name
Test status
Simulation time 58928842 ps
CPU time 1.26 seconds
Started Jul 25 05:11:49 PM PDT 24
Finished Jul 25 05:11:51 PM PDT 24
Peak memory 236604 kb
Host smart-24eb72ac-ec54-4644-a8c2-036a748c3925
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2298173637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.2298173637
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.637120507
Short name T733
Test name
Test status
Simulation time 11269945 ps
CPU time 1.32 seconds
Started Jul 25 05:11:45 PM PDT 24
Finished Jul 25 05:11:47 PM PDT 24
Peak memory 235452 kb
Host smart-d6cd7f27-eb25-40da-ba53-371900c2ab49
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=637120507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.637120507
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3487138637
Short name T809
Test name
Test status
Simulation time 13118433 ps
CPU time 1.42 seconds
Started Jul 25 05:11:47 PM PDT 24
Finished Jul 25 05:11:49 PM PDT 24
Peak memory 237416 kb
Host smart-7cd1126d-6336-444c-8b2d-a134a57cbb68
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3487138637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3487138637
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1448674791
Short name T820
Test name
Test status
Simulation time 12898653 ps
CPU time 1.65 seconds
Started Jul 25 05:11:47 PM PDT 24
Finished Jul 25 05:11:48 PM PDT 24
Peak memory 237492 kb
Host smart-c80912a1-68ce-4025-a4f1-1e705d3da7ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1448674791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1448674791
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3644216427
Short name T745
Test name
Test status
Simulation time 9082466 ps
CPU time 1.62 seconds
Started Jul 25 05:11:50 PM PDT 24
Finished Jul 25 05:11:51 PM PDT 24
Peak memory 237484 kb
Host smart-c2763c2f-1bad-4ba7-9fb7-b0e01c38180e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3644216427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3644216427
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.1571074212
Short name T351
Test name
Test status
Simulation time 18878185 ps
CPU time 1.35 seconds
Started Jul 25 05:11:47 PM PDT 24
Finished Jul 25 05:11:48 PM PDT 24
Peak memory 237504 kb
Host smart-f14c70fb-a4b4-4ac6-b98c-fab07ff38e7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1571074212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.1571074212
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.1420532519
Short name T785
Test name
Test status
Simulation time 8774808 ps
CPU time 1.32 seconds
Started Jul 25 05:11:45 PM PDT 24
Finished Jul 25 05:11:47 PM PDT 24
Peak memory 237472 kb
Host smart-6330dea9-fdf0-457f-a7b8-c3863a45d9a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1420532519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.1420532519
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.3688897922
Short name T750
Test name
Test status
Simulation time 3293553532 ps
CPU time 125.31 seconds
Started Jul 25 05:10:59 PM PDT 24
Finished Jul 25 05:13:05 PM PDT 24
Peak memory 237604 kb
Host smart-14dfba08-e146-4d90-b7b8-39600c7196f6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3688897922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.3688897922
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3633769755
Short name T798
Test name
Test status
Simulation time 6533272769 ps
CPU time 181.98 seconds
Started Jul 25 05:10:56 PM PDT 24
Finished Jul 25 05:13:58 PM PDT 24
Peak memory 236716 kb
Host smart-1bcce739-9adb-496a-9cce-0c6946ddf213
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3633769755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3633769755
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1184772852
Short name T790
Test name
Test status
Simulation time 66811381 ps
CPU time 5.87 seconds
Started Jul 25 05:10:56 PM PDT 24
Finished Jul 25 05:11:02 PM PDT 24
Peak memory 248604 kb
Host smart-20ba1d5e-86ce-4c6b-9d10-f3d5b0f5fa6b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1184772852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1184772852
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.652881946
Short name T189
Test name
Test status
Simulation time 62908584 ps
CPU time 5.35 seconds
Started Jul 25 05:10:57 PM PDT 24
Finished Jul 25 05:11:02 PM PDT 24
Peak memory 252324 kb
Host smart-fd7efacd-c28b-42f3-b039-57cb90120af9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=652881946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 3.alert_handler_csr_mem_rw_with_rand_reset.652881946
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1489810103
Short name T773
Test name
Test status
Simulation time 53751366 ps
CPU time 4.79 seconds
Started Jul 25 05:11:01 PM PDT 24
Finished Jul 25 05:11:06 PM PDT 24
Peak memory 239816 kb
Host smart-40afc6e8-8e50-4ea1-9c14-df772876b13d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1489810103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1489810103
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2481814326
Short name T752
Test name
Test status
Simulation time 1335595293 ps
CPU time 21.57 seconds
Started Jul 25 05:10:56 PM PDT 24
Finished Jul 25 05:11:18 PM PDT 24
Peak memory 245620 kb
Host smart-9e0af75d-39a2-4730-8eda-f404cdb399dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2481814326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2481814326
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1974799252
Short name T147
Test name
Test status
Simulation time 30889959824 ps
CPU time 582.58 seconds
Started Jul 25 05:10:55 PM PDT 24
Finished Jul 25 05:20:38 PM PDT 24
Peak memory 265384 kb
Host smart-a178f4ac-3363-4aae-b15e-ce13238567ee
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974799252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1974799252
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3221586738
Short name T736
Test name
Test status
Simulation time 413587824 ps
CPU time 9.02 seconds
Started Jul 25 05:10:58 PM PDT 24
Finished Jul 25 05:11:07 PM PDT 24
Peak memory 248628 kb
Host smart-30d69549-81d2-4fe6-8b24-473c39b4715c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3221586738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3221586738
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3999096144
Short name T782
Test name
Test status
Simulation time 10285776 ps
CPU time 1.35 seconds
Started Jul 25 05:11:45 PM PDT 24
Finished Jul 25 05:11:46 PM PDT 24
Peak memory 235484 kb
Host smart-454d397c-2917-4203-a47d-5480333fab17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3999096144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3999096144
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.2589547212
Short name T153
Test name
Test status
Simulation time 8501421 ps
CPU time 1.35 seconds
Started Jul 25 05:11:48 PM PDT 24
Finished Jul 25 05:11:50 PM PDT 24
Peak memory 237428 kb
Host smart-7688bdcb-5af4-47f1-a868-fba7e5940350
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2589547212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.2589547212
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.404819336
Short name T789
Test name
Test status
Simulation time 13226034 ps
CPU time 1.53 seconds
Started Jul 25 05:11:58 PM PDT 24
Finished Jul 25 05:11:59 PM PDT 24
Peak memory 237464 kb
Host smart-7643924b-a8cd-4f87-ab27-d1df927ff7d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=404819336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.404819336
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.4017085664
Short name T746
Test name
Test status
Simulation time 78389594 ps
CPU time 1.4 seconds
Started Jul 25 05:11:49 PM PDT 24
Finished Jul 25 05:11:50 PM PDT 24
Peak memory 236496 kb
Host smart-c5eeda40-db74-4e56-9015-a4bb55e25bc7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4017085664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.4017085664
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3989127923
Short name T829
Test name
Test status
Simulation time 32541357 ps
CPU time 1.44 seconds
Started Jul 25 05:11:47 PM PDT 24
Finished Jul 25 05:11:48 PM PDT 24
Peak memory 237484 kb
Host smart-f0d1c634-e614-4862-af8f-bd87fcbef372
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3989127923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3989127923
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3300508587
Short name T807
Test name
Test status
Simulation time 11597642 ps
CPU time 1.38 seconds
Started Jul 25 05:11:45 PM PDT 24
Finished Jul 25 05:11:47 PM PDT 24
Peak memory 236616 kb
Host smart-4ee23004-8add-4909-b877-1a32ccbbe2c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3300508587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3300508587
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.1777751223
Short name T737
Test name
Test status
Simulation time 63499062 ps
CPU time 1.46 seconds
Started Jul 25 05:11:47 PM PDT 24
Finished Jul 25 05:11:48 PM PDT 24
Peak memory 237504 kb
Host smart-91f863d3-1411-455b-9301-813f3bdaaf7c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1777751223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.1777751223
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2679895627
Short name T764
Test name
Test status
Simulation time 47797294 ps
CPU time 1.46 seconds
Started Jul 25 05:11:48 PM PDT 24
Finished Jul 25 05:11:50 PM PDT 24
Peak memory 237304 kb
Host smart-70da38a4-c4f5-40db-a2e9-0e108da15534
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2679895627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.2679895627
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.1302494467
Short name T828
Test name
Test status
Simulation time 11307715 ps
CPU time 1.61 seconds
Started Jul 25 05:11:47 PM PDT 24
Finished Jul 25 05:11:49 PM PDT 24
Peak memory 237488 kb
Host smart-fa804969-2b5b-4fd0-b4a5-5691ebe4eda0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1302494467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.1302494467
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.2557037789
Short name T349
Test name
Test status
Simulation time 16541608 ps
CPU time 1.35 seconds
Started Jul 25 05:11:47 PM PDT 24
Finished Jul 25 05:11:48 PM PDT 24
Peak memory 235488 kb
Host smart-46408302-6038-4af7-9686-84119b23c76f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2557037789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.2557037789
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2801228038
Short name T722
Test name
Test status
Simulation time 17551770387 ps
CPU time 166.08 seconds
Started Jul 25 05:11:07 PM PDT 24
Finished Jul 25 05:13:53 PM PDT 24
Peak memory 240512 kb
Host smart-b825519e-8a94-40ba-9174-b6654459f4a4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2801228038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2801228038
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3846761348
Short name T821
Test name
Test status
Simulation time 821505098 ps
CPU time 92.54 seconds
Started Jul 25 05:11:21 PM PDT 24
Finished Jul 25 05:12:54 PM PDT 24
Peak memory 240372 kb
Host smart-3e5957a2-e317-433b-b9d1-970dfc284b75
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3846761348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3846761348
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3091788176
Short name T771
Test name
Test status
Simulation time 491418371 ps
CPU time 5.77 seconds
Started Jul 25 05:11:08 PM PDT 24
Finished Jul 25 05:11:14 PM PDT 24
Peak memory 240420 kb
Host smart-8b6829e0-9c2b-4c2c-b563-5c7ac87cb7c7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3091788176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3091788176
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.146453444
Short name T360
Test name
Test status
Simulation time 280099702 ps
CPU time 8.92 seconds
Started Jul 25 05:11:07 PM PDT 24
Finished Jul 25 05:11:16 PM PDT 24
Peak memory 253300 kb
Host smart-626dcfc8-81d3-4df4-b175-a6976a7797c6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146453444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.alert_handler_csr_mem_rw_with_rand_reset.146453444
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.164932161
Short name T801
Test name
Test status
Simulation time 110102832 ps
CPU time 8.02 seconds
Started Jul 25 05:11:09 PM PDT 24
Finished Jul 25 05:11:17 PM PDT 24
Peak memory 240408 kb
Host smart-e8c0f842-d6f5-4740-83aa-904a64193fe0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=164932161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.164932161
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1606207365
Short name T728
Test name
Test status
Simulation time 27351156 ps
CPU time 1.29 seconds
Started Jul 25 05:11:22 PM PDT 24
Finished Jul 25 05:11:23 PM PDT 24
Peak memory 236340 kb
Host smart-f570f829-e951-45d1-a2c7-eef89bed0374
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1606207365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1606207365
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.738961675
Short name T788
Test name
Test status
Simulation time 2136377817 ps
CPU time 40.72 seconds
Started Jul 25 05:11:09 PM PDT 24
Finished Jul 25 05:11:50 PM PDT 24
Peak memory 245692 kb
Host smart-15a5707c-69c1-459f-8606-719f5042c8b8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=738961675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outs
tanding.738961675
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2891835184
Short name T143
Test name
Test status
Simulation time 2571566297 ps
CPU time 276.12 seconds
Started Jul 25 05:11:07 PM PDT 24
Finished Jul 25 05:15:44 PM PDT 24
Peak memory 265512 kb
Host smart-81235b4c-87fc-4dd4-9115-a23476c1ecef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2891835184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.2891835184
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.3263997416
Short name T364
Test name
Test status
Simulation time 249051585087 ps
CPU time 1105.5 seconds
Started Jul 25 05:10:57 PM PDT 24
Finished Jul 25 05:29:23 PM PDT 24
Peak memory 265396 kb
Host smart-85f4d26c-e502-466a-a7ad-2809bcb7601b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263997416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.3263997416
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1719867166
Short name T721
Test name
Test status
Simulation time 138836496 ps
CPU time 5.25 seconds
Started Jul 25 05:11:07 PM PDT 24
Finished Jul 25 05:11:13 PM PDT 24
Peak memory 248148 kb
Host smart-9b38e678-8600-4fd6-a1e5-1235566bd2bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1719867166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1719867166
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.1142578135
Short name T760
Test name
Test status
Simulation time 9881263 ps
CPU time 1.38 seconds
Started Jul 25 05:11:45 PM PDT 24
Finished Jul 25 05:11:47 PM PDT 24
Peak memory 237432 kb
Host smart-941815f8-ec95-4170-9f87-acd4b3847a21
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1142578135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.1142578135
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.280212927
Short name T779
Test name
Test status
Simulation time 15728120 ps
CPU time 1.27 seconds
Started Jul 25 05:11:47 PM PDT 24
Finished Jul 25 05:11:48 PM PDT 24
Peak memory 237488 kb
Host smart-c755f239-932f-4532-bf1f-839b093db44a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=280212927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.280212927
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2035221867
Short name T230
Test name
Test status
Simulation time 13862433 ps
CPU time 1.62 seconds
Started Jul 25 05:11:46 PM PDT 24
Finished Jul 25 05:11:48 PM PDT 24
Peak memory 237512 kb
Host smart-70e60693-e82f-4ae6-b7ae-efa262ce8900
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2035221867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2035221867
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.4162436408
Short name T780
Test name
Test status
Simulation time 14094211 ps
CPU time 1.26 seconds
Started Jul 25 05:11:48 PM PDT 24
Finished Jul 25 05:11:49 PM PDT 24
Peak memory 236500 kb
Host smart-7a54a799-4672-401f-a6af-994bd73415d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4162436408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.4162436408
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.662487479
Short name T777
Test name
Test status
Simulation time 6616993 ps
CPU time 1.43 seconds
Started Jul 25 05:11:48 PM PDT 24
Finished Jul 25 05:11:49 PM PDT 24
Peak memory 236496 kb
Host smart-0aa217ed-f8a1-4942-9b19-bfef71fd312b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=662487479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.662487479
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3902653167
Short name T794
Test name
Test status
Simulation time 10691340 ps
CPU time 1.61 seconds
Started Jul 25 05:11:48 PM PDT 24
Finished Jul 25 05:11:50 PM PDT 24
Peak memory 236588 kb
Host smart-35439557-20b6-4082-bba8-563e86ef0837
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3902653167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3902653167
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2289773495
Short name T354
Test name
Test status
Simulation time 18484651 ps
CPU time 1.37 seconds
Started Jul 25 05:11:49 PM PDT 24
Finished Jul 25 05:11:51 PM PDT 24
Peak memory 235544 kb
Host smart-529d9e67-cdd5-4c68-afdf-fd190a7c4028
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2289773495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2289773495
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.2062674638
Short name T353
Test name
Test status
Simulation time 23143825 ps
CPU time 1.44 seconds
Started Jul 25 05:11:47 PM PDT 24
Finished Jul 25 05:11:49 PM PDT 24
Peak memory 237528 kb
Host smart-36ab8833-1dd6-4d4a-9beb-6c58f0038a3f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2062674638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.2062674638
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1181631712
Short name T723
Test name
Test status
Simulation time 9404016 ps
CPU time 1.38 seconds
Started Jul 25 05:11:48 PM PDT 24
Finished Jul 25 05:11:50 PM PDT 24
Peak memory 237444 kb
Host smart-ac9f0350-9fa5-4064-81b0-fd8b4b2fa2c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1181631712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1181631712
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2592896626
Short name T729
Test name
Test status
Simulation time 25701579 ps
CPU time 1.42 seconds
Started Jul 25 05:11:57 PM PDT 24
Finished Jul 25 05:11:59 PM PDT 24
Peak memory 237480 kb
Host smart-dc38d1cd-9470-491b-a718-d8d09e337f3d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2592896626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2592896626
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.185073427
Short name T732
Test name
Test status
Simulation time 139074924 ps
CPU time 6.18 seconds
Started Jul 25 05:11:22 PM PDT 24
Finished Jul 25 05:11:28 PM PDT 24
Peak memory 240416 kb
Host smart-bcee0f93-f6f1-4af6-950e-8913f85e63fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185073427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.185073427
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.421951875
Short name T769
Test name
Test status
Simulation time 121321153 ps
CPU time 5.68 seconds
Started Jul 25 05:11:10 PM PDT 24
Finished Jul 25 05:11:16 PM PDT 24
Peak memory 236528 kb
Host smart-ab802f54-90a9-47a5-8d6e-ddf3d4260a71
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=421951875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.421951875
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1924409930
Short name T350
Test name
Test status
Simulation time 6715626 ps
CPU time 1.43 seconds
Started Jul 25 05:11:06 PM PDT 24
Finished Jul 25 05:11:08 PM PDT 24
Peak memory 237492 kb
Host smart-50179d81-8e33-4f94-bef2-a9c123028a1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1924409930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1924409930
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.1298472228
Short name T170
Test name
Test status
Simulation time 184939981 ps
CPU time 24.05 seconds
Started Jul 25 05:11:09 PM PDT 24
Finished Jul 25 05:11:33 PM PDT 24
Peak memory 245716 kb
Host smart-efe02108-4902-4c6f-9e3b-24b1af25112c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1298472228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.1298472228
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.478768975
Short name T139
Test name
Test status
Simulation time 23310302124 ps
CPU time 270.54 seconds
Started Jul 25 05:11:07 PM PDT 24
Finished Jul 25 05:15:37 PM PDT 24
Peak memory 265336 kb
Host smart-f86b5920-afc7-41ce-be6a-1b958a942a96
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478768975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.478768975
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3181872351
Short name T786
Test name
Test status
Simulation time 114107860 ps
CPU time 4.59 seconds
Started Jul 25 05:11:08 PM PDT 24
Finished Jul 25 05:11:13 PM PDT 24
Peak memory 248516 kb
Host smart-aa0a3804-a1d6-4628-8633-0789822766f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3181872351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3181872351
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.3068088066
Short name T748
Test name
Test status
Simulation time 54057659 ps
CPU time 5.66 seconds
Started Jul 25 05:11:08 PM PDT 24
Finished Jul 25 05:11:14 PM PDT 24
Peak memory 242156 kb
Host smart-7155525a-a3e4-4450-9293-d7fd78c78a67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068088066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.3068088066
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.1565444667
Short name T187
Test name
Test status
Simulation time 57432830 ps
CPU time 4.54 seconds
Started Jul 25 05:11:07 PM PDT 24
Finished Jul 25 05:11:12 PM PDT 24
Peak memory 236644 kb
Host smart-530f0df0-b35d-4989-aff8-3ee2217339a3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1565444667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.1565444667
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3239887149
Short name T356
Test name
Test status
Simulation time 11802518 ps
CPU time 1.35 seconds
Started Jul 25 05:11:15 PM PDT 24
Finished Jul 25 05:11:16 PM PDT 24
Peak memory 237484 kb
Host smart-91e9c572-0ad5-4dbf-b5e1-7b5473eaac0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3239887149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3239887149
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.3108721420
Short name T754
Test name
Test status
Simulation time 1617597674 ps
CPU time 36.8 seconds
Started Jul 25 05:11:11 PM PDT 24
Finished Jul 25 05:11:47 PM PDT 24
Peak memory 245684 kb
Host smart-301a184a-48d9-4692-bd65-8117e116472b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3108721420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.3108721420
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3855147966
Short name T795
Test name
Test status
Simulation time 77545140 ps
CPU time 8.03 seconds
Started Jul 25 05:11:10 PM PDT 24
Finished Jul 25 05:11:18 PM PDT 24
Peak memory 255324 kb
Host smart-88bf879c-076d-443d-b1bc-ce862c061a1e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3855147966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3855147966
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.1284667020
Short name T783
Test name
Test status
Simulation time 41435280 ps
CPU time 6.51 seconds
Started Jul 25 05:17:10 PM PDT 24
Finished Jul 25 05:17:16 PM PDT 24
Peak memory 253904 kb
Host smart-4c918408-2aaa-4600-90e1-572eae91ffb5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284667020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.1284667020
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2729794389
Short name T741
Test name
Test status
Simulation time 58505394 ps
CPU time 5.5 seconds
Started Jul 25 05:11:07 PM PDT 24
Finished Jul 25 05:11:13 PM PDT 24
Peak memory 237472 kb
Host smart-6922d994-3ceb-480d-adf5-f0c357556b12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2729794389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2729794389
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2514524067
Short name T830
Test name
Test status
Simulation time 20810454 ps
CPU time 2.09 seconds
Started Jul 25 05:11:09 PM PDT 24
Finished Jul 25 05:11:11 PM PDT 24
Peak memory 236540 kb
Host smart-deb87cb5-4e9d-4d81-a335-3ff2cb96f4d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2514524067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2514524067
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3024546641
Short name T734
Test name
Test status
Simulation time 353626233 ps
CPU time 26.74 seconds
Started Jul 25 05:11:07 PM PDT 24
Finished Jul 25 05:11:34 PM PDT 24
Peak memory 240340 kb
Host smart-c6441249-ff14-4c9f-85d0-1ede14ff0517
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3024546641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3024546641
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3881913388
Short name T130
Test name
Test status
Simulation time 2333126515 ps
CPU time 149.45 seconds
Started Jul 25 05:11:11 PM PDT 24
Finished Jul 25 05:13:40 PM PDT 24
Peak memory 265420 kb
Host smart-1a514b0f-e212-4a62-a62d-246b44a9851d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3881913388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3881913388
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2297964753
Short name T715
Test name
Test status
Simulation time 101211521 ps
CPU time 10.83 seconds
Started Jul 25 05:11:06 PM PDT 24
Finished Jul 25 05:11:17 PM PDT 24
Peak memory 254848 kb
Host smart-5d26160d-4110-429f-aead-a302755c2d09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2297964753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2297964753
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3765799858
Short name T825
Test name
Test status
Simulation time 305943197 ps
CPU time 11.84 seconds
Started Jul 25 05:11:15 PM PDT 24
Finished Jul 25 05:11:27 PM PDT 24
Peak memory 251128 kb
Host smart-97c018a0-bdad-4625-9076-e7bb3a1ca5c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765799858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3765799858
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.3275057416
Short name T819
Test name
Test status
Simulation time 46188643 ps
CPU time 4.39 seconds
Started Jul 25 05:11:17 PM PDT 24
Finished Jul 25 05:11:22 PM PDT 24
Peak memory 236528 kb
Host smart-00ede6f9-182f-45b2-93d5-351afc7dd847
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3275057416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.3275057416
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1202245305
Short name T814
Test name
Test status
Simulation time 17529736 ps
CPU time 1.4 seconds
Started Jul 25 05:11:08 PM PDT 24
Finished Jul 25 05:11:10 PM PDT 24
Peak memory 236592 kb
Host smart-04f0e6d6-7a5e-4501-b4a1-1d0de90bdefc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1202245305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1202245305
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.374222437
Short name T188
Test name
Test status
Simulation time 8528789212 ps
CPU time 43.56 seconds
Started Jul 25 05:11:08 PM PDT 24
Finished Jul 25 05:11:52 PM PDT 24
Peak memory 248708 kb
Host smart-dabfd746-e3ab-4ddc-9d87-4379c9c720c6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=374222437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.374222437
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1387172414
Short name T132
Test name
Test status
Simulation time 3930971836 ps
CPU time 313.28 seconds
Started Jul 25 05:11:11 PM PDT 24
Finished Jul 25 05:16:24 PM PDT 24
Peak memory 265432 kb
Host smart-6e981bf1-bfe8-4b31-873c-0803ac0e54ce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1387172414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1387172414
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1575279750
Short name T123
Test name
Test status
Simulation time 7796001972 ps
CPU time 542.51 seconds
Started Jul 25 05:11:14 PM PDT 24
Finished Jul 25 05:20:17 PM PDT 24
Peak memory 264996 kb
Host smart-ec0f09f4-4079-4e16-b11b-82fdb2408e16
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575279750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.1575279750
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.248113051
Short name T717
Test name
Test status
Simulation time 76095740 ps
CPU time 9.5 seconds
Started Jul 25 05:11:07 PM PDT 24
Finished Jul 25 05:11:17 PM PDT 24
Peak memory 255732 kb
Host smart-2605dbd7-9b86-4685-8fc8-9b85b2f57598
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=248113051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.248113051
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.292354988
Short name T767
Test name
Test status
Simulation time 217196368 ps
CPU time 8.65 seconds
Started Jul 25 05:11:17 PM PDT 24
Finished Jul 25 05:11:25 PM PDT 24
Peak memory 255508 kb
Host smart-5e226397-18c3-48ad-8cd5-d852da00542d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292354988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.alert_handler_csr_mem_rw_with_rand_reset.292354988
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.197879064
Short name T793
Test name
Test status
Simulation time 505046346 ps
CPU time 5.2 seconds
Started Jul 25 05:11:16 PM PDT 24
Finished Jul 25 05:11:21 PM PDT 24
Peak memory 240408 kb
Host smart-1ce5987a-cb64-45db-9445-fda2a68059e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=197879064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.197879064
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2373544725
Short name T352
Test name
Test status
Simulation time 6226634 ps
CPU time 1.47 seconds
Started Jul 25 05:11:20 PM PDT 24
Finished Jul 25 05:11:22 PM PDT 24
Peak memory 236632 kb
Host smart-65546c1c-052e-42a3-8ccb-3526772736b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2373544725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2373544725
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.394707476
Short name T755
Test name
Test status
Simulation time 180477528 ps
CPU time 22.82 seconds
Started Jul 25 05:11:16 PM PDT 24
Finished Jul 25 05:11:39 PM PDT 24
Peak memory 244764 kb
Host smart-911529ae-e0ca-449c-84eb-cfac913e1c6d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=394707476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_outs
tanding.394707476
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1110314458
Short name T121
Test name
Test status
Simulation time 14671120647 ps
CPU time 92.85 seconds
Started Jul 25 05:11:17 PM PDT 24
Finished Jul 25 05:12:50 PM PDT 24
Peak memory 257240 kb
Host smart-7299dd5e-767e-473d-a699-82da85bd6ac0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1110314458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1110314458
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2872235591
Short name T142
Test name
Test status
Simulation time 8597094932 ps
CPU time 381.81 seconds
Started Jul 25 05:11:11 PM PDT 24
Finished Jul 25 05:17:33 PM PDT 24
Peak memory 265404 kb
Host smart-ba18e069-607a-4395-8189-eb29bc2ad0ee
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872235591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2872235591
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3202701388
Short name T761
Test name
Test status
Simulation time 308452623 ps
CPU time 20.77 seconds
Started Jul 25 05:11:16 PM PDT 24
Finished Jul 25 05:11:37 PM PDT 24
Peak memory 248356 kb
Host smart-2d017e47-68c9-4358-b2f8-0b5bb822756c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3202701388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3202701388
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3485349697
Short name T52
Test name
Test status
Simulation time 176584642820 ps
CPU time 2357.24 seconds
Started Jul 25 05:21:21 PM PDT 24
Finished Jul 25 06:00:38 PM PDT 24
Peak memory 281568 kb
Host smart-393c8e6a-161f-4c5d-bb67-26d5c7f6ef9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485349697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3485349697
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.1905115826
Short name T448
Test name
Test status
Simulation time 376691136 ps
CPU time 11.18 seconds
Started Jul 25 05:21:21 PM PDT 24
Finished Jul 25 05:21:32 PM PDT 24
Peak memory 248888 kb
Host smart-2256c3b2-529f-4b1e-8336-24493ab31429
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1905115826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.1905115826
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.3614140711
Short name T690
Test name
Test status
Simulation time 1507574039 ps
CPU time 98.66 seconds
Started Jul 25 05:21:21 PM PDT 24
Finished Jul 25 05:22:59 PM PDT 24
Peak memory 256624 kb
Host smart-ffd50728-accb-4c85-a6b8-ddac13110b11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36141
40711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.3614140711
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2330071271
Short name T215
Test name
Test status
Simulation time 1139998934 ps
CPU time 20.87 seconds
Started Jul 25 05:21:19 PM PDT 24
Finished Jul 25 05:21:40 PM PDT 24
Peak memory 248664 kb
Host smart-35d96856-e481-4a3c-adcb-72e427621c80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23300
71271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2330071271
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2229103836
Short name T683
Test name
Test status
Simulation time 31456621901 ps
CPU time 1846.94 seconds
Started Jul 25 05:21:20 PM PDT 24
Finished Jul 25 05:52:08 PM PDT 24
Peak memory 273400 kb
Host smart-8d921954-9c89-4f28-9833-3b4c78725267
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229103836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2229103836
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.1304484051
Short name T399
Test name
Test status
Simulation time 12200102176 ps
CPU time 1274.2 seconds
Started Jul 25 05:21:21 PM PDT 24
Finished Jul 25 05:42:35 PM PDT 24
Peak memory 284416 kb
Host smart-20441166-f46c-4c83-bb73-146802d9b6d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304484051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.1304484051
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.879428970
Short name T216
Test name
Test status
Simulation time 632423635 ps
CPU time 43.67 seconds
Started Jul 25 05:21:21 PM PDT 24
Finished Jul 25 05:22:05 PM PDT 24
Peak memory 248912 kb
Host smart-c4816593-4373-44c4-92ae-cf9b6e92295d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87942
8970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.879428970
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.497924557
Short name T537
Test name
Test status
Simulation time 1783080183 ps
CPU time 46.82 seconds
Started Jul 25 05:21:21 PM PDT 24
Finished Jul 25 05:22:08 PM PDT 24
Peak memory 249752 kb
Host smart-c17444a3-9b3d-48dd-8ad5-1af93ed2ecd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49792
4557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.497924557
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.4277173069
Short name T34
Test name
Test status
Simulation time 434293722 ps
CPU time 24 seconds
Started Jul 25 05:21:28 PM PDT 24
Finished Jul 25 05:21:52 PM PDT 24
Peak memory 271048 kb
Host smart-bff9aa97-b93e-42bb-ab41-8a8b6fa4fb36
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4277173069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.4277173069
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2089612200
Short name T82
Test name
Test status
Simulation time 488653004 ps
CPU time 28.55 seconds
Started Jul 25 05:21:20 PM PDT 24
Finished Jul 25 05:21:48 PM PDT 24
Peak memory 248340 kb
Host smart-4392a84d-6022-416c-b6f1-e41be1e22b4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20896
12200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2089612200
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.348659532
Short name T423
Test name
Test status
Simulation time 872842761 ps
CPU time 21.23 seconds
Started Jul 25 05:21:12 PM PDT 24
Finished Jul 25 05:21:33 PM PDT 24
Peak memory 248856 kb
Host smart-e23f15e7-bf33-4786-95a9-e10fe35ece76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34865
9532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.348659532
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.2868580660
Short name T476
Test name
Test status
Simulation time 187682393 ps
CPU time 10.39 seconds
Started Jul 25 05:21:36 PM PDT 24
Finished Jul 25 05:21:47 PM PDT 24
Peak memory 248772 kb
Host smart-51c90023-5fe0-4391-b6c2-ebb7804666b3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2868580660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.2868580660
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2833725805
Short name T554
Test name
Test status
Simulation time 877622051 ps
CPU time 110.29 seconds
Started Jul 25 05:21:32 PM PDT 24
Finished Jul 25 05:23:22 PM PDT 24
Peak memory 257052 kb
Host smart-0db99511-ac65-4a42-a383-804d46853aee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28337
25805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2833725805
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.2020532274
Short name T628
Test name
Test status
Simulation time 169514811 ps
CPU time 19.17 seconds
Started Jul 25 05:21:29 PM PDT 24
Finished Jul 25 05:21:49 PM PDT 24
Peak memory 248704 kb
Host smart-5a3dc3c2-0cbc-48cc-b320-ba456cec17c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20205
32274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.2020532274
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.3598644025
Short name T445
Test name
Test status
Simulation time 24220149924 ps
CPU time 1703.71 seconds
Started Jul 25 05:21:37 PM PDT 24
Finished Jul 25 05:50:01 PM PDT 24
Peak memory 273320 kb
Host smart-8c409b20-101a-4230-9332-ca0154281d46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598644025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.3598644025
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2749056010
Short name T22
Test name
Test status
Simulation time 1863703646 ps
CPU time 47.5 seconds
Started Jul 25 05:21:29 PM PDT 24
Finished Jul 25 05:22:16 PM PDT 24
Peak memory 256244 kb
Host smart-2e3d5592-aa9b-41b7-8d5c-0c2bc1dda47b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27490
56010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2749056010
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1568040150
Short name T521
Test name
Test status
Simulation time 743416169 ps
CPU time 21.44 seconds
Started Jul 25 05:21:28 PM PDT 24
Finished Jul 25 05:21:50 PM PDT 24
Peak memory 256384 kb
Host smart-b31eb336-2f0d-425f-865f-00cda5a3b500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15680
40150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1568040150
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.3067851070
Short name T33
Test name
Test status
Simulation time 852777423 ps
CPU time 26.82 seconds
Started Jul 25 05:21:35 PM PDT 24
Finished Jul 25 05:22:02 PM PDT 24
Peak memory 270076 kb
Host smart-c938a38a-1a83-493e-8fcb-db0cc7e1ac70
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3067851070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3067851070
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.102841371
Short name T239
Test name
Test status
Simulation time 42874894446 ps
CPU time 2553.48 seconds
Started Jul 25 05:21:36 PM PDT 24
Finished Jul 25 06:04:10 PM PDT 24
Peak memory 281732 kb
Host smart-411c0842-d1ca-4bcd-85fa-400c40280f99
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102841371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.102841371
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1797734601
Short name T503
Test name
Test status
Simulation time 143978431576 ps
CPU time 2551.39 seconds
Started Jul 25 05:23:42 PM PDT 24
Finished Jul 25 06:06:14 PM PDT 24
Peak memory 287232 kb
Host smart-688a67b7-5b4f-4e93-b718-f121c669ccc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797734601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1797734601
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2130725468
Short name T4
Test name
Test status
Simulation time 181101065 ps
CPU time 11.44 seconds
Started Jul 25 05:23:42 PM PDT 24
Finished Jul 25 05:23:54 PM PDT 24
Peak memory 248864 kb
Host smart-7f1d71cf-537f-49ed-af4c-3fe26c6207c7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2130725468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2130725468
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.711943372
Short name T271
Test name
Test status
Simulation time 774572895 ps
CPU time 18.16 seconds
Started Jul 25 05:23:34 PM PDT 24
Finished Jul 25 05:23:53 PM PDT 24
Peak memory 256232 kb
Host smart-4b81b0b8-7a88-4ad1-9b2a-f2a317eb65e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71194
3372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.711943372
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3240005863
Short name T35
Test name
Test status
Simulation time 494520737 ps
CPU time 28.7 seconds
Started Jul 25 05:23:35 PM PDT 24
Finished Jul 25 05:24:04 PM PDT 24
Peak memory 256064 kb
Host smart-63772c7d-1fbb-4941-98ff-e7bc99dc7eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32400
05863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3240005863
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.985792147
Short name T326
Test name
Test status
Simulation time 36105952667 ps
CPU time 860.95 seconds
Started Jul 25 05:23:43 PM PDT 24
Finished Jul 25 05:38:04 PM PDT 24
Peak memory 272684 kb
Host smart-683fa291-eefe-4095-a23a-59ea2d980750
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985792147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.985792147
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1672405873
Short name T619
Test name
Test status
Simulation time 14236424654 ps
CPU time 1435.73 seconds
Started Jul 25 05:23:44 PM PDT 24
Finished Jul 25 05:47:40 PM PDT 24
Peak memory 289044 kb
Host smart-2c93542c-b65d-4f79-8d6f-8ac51c74f9f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672405873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1672405873
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2505678065
Short name T267
Test name
Test status
Simulation time 454051799 ps
CPU time 31.84 seconds
Started Jul 25 05:23:34 PM PDT 24
Finished Jul 25 05:24:06 PM PDT 24
Peak memory 255504 kb
Host smart-a3abee7e-79c5-4269-98a2-3db7349b4168
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25056
78065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2505678065
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.4254707394
Short name T102
Test name
Test status
Simulation time 3294022634 ps
CPU time 42.25 seconds
Started Jul 25 05:23:34 PM PDT 24
Finished Jul 25 05:24:16 PM PDT 24
Peak memory 257076 kb
Host smart-85f4e936-6f77-4e70-9a30-c5a05e51d4aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42547
07394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.4254707394
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.3213819227
Short name T612
Test name
Test status
Simulation time 302304109 ps
CPU time 9.92 seconds
Started Jul 25 05:23:42 PM PDT 24
Finished Jul 25 05:23:52 PM PDT 24
Peak memory 248276 kb
Host smart-a053f3dc-e564-4710-ae68-34fc85c84647
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32138
19227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3213819227
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.470762742
Short name T518
Test name
Test status
Simulation time 2151636809 ps
CPU time 41.16 seconds
Started Jul 25 05:23:35 PM PDT 24
Finished Jul 25 05:24:16 PM PDT 24
Peak memory 256492 kb
Host smart-783c7fed-d133-4201-8181-6dc03416d065
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47076
2742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.470762742
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1452500421
Short name T708
Test name
Test status
Simulation time 10243118933 ps
CPU time 532.27 seconds
Started Jul 25 05:23:56 PM PDT 24
Finished Jul 25 05:32:49 PM PDT 24
Peak memory 257084 kb
Host smart-a3c4159d-6a96-4f73-88c8-63c9c1c08e57
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452500421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1452500421
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2333357535
Short name T207
Test name
Test status
Simulation time 107636174 ps
CPU time 2.91 seconds
Started Jul 25 05:24:05 PM PDT 24
Finished Jul 25 05:24:08 PM PDT 24
Peak memory 249192 kb
Host smart-3d3730ea-00f9-4145-965e-a02589efb387
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2333357535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2333357535
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.1234751832
Short name T551
Test name
Test status
Simulation time 97816721469 ps
CPU time 1942.81 seconds
Started Jul 25 05:24:06 PM PDT 24
Finished Jul 25 05:56:29 PM PDT 24
Peak memory 284884 kb
Host smart-dca0ea6f-4c4d-43ce-8af6-1cf185ec72da
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234751832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.1234751832
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.26811637
Short name T371
Test name
Test status
Simulation time 2854735112 ps
CPU time 15.5 seconds
Started Jul 25 05:24:04 PM PDT 24
Finished Jul 25 05:24:20 PM PDT 24
Peak memory 248840 kb
Host smart-13ea97f1-9c53-4179-bfe4-6ed12612bc9a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=26811637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.26811637
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.2588724905
Short name T608
Test name
Test status
Simulation time 7809051801 ps
CPU time 201.9 seconds
Started Jul 25 05:23:57 PM PDT 24
Finished Jul 25 05:27:19 PM PDT 24
Peak memory 252016 kb
Host smart-5420cb84-4c89-41a8-a986-a380ae90ca88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25887
24905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2588724905
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1499590279
Short name T380
Test name
Test status
Simulation time 351756687 ps
CPU time 33.39 seconds
Started Jul 25 05:23:54 PM PDT 24
Finished Jul 25 05:24:28 PM PDT 24
Peak memory 248900 kb
Host smart-47235939-3cc7-4f6d-93e1-09f68346e076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14995
90279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1499590279
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.640985194
Short name T547
Test name
Test status
Simulation time 38920287618 ps
CPU time 2596.66 seconds
Started Jul 25 05:24:04 PM PDT 24
Finished Jul 25 06:07:21 PM PDT 24
Peak memory 281632 kb
Host smart-668f7f87-e5ed-422c-86f8-e482a26941c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640985194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.640985194
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.2106901644
Short name T697
Test name
Test status
Simulation time 1603233178 ps
CPU time 15.67 seconds
Started Jul 25 05:23:55 PM PDT 24
Finished Jul 25 05:24:10 PM PDT 24
Peak memory 256300 kb
Host smart-1666754b-0d8c-432b-9d44-172e23fba829
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21069
01644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.2106901644
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3022902763
Short name T473
Test name
Test status
Simulation time 146859364 ps
CPU time 8.05 seconds
Started Jul 25 05:23:54 PM PDT 24
Finished Jul 25 05:24:02 PM PDT 24
Peak memory 248408 kb
Host smart-8425ffef-dfa1-4e24-9e21-90109786c251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30229
02763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3022902763
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1333521032
Short name T401
Test name
Test status
Simulation time 657529753 ps
CPU time 16.22 seconds
Started Jul 25 05:24:04 PM PDT 24
Finished Jul 25 05:24:20 PM PDT 24
Peak memory 249412 kb
Host smart-3bed19f6-f8f8-4d44-b26f-ed6e622c62e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13335
21032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1333521032
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.4153552559
Short name T577
Test name
Test status
Simulation time 3255839602 ps
CPU time 54.97 seconds
Started Jul 25 05:23:57 PM PDT 24
Finished Jul 25 05:24:52 PM PDT 24
Peak memory 256292 kb
Host smart-9196ea48-7537-4b08-b436-00b92b2b67c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41535
52559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.4153552559
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1992879817
Short name T47
Test name
Test status
Simulation time 14985921587 ps
CPU time 1646.09 seconds
Started Jul 25 05:24:05 PM PDT 24
Finished Jul 25 05:51:31 PM PDT 24
Peak memory 289340 kb
Host smart-f7a69aa2-393f-4e44-b8ea-3c66407f92b5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992879817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1992879817
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.2398296510
Short name T51
Test name
Test status
Simulation time 7903802067 ps
CPU time 855.17 seconds
Started Jul 25 05:24:14 PM PDT 24
Finished Jul 25 05:38:29 PM PDT 24
Peak memory 273288 kb
Host smart-50215e97-e6b1-407a-a08f-6a051bdf1233
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398296510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.2398296510
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3812323550
Short name T385
Test name
Test status
Simulation time 1464752124 ps
CPU time 12.77 seconds
Started Jul 25 05:24:13 PM PDT 24
Finished Jul 25 05:24:26 PM PDT 24
Peak memory 248848 kb
Host smart-c5556b1d-8b38-467e-a29b-720c6472efff
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3812323550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3812323550
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2374645622
Short name T493
Test name
Test status
Simulation time 1708463432 ps
CPU time 25.3 seconds
Started Jul 25 05:24:06 PM PDT 24
Finished Jul 25 05:24:31 PM PDT 24
Peak memory 256528 kb
Host smart-cae29b8e-fa0a-46ca-bdc8-e3bbb2fc7aa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23746
45622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2374645622
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2231440299
Short name T412
Test name
Test status
Simulation time 1569050960 ps
CPU time 29.08 seconds
Started Jul 25 05:24:07 PM PDT 24
Finished Jul 25 05:24:36 PM PDT 24
Peak memory 257060 kb
Host smart-d0ea932e-036f-439c-92bf-82044de81143
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22314
40299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2231440299
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.4277801739
Short name T654
Test name
Test status
Simulation time 42031225202 ps
CPU time 1658.03 seconds
Started Jul 25 05:24:14 PM PDT 24
Finished Jul 25 05:51:53 PM PDT 24
Peak memory 269352 kb
Host smart-609741c0-dccd-4eae-be5a-be3ea2156687
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277801739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.4277801739
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2603934270
Short name T650
Test name
Test status
Simulation time 64551434121 ps
CPU time 3467.61 seconds
Started Jul 25 05:24:14 PM PDT 24
Finished Jul 25 06:22:02 PM PDT 24
Peak memory 289856 kb
Host smart-9d0f03c7-5c8d-4572-91ee-8826c3c873e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2603934270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2603934270
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2397700757
Short name T299
Test name
Test status
Simulation time 6428774855 ps
CPU time 243.81 seconds
Started Jul 25 05:24:18 PM PDT 24
Finished Jul 25 05:28:22 PM PDT 24
Peak memory 248668 kb
Host smart-91f94258-3756-4e3f-90f7-7cde607bb277
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397700757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2397700757
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.1522559558
Short name T490
Test name
Test status
Simulation time 4019940286 ps
CPU time 57.8 seconds
Started Jul 25 05:24:06 PM PDT 24
Finished Jul 25 05:25:04 PM PDT 24
Peak memory 248880 kb
Host smart-ac7e6781-5dff-458e-974a-0a2c27b4e4b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15225
59558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.1522559558
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.2315087884
Short name T458
Test name
Test status
Simulation time 2392365939 ps
CPU time 71.24 seconds
Started Jul 25 05:24:07 PM PDT 24
Finished Jul 25 05:25:18 PM PDT 24
Peak memory 257136 kb
Host smart-2de93d72-63e7-425d-929a-9ec48b67c10c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23150
87884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2315087884
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1761675946
Short name T222
Test name
Test status
Simulation time 348372911 ps
CPU time 7.11 seconds
Started Jul 25 05:24:07 PM PDT 24
Finished Jul 25 05:24:14 PM PDT 24
Peak memory 248876 kb
Host smart-fe603d8b-01a7-48e1-a72e-bb5cee5701fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17616
75946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1761675946
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3742152755
Short name T662
Test name
Test status
Simulation time 505159748 ps
CPU time 36.08 seconds
Started Jul 25 05:24:05 PM PDT 24
Finished Jul 25 05:24:41 PM PDT 24
Peak memory 248824 kb
Host smart-9f5c75f5-bf40-4561-99de-778f07726ac5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37421
52755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3742152755
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.2316155370
Short name T254
Test name
Test status
Simulation time 14155722343 ps
CPU time 705.16 seconds
Started Jul 25 05:24:12 PM PDT 24
Finished Jul 25 05:35:58 PM PDT 24
Peak memory 267680 kb
Host smart-ed5b6faf-52f4-4937-a675-d4d532e5db32
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316155370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.2316155370
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.4147159631
Short name T1
Test name
Test status
Simulation time 309047836 ps
CPU time 3.73 seconds
Started Jul 25 05:24:28 PM PDT 24
Finished Jul 25 05:24:32 PM PDT 24
Peak memory 248980 kb
Host smart-1f831dd4-9b86-4430-9aa4-b7b1c6bd4a5b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4147159631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.4147159631
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.400978375
Short name T669
Test name
Test status
Simulation time 7472009365 ps
CPU time 832.94 seconds
Started Jul 25 05:24:26 PM PDT 24
Finished Jul 25 05:38:19 PM PDT 24
Peak memory 273508 kb
Host smart-c2ebf70a-056d-449e-87e9-7e51f3349b0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400978375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.400978375
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1757632653
Short name T214
Test name
Test status
Simulation time 1085163898 ps
CPU time 24.69 seconds
Started Jul 25 05:24:32 PM PDT 24
Finished Jul 25 05:24:57 PM PDT 24
Peak memory 248880 kb
Host smart-f7b5f0d4-1593-46d8-9769-51a3f17a0748
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1757632653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1757632653
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.4265607786
Short name T73
Test name
Test status
Simulation time 432249567 ps
CPU time 32.81 seconds
Started Jul 25 05:24:21 PM PDT 24
Finished Jul 25 05:24:54 PM PDT 24
Peak memory 256392 kb
Host smart-dd43fd22-39a9-46fa-a92d-811b4f0016ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42656
07786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.4265607786
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.600290167
Short name T485
Test name
Test status
Simulation time 913534243 ps
CPU time 25.47 seconds
Started Jul 25 05:24:23 PM PDT 24
Finished Jul 25 05:24:49 PM PDT 24
Peak memory 255876 kb
Host smart-b6b561b0-dad8-4096-b3f8-7acaf8a5ca89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60029
0167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.600290167
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2087279317
Short name T263
Test name
Test status
Simulation time 795854754274 ps
CPU time 2757.83 seconds
Started Jul 25 05:24:28 PM PDT 24
Finished Jul 25 06:10:26 PM PDT 24
Peak memory 289696 kb
Host smart-95db61e2-670b-4be4-9c7a-ee66f3a5c72b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087279317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2087279317
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1703624532
Short name T599
Test name
Test status
Simulation time 13677064070 ps
CPU time 272.18 seconds
Started Jul 25 05:24:22 PM PDT 24
Finished Jul 25 05:28:54 PM PDT 24
Peak memory 248872 kb
Host smart-1b71e67b-e03c-4ff6-80f6-93f2f8a2f4bb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703624532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1703624532
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3751623051
Short name T701
Test name
Test status
Simulation time 1077803114 ps
CPU time 67.02 seconds
Started Jul 25 05:24:22 PM PDT 24
Finished Jul 25 05:25:29 PM PDT 24
Peak memory 256300 kb
Host smart-c219cf6d-67a0-4725-806a-985d9e03e1c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37516
23051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3751623051
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.34169563
Short name T85
Test name
Test status
Simulation time 2803094952 ps
CPU time 52.47 seconds
Started Jul 25 05:24:24 PM PDT 24
Finished Jul 25 05:25:16 PM PDT 24
Peak memory 256652 kb
Host smart-4485d814-ca4b-4741-a3fc-2931a7b3ac1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34169
563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.34169563
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3661762842
Short name T420
Test name
Test status
Simulation time 255417706 ps
CPU time 27.9 seconds
Started Jul 25 05:24:22 PM PDT 24
Finished Jul 25 05:24:50 PM PDT 24
Peak memory 256480 kb
Host smart-ff2bae66-6ee4-47db-9481-f0e2ae390cd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36617
62842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3661762842
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3407678439
Short name T555
Test name
Test status
Simulation time 117551977 ps
CPU time 4.8 seconds
Started Jul 25 05:24:24 PM PDT 24
Finished Jul 25 05:24:29 PM PDT 24
Peak memory 251088 kb
Host smart-5f9c22ba-9e97-42d6-b613-90904f102b26
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34076
78439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3407678439
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2316599689
Short name T546
Test name
Test status
Simulation time 135726611747 ps
CPU time 2381.92 seconds
Started Jul 25 05:24:28 PM PDT 24
Finished Jul 25 06:04:10 PM PDT 24
Peak memory 289632 kb
Host smart-ae87642a-8e38-40c3-a055-d33bf0d657b8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316599689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2316599689
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3064754380
Short name T220
Test name
Test status
Simulation time 75761695456 ps
CPU time 4006.08 seconds
Started Jul 25 05:24:33 PM PDT 24
Finished Jul 25 06:31:19 PM PDT 24
Peak memory 305592 kb
Host smart-d5c794b8-5d6c-42a6-bec2-dbeaa1133ab5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3064754380 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3064754380
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2447949792
Short name T200
Test name
Test status
Simulation time 48526605 ps
CPU time 3.57 seconds
Started Jul 25 05:24:48 PM PDT 24
Finished Jul 25 05:24:52 PM PDT 24
Peak memory 249164 kb
Host smart-25f1cd3c-1d53-4d85-a867-f54fe3c12638
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2447949792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2447949792
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.1538168954
Short name T400
Test name
Test status
Simulation time 22753760470 ps
CPU time 1523.13 seconds
Started Jul 25 05:24:40 PM PDT 24
Finished Jul 25 05:50:03 PM PDT 24
Peak memory 273460 kb
Host smart-94b7a635-45a2-4926-b1df-4dbcad1e357c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538168954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1538168954
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2093556279
Short name T438
Test name
Test status
Simulation time 1113071692 ps
CPU time 28.01 seconds
Started Jul 25 05:24:50 PM PDT 24
Finished Jul 25 05:25:18 PM PDT 24
Peak memory 248804 kb
Host smart-3508a20e-7be1-4632-8660-7aa03a870082
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2093556279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2093556279
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.1514683205
Short name T635
Test name
Test status
Simulation time 4218028442 ps
CPU time 246.31 seconds
Started Jul 25 05:24:38 PM PDT 24
Finished Jul 25 05:28:45 PM PDT 24
Peak memory 257196 kb
Host smart-1ea4568d-dc4a-400b-b1cc-9d2f5d49bbd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15146
83205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1514683205
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3786397394
Short name T110
Test name
Test status
Simulation time 2299895471 ps
CPU time 25.43 seconds
Started Jul 25 05:24:37 PM PDT 24
Finished Jul 25 05:25:03 PM PDT 24
Peak memory 248512 kb
Host smart-d5e205b6-ebce-4030-a14d-348fa8f53bf1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37863
97394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3786397394
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3559235584
Short name T309
Test name
Test status
Simulation time 7770085329 ps
CPU time 348.63 seconds
Started Jul 25 05:24:38 PM PDT 24
Finished Jul 25 05:30:27 PM PDT 24
Peak memory 248920 kb
Host smart-f7fc147e-94a8-4e81-9935-f8dfaf000d0e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559235584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3559235584
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2747577255
Short name T106
Test name
Test status
Simulation time 83239155 ps
CPU time 6.29 seconds
Started Jul 25 05:24:32 PM PDT 24
Finished Jul 25 05:24:39 PM PDT 24
Peak memory 248852 kb
Host smart-a7ca7da7-4bae-44f5-bba7-f2d3aaea8fb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27475
77255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2747577255
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2791232713
Short name T477
Test name
Test status
Simulation time 685798554 ps
CPU time 9 seconds
Started Jul 25 05:24:41 PM PDT 24
Finished Jul 25 05:24:50 PM PDT 24
Peak memory 251600 kb
Host smart-8f437cf1-a1f4-4510-ba95-8c595d146975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27912
32713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2791232713
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.196785897
Short name T459
Test name
Test status
Simulation time 374318733 ps
CPU time 22.04 seconds
Started Jul 25 05:24:37 PM PDT 24
Finished Jul 25 05:24:59 PM PDT 24
Peak memory 248828 kb
Host smart-efc6d318-ff82-4964-9c3e-e830f5987082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19678
5897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.196785897
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3406274150
Short name T415
Test name
Test status
Simulation time 511202404 ps
CPU time 9.93 seconds
Started Jul 25 05:24:33 PM PDT 24
Finished Jul 25 05:24:43 PM PDT 24
Peak memory 255140 kb
Host smart-dc951a3e-bdf3-426a-96a4-559b2fd36080
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34062
74150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3406274150
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3273395595
Short name T692
Test name
Test status
Simulation time 66720921519 ps
CPU time 1819.79 seconds
Started Jul 25 05:24:48 PM PDT 24
Finished Jul 25 05:55:08 PM PDT 24
Peak memory 289208 kb
Host smart-9e8d14fb-aa3a-416b-ba9b-164cba5215b8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273395595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3273395595
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3977031744
Short name T199
Test name
Test status
Simulation time 15772820 ps
CPU time 2.28 seconds
Started Jul 25 05:25:05 PM PDT 24
Finished Jul 25 05:25:07 PM PDT 24
Peak memory 249052 kb
Host smart-00d5c8f2-7dee-402d-9a17-d75bc7c14181
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3977031744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3977031744
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.1267097064
Short name T446
Test name
Test status
Simulation time 40431956633 ps
CPU time 2274.55 seconds
Started Jul 25 05:24:56 PM PDT 24
Finished Jul 25 06:02:51 PM PDT 24
Peak memory 281656 kb
Host smart-b2171388-d7f1-400b-83d8-21b235dacd13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1267097064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.1267097064
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1336718988
Short name T684
Test name
Test status
Simulation time 6457943063 ps
CPU time 100.37 seconds
Started Jul 25 05:24:58 PM PDT 24
Finished Jul 25 05:26:38 PM PDT 24
Peak memory 256736 kb
Host smart-1f3a9074-34a0-46cd-aef2-6a4192fdeb4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13367
18988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1336718988
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1844331356
Short name T677
Test name
Test status
Simulation time 66556251 ps
CPU time 7.72 seconds
Started Jul 25 05:24:56 PM PDT 24
Finished Jul 25 05:25:04 PM PDT 24
Peak memory 248808 kb
Host smart-035f6f2e-32fb-4eb2-99c2-3e5c0b69c9d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18443
31356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1844331356
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2787094102
Short name T342
Test name
Test status
Simulation time 264107968081 ps
CPU time 1959.45 seconds
Started Jul 25 05:24:56 PM PDT 24
Finished Jul 25 05:57:36 PM PDT 24
Peak memory 281652 kb
Host smart-7da4a6d6-89b3-4f9d-8206-310a15f0f4fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787094102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2787094102
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.896752762
Short name T431
Test name
Test status
Simulation time 137861783570 ps
CPU time 1938.74 seconds
Started Jul 25 05:24:57 PM PDT 24
Finished Jul 25 05:57:16 PM PDT 24
Peak memory 273380 kb
Host smart-490961ec-9a54-4d82-9f94-55c21e723c81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896752762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.896752762
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.2928050880
Short name T465
Test name
Test status
Simulation time 9820645545 ps
CPU time 45.92 seconds
Started Jul 25 05:24:49 PM PDT 24
Finished Jul 25 05:25:36 PM PDT 24
Peak memory 256900 kb
Host smart-5f38592b-d99d-42f7-8743-bcebd1061c8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29280
50880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.2928050880
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.770302552
Short name T624
Test name
Test status
Simulation time 2098731577 ps
CPU time 22.5 seconds
Started Jul 25 05:24:56 PM PDT 24
Finished Jul 25 05:25:18 PM PDT 24
Peak memory 248260 kb
Host smart-1d3eaf53-9b36-437b-8cb9-ffd844e251ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77030
2552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.770302552
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1421940631
Short name T583
Test name
Test status
Simulation time 182678991 ps
CPU time 12.93 seconds
Started Jul 25 05:24:57 PM PDT 24
Finished Jul 25 05:25:10 PM PDT 24
Peak memory 248396 kb
Host smart-b28acbd7-90c3-451d-a3cb-615f20bcd4cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14219
40631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1421940631
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2977658115
Short name T591
Test name
Test status
Simulation time 767730536 ps
CPU time 45.66 seconds
Started Jul 25 05:24:50 PM PDT 24
Finished Jul 25 05:25:36 PM PDT 24
Peak memory 257040 kb
Host smart-fd30e23a-1de9-4460-88f3-5b04fbcc57f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29776
58115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2977658115
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.2534694102
Short name T589
Test name
Test status
Simulation time 7812680727 ps
CPU time 224.85 seconds
Started Jul 25 05:24:58 PM PDT 24
Finished Jul 25 05:28:43 PM PDT 24
Peak memory 257076 kb
Host smart-11135c04-d7aa-4ef1-aef1-00f03f8c6b65
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534694102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.2534694102
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.499821284
Short name T91
Test name
Test status
Simulation time 160821260679 ps
CPU time 1107.36 seconds
Started Jul 25 05:25:04 PM PDT 24
Finished Jul 25 05:43:31 PM PDT 24
Peak memory 281740 kb
Host smart-3c2f1b0c-2d5c-4c2d-8ebe-fa11949728f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499821284 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.499821284
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.4132899721
Short name T203
Test name
Test status
Simulation time 38539612 ps
CPU time 3.45 seconds
Started Jul 25 05:25:24 PM PDT 24
Finished Jul 25 05:25:28 PM PDT 24
Peak memory 249192 kb
Host smart-10221e15-5bda-49e7-a276-ea9771b16dc2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4132899721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.4132899721
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1072276119
Short name T582
Test name
Test status
Simulation time 55552635230 ps
CPU time 2720.85 seconds
Started Jul 25 05:25:15 PM PDT 24
Finished Jul 25 06:10:36 PM PDT 24
Peak memory 288916 kb
Host smart-257721a6-6e39-46d7-b376-475ddfecee67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072276119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1072276119
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.2932702495
Short name T447
Test name
Test status
Simulation time 411216807 ps
CPU time 11.17 seconds
Started Jul 25 05:25:24 PM PDT 24
Finished Jul 25 05:25:36 PM PDT 24
Peak memory 248864 kb
Host smart-363ce477-7aec-4c69-9099-a602a84fd39b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2932702495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.2932702495
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.4067220737
Short name T671
Test name
Test status
Simulation time 16723949061 ps
CPU time 286.55 seconds
Started Jul 25 05:25:05 PM PDT 24
Finished Jul 25 05:29:52 PM PDT 24
Peak memory 256380 kb
Host smart-50fa4f8e-3121-4171-9ab0-568f257939e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40672
20737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.4067220737
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.1693171365
Short name T60
Test name
Test status
Simulation time 313992190 ps
CPU time 22.34 seconds
Started Jul 25 05:25:06 PM PDT 24
Finished Jul 25 05:25:29 PM PDT 24
Peak memory 248472 kb
Host smart-a4178618-5308-4b27-9e71-7863b4b6bb83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16931
71365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1693171365
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.106049590
Short name T641
Test name
Test status
Simulation time 63900965374 ps
CPU time 2382.85 seconds
Started Jul 25 05:25:25 PM PDT 24
Finished Jul 25 06:05:09 PM PDT 24
Peak memory 289752 kb
Host smart-e4e19117-8f8f-4acf-b2d7-832fdb3a848a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106049590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.106049590
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1785271225
Short name T575
Test name
Test status
Simulation time 6683095334 ps
CPU time 29.62 seconds
Started Jul 25 05:25:05 PM PDT 24
Finished Jul 25 05:25:35 PM PDT 24
Peak memory 255872 kb
Host smart-f5b7ad2d-7b0e-41a2-908c-95e964ff73bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17852
71225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1785271225
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.2319781836
Short name T424
Test name
Test status
Simulation time 1875816164 ps
CPU time 31.35 seconds
Started Jul 25 05:25:07 PM PDT 24
Finished Jul 25 05:25:38 PM PDT 24
Peak memory 248444 kb
Host smart-cd241fb3-914b-4a61-bda8-a3f98116667a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23197
81836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2319781836
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.2533521900
Short name T104
Test name
Test status
Simulation time 1572784237 ps
CPU time 54.89 seconds
Started Jul 25 05:25:15 PM PDT 24
Finished Jul 25 05:26:10 PM PDT 24
Peak memory 257112 kb
Host smart-efe74449-2c8b-4e2f-bf45-6f778a54c50b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25335
21900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.2533521900
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.3739636456
Short name T278
Test name
Test status
Simulation time 434101088 ps
CPU time 21.06 seconds
Started Jul 25 05:25:07 PM PDT 24
Finished Jul 25 05:25:28 PM PDT 24
Peak memory 257024 kb
Host smart-2642b925-c443-4f0b-bf13-bda8d728bde6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37396
36456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3739636456
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.1046393469
Short name T205
Test name
Test status
Simulation time 18351479 ps
CPU time 2.87 seconds
Started Jul 25 05:25:40 PM PDT 24
Finished Jul 25 05:25:43 PM PDT 24
Peak memory 249192 kb
Host smart-c13b2769-2984-4d62-aa2a-57a1525a4da1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1046393469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1046393469
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.1275054955
Short name T107
Test name
Test status
Simulation time 103577046481 ps
CPU time 1450.91 seconds
Started Jul 25 05:25:37 PM PDT 24
Finished Jul 25 05:49:49 PM PDT 24
Peak memory 273512 kb
Host smart-5b370925-23ac-4341-b34b-e372cf378be0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1275054955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.1275054955
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.818418227
Short name T475
Test name
Test status
Simulation time 349826809 ps
CPU time 14.12 seconds
Started Jul 25 05:25:37 PM PDT 24
Finished Jul 25 05:25:51 PM PDT 24
Peak memory 248804 kb
Host smart-5fed4056-4181-4e53-a3f2-d452a90258c6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=818418227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.818418227
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.1114821438
Short name T639
Test name
Test status
Simulation time 285434337 ps
CPU time 17.82 seconds
Started Jul 25 05:25:25 PM PDT 24
Finished Jul 25 05:25:43 PM PDT 24
Peak memory 248128 kb
Host smart-add345ce-cf88-4aa3-8f43-a186179b1bf3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11148
21438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.1114821438
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3974919777
Short name T428
Test name
Test status
Simulation time 37179457 ps
CPU time 6.17 seconds
Started Jul 25 05:25:22 PM PDT 24
Finished Jul 25 05:25:29 PM PDT 24
Peak memory 251772 kb
Host smart-8eae5e70-5a4e-41ec-ba44-bec0eb9ae5ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39749
19777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3974919777
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.3347107644
Short name T97
Test name
Test status
Simulation time 197615735185 ps
CPU time 2049.48 seconds
Started Jul 25 05:25:37 PM PDT 24
Finished Jul 25 05:59:47 PM PDT 24
Peak memory 289824 kb
Host smart-05521149-fe82-435b-bfa6-7339bd074067
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347107644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3347107644
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.193009284
Short name T544
Test name
Test status
Simulation time 106668838044 ps
CPU time 1829.55 seconds
Started Jul 25 05:25:37 PM PDT 24
Finished Jul 25 05:56:07 PM PDT 24
Peak memory 285932 kb
Host smart-4635ea9f-c7a5-4f5b-943b-5609f41d6439
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193009284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.193009284
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.834336772
Short name T604
Test name
Test status
Simulation time 48437381630 ps
CPU time 234.96 seconds
Started Jul 25 05:25:37 PM PDT 24
Finished Jul 25 05:29:32 PM PDT 24
Peak memory 248660 kb
Host smart-4a13fe9a-dd8f-466e-807d-ec41e553f37d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834336772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.834336772
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.4288709409
Short name T417
Test name
Test status
Simulation time 676599001 ps
CPU time 36.67 seconds
Started Jul 25 05:25:24 PM PDT 24
Finished Jul 25 05:26:01 PM PDT 24
Peak memory 248836 kb
Host smart-122b9279-26e8-4a4f-9484-0fd157c5dfae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42887
09409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.4288709409
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3602536606
Short name T652
Test name
Test status
Simulation time 7966425466 ps
CPU time 49.03 seconds
Started Jul 25 05:25:24 PM PDT 24
Finished Jul 25 05:26:13 PM PDT 24
Peak memory 248860 kb
Host smart-03bf217d-cb57-4583-8570-47a3cbf5f274
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36025
36606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3602536606
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1624085617
Short name T451
Test name
Test status
Simulation time 1834479397 ps
CPU time 57.15 seconds
Started Jul 25 05:25:39 PM PDT 24
Finished Jul 25 05:26:36 PM PDT 24
Peak memory 248908 kb
Host smart-68a459d6-6ba8-4d1a-80d7-9c88418e1db6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16240
85617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1624085617
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.1665720341
Short name T40
Test name
Test status
Simulation time 330272031 ps
CPU time 36.26 seconds
Started Jul 25 05:25:25 PM PDT 24
Finished Jul 25 05:26:02 PM PDT 24
Peak memory 257052 kb
Host smart-85b0be34-fedc-4f87-9691-524851a0ff3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16657
20341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1665720341
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1624354772
Short name T580
Test name
Test status
Simulation time 26877129626 ps
CPU time 1852.89 seconds
Started Jul 25 05:25:36 PM PDT 24
Finished Jul 25 05:56:29 PM PDT 24
Peak memory 273524 kb
Host smart-2da3ade1-84a7-408e-b75d-6235b350da9d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624354772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1624354772
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.2371560759
Short name T196
Test name
Test status
Simulation time 23092121 ps
CPU time 2.38 seconds
Started Jul 25 05:25:45 PM PDT 24
Finished Jul 25 05:25:47 PM PDT 24
Peak memory 249160 kb
Host smart-0f72079c-d92f-4467-969a-7615cf1b25f1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2371560759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.2371560759
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1958135618
Short name T549
Test name
Test status
Simulation time 144403913627 ps
CPU time 2069.02 seconds
Started Jul 25 05:25:45 PM PDT 24
Finished Jul 25 06:00:15 PM PDT 24
Peak memory 273504 kb
Host smart-fcf151a1-eb0c-4be2-adbe-aa8a3327b50c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958135618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1958135618
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.409173250
Short name T705
Test name
Test status
Simulation time 1621097862 ps
CPU time 20.55 seconds
Started Jul 25 05:25:46 PM PDT 24
Finished Jul 25 05:26:06 PM PDT 24
Peak memory 248860 kb
Host smart-d5d77d56-c8d1-4955-bf7f-6878cefd043c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=409173250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.409173250
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.873098941
Short name T469
Test name
Test status
Simulation time 3868426464 ps
CPU time 151.65 seconds
Started Jul 25 05:25:45 PM PDT 24
Finished Jul 25 05:28:17 PM PDT 24
Peak memory 257080 kb
Host smart-d61a344b-039b-4296-8a2a-239fdfa255fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87309
8941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.873098941
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.2429362058
Short name T434
Test name
Test status
Simulation time 70759593 ps
CPU time 7.99 seconds
Started Jul 25 05:25:37 PM PDT 24
Finished Jul 25 05:25:46 PM PDT 24
Peak memory 248828 kb
Host smart-f9eedc7b-5318-4e51-a670-879a5f21cf69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24293
62058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2429362058
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.889793622
Short name T344
Test name
Test status
Simulation time 25041913305 ps
CPU time 973.01 seconds
Started Jul 25 05:25:48 PM PDT 24
Finished Jul 25 05:42:02 PM PDT 24
Peak memory 273056 kb
Host smart-824156a8-ca39-4c81-b6ed-022af061e6f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889793622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.889793622
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.1629859995
Short name T649
Test name
Test status
Simulation time 28642303221 ps
CPU time 1426.67 seconds
Started Jul 25 05:25:47 PM PDT 24
Finished Jul 25 05:49:34 PM PDT 24
Peak memory 289116 kb
Host smart-9967020d-1d6c-434b-9642-e13b86f3a4b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629859995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.1629859995
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2588560266
Short name T413
Test name
Test status
Simulation time 1361032584 ps
CPU time 21.41 seconds
Started Jul 25 05:25:39 PM PDT 24
Finished Jul 25 05:26:00 PM PDT 24
Peak memory 248828 kb
Host smart-ed2778f1-adae-4833-9710-9c7701be9866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25885
60266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2588560266
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.2133987412
Short name T113
Test name
Test status
Simulation time 6409713549 ps
CPU time 48.74 seconds
Started Jul 25 05:25:38 PM PDT 24
Finished Jul 25 05:26:27 PM PDT 24
Peak memory 257036 kb
Host smart-a4b8d152-7046-4c89-a142-b984e6f7f797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21339
87412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2133987412
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2969828804
Short name T241
Test name
Test status
Simulation time 8500454900 ps
CPU time 30.4 seconds
Started Jul 25 05:25:48 PM PDT 24
Finished Jul 25 05:26:19 PM PDT 24
Peak memory 256364 kb
Host smart-84a1cbbc-afcf-41ed-a8d7-3a7d596571ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29698
28804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2969828804
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3782659375
Short name T622
Test name
Test status
Simulation time 297459572 ps
CPU time 26.12 seconds
Started Jul 25 05:25:36 PM PDT 24
Finished Jul 25 05:26:03 PM PDT 24
Peak memory 256164 kb
Host smart-2b9bcd70-4ba4-4fb6-a4fb-67e83f481f37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37826
59375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3782659375
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.364587815
Short name T535
Test name
Test status
Simulation time 52979426455 ps
CPU time 2887.25 seconds
Started Jul 25 05:25:46 PM PDT 24
Finished Jul 25 06:13:53 PM PDT 24
Peak memory 297996 kb
Host smart-fe91a32b-4483-4540-ada6-d74c209d0a5d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364587815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.364587815
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.1019790346
Short name T50
Test name
Test status
Simulation time 271230543661 ps
CPU time 6611.91 seconds
Started Jul 25 05:25:45 PM PDT 24
Finished Jul 25 07:15:58 PM PDT 24
Peak memory 355436 kb
Host smart-1fa31645-b827-4f07-936a-47ca8b4a0860
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019790346 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.1019790346
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1451299870
Short name T198
Test name
Test status
Simulation time 152139273 ps
CPU time 4.01 seconds
Started Jul 25 05:26:07 PM PDT 24
Finished Jul 25 05:26:11 PM PDT 24
Peak memory 249192 kb
Host smart-f6e66470-9822-4679-8206-3ad210f743b6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1451299870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1451299870
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3619116983
Short name T226
Test name
Test status
Simulation time 2315295922 ps
CPU time 28.65 seconds
Started Jul 25 05:26:07 PM PDT 24
Finished Jul 25 05:26:36 PM PDT 24
Peak memory 248764 kb
Host smart-e17c4972-2d34-42fa-870e-8dae76568f2e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3619116983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3619116983
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1555590353
Short name T615
Test name
Test status
Simulation time 3280105672 ps
CPU time 81.7 seconds
Started Jul 25 05:25:56 PM PDT 24
Finished Jul 25 05:27:18 PM PDT 24
Peak memory 256436 kb
Host smart-2faa6826-93c4-482b-b404-c452f98d4ca5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15555
90353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1555590353
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2057153519
Short name T175
Test name
Test status
Simulation time 2769854379 ps
CPU time 36.04 seconds
Started Jul 25 05:25:57 PM PDT 24
Finished Jul 25 05:26:33 PM PDT 24
Peak memory 249968 kb
Host smart-b3599b45-addc-4d7c-b6d0-156b5fa7f0b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20571
53519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2057153519
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.2836713957
Short name T343
Test name
Test status
Simulation time 179072522155 ps
CPU time 2290.29 seconds
Started Jul 25 05:26:10 PM PDT 24
Finished Jul 25 06:04:21 PM PDT 24
Peak memory 286252 kb
Host smart-9ec471db-722b-4e0d-9cc3-2a3edf523407
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836713957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.2836713957
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3407941128
Short name T314
Test name
Test status
Simulation time 11523088766 ps
CPU time 224.16 seconds
Started Jul 25 05:26:06 PM PDT 24
Finished Jul 25 05:29:51 PM PDT 24
Peak memory 248624 kb
Host smart-0b790fc5-3048-4718-ab52-792a7274fbb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407941128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3407941128
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.1598552465
Short name T488
Test name
Test status
Simulation time 452498256 ps
CPU time 12.36 seconds
Started Jul 25 05:25:47 PM PDT 24
Finished Jul 25 05:26:00 PM PDT 24
Peak memory 256392 kb
Host smart-4ca1cf7c-de38-4dd4-b14b-d92c95f2cdc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15985
52465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1598552465
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3090440240
Short name T275
Test name
Test status
Simulation time 144500610 ps
CPU time 8.81 seconds
Started Jul 25 05:25:56 PM PDT 24
Finished Jul 25 05:26:05 PM PDT 24
Peak memory 252804 kb
Host smart-9a351d9d-6f7f-47a0-8762-af812e9ecd14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30904
40240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3090440240
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2685577263
Short name T486
Test name
Test status
Simulation time 1536952642 ps
CPU time 24.94 seconds
Started Jul 25 05:25:59 PM PDT 24
Finished Jul 25 05:26:25 PM PDT 24
Peak memory 248900 kb
Host smart-9073bcfc-1cf1-4412-b605-6c72fd18eea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26855
77263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2685577263
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1797637026
Short name T398
Test name
Test status
Simulation time 1127124280 ps
CPU time 23.09 seconds
Started Jul 25 05:25:47 PM PDT 24
Finished Jul 25 05:26:10 PM PDT 24
Peak memory 256244 kb
Host smart-93bf76b5-7e2d-4a62-9191-576d243dbb79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17976
37026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1797637026
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1636012820
Short name T177
Test name
Test status
Simulation time 56708806 ps
CPU time 5.01 seconds
Started Jul 25 05:21:54 PM PDT 24
Finished Jul 25 05:21:59 PM PDT 24
Peak memory 249168 kb
Host smart-995ccf50-8be4-4d75-808d-2795ccc096f9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1636012820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1636012820
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.3324768602
Short name T468
Test name
Test status
Simulation time 124978130475 ps
CPU time 1469.61 seconds
Started Jul 25 05:21:54 PM PDT 24
Finished Jul 25 05:46:24 PM PDT 24
Peak memory 273440 kb
Host smart-6711040e-ce83-4d98-92a3-5aa4eeeb09ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324768602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.3324768602
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1635739914
Short name T375
Test name
Test status
Simulation time 430599433 ps
CPU time 21.75 seconds
Started Jul 25 05:21:53 PM PDT 24
Finished Jul 25 05:22:15 PM PDT 24
Peak memory 248880 kb
Host smart-a56d0c77-9216-4eb0-9bbd-440274e9649d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1635739914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1635739914
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.263181154
Short name T384
Test name
Test status
Simulation time 2390916377 ps
CPU time 157.99 seconds
Started Jul 25 05:22:04 PM PDT 24
Finished Jul 25 05:24:42 PM PDT 24
Peak memory 256452 kb
Host smart-d3f0094e-e480-4fc7-93f7-08acfb968dfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26318
1154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.263181154
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.118802423
Short name T637
Test name
Test status
Simulation time 1902966215 ps
CPU time 29.53 seconds
Started Jul 25 05:21:46 PM PDT 24
Finished Jul 25 05:22:16 PM PDT 24
Peak memory 255772 kb
Host smart-cf2e093b-74d7-4bbf-a44b-6c8060a4e83b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11880
2423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.118802423
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1791724078
Short name T517
Test name
Test status
Simulation time 20790097395 ps
CPU time 1047.19 seconds
Started Jul 25 05:21:54 PM PDT 24
Finished Jul 25 05:39:22 PM PDT 24
Peak memory 283804 kb
Host smart-7d634860-6b9c-4950-8edb-b55f41fd89a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791724078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1791724078
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.4194220682
Short name T452
Test name
Test status
Simulation time 20020177628 ps
CPU time 1572.92 seconds
Started Jul 25 05:22:01 PM PDT 24
Finished Jul 25 05:48:14 PM PDT 24
Peak memory 289204 kb
Host smart-d2fb9438-dc84-437d-a9e6-879ee5f77509
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194220682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.4194220682
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3584105277
Short name T460
Test name
Test status
Simulation time 89667640619 ps
CPU time 335.88 seconds
Started Jul 25 05:21:54 PM PDT 24
Finished Jul 25 05:27:30 PM PDT 24
Peak memory 248948 kb
Host smart-c094c9cd-266c-4730-91dc-dd4bdcfb6eb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584105277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3584105277
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.3907351078
Short name T433
Test name
Test status
Simulation time 405646220 ps
CPU time 12.55 seconds
Started Jul 25 05:21:44 PM PDT 24
Finished Jul 25 05:21:57 PM PDT 24
Peak memory 248828 kb
Host smart-40e4a7a2-9efd-4ad2-8ca4-18ec4dd7d8ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39073
51078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3907351078
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.446412481
Short name T179
Test name
Test status
Simulation time 199620645 ps
CPU time 8.22 seconds
Started Jul 25 05:21:45 PM PDT 24
Finished Jul 25 05:21:53 PM PDT 24
Peak memory 254848 kb
Host smart-dc011db7-1689-4a88-89ad-9ff7a516cd21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44641
2481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.446412481
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2790753023
Short name T9
Test name
Test status
Simulation time 455694970 ps
CPU time 15.35 seconds
Started Jul 25 05:22:01 PM PDT 24
Finished Jul 25 05:22:17 PM PDT 24
Peak memory 270280 kb
Host smart-b444f398-ba03-438c-ad26-7057b29727d6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2790753023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2790753023
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.925964182
Short name T427
Test name
Test status
Simulation time 532810611 ps
CPU time 18.61 seconds
Started Jul 25 05:21:54 PM PDT 24
Finished Jul 25 05:22:13 PM PDT 24
Peak memory 256140 kb
Host smart-ae6de5ce-8138-4836-8ff5-0e20fb98ebda
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92596
4182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.925964182
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1132823760
Short name T548
Test name
Test status
Simulation time 473819172 ps
CPU time 37.56 seconds
Started Jul 25 05:21:38 PM PDT 24
Finished Jul 25 05:22:16 PM PDT 24
Peak memory 248888 kb
Host smart-346946e2-4809-4170-9419-94bde17572a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11328
23760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1132823760
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2539901970
Short name T232
Test name
Test status
Simulation time 894345437031 ps
CPU time 3178.34 seconds
Started Jul 25 05:21:54 PM PDT 24
Finished Jul 25 06:14:53 PM PDT 24
Peak memory 289044 kb
Host smart-69a32243-c8cd-47ce-bb5b-2298e92f7589
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539901970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2539901970
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.969933163
Short name T645
Test name
Test status
Simulation time 31080074468 ps
CPU time 1854.97 seconds
Started Jul 25 05:26:18 PM PDT 24
Finished Jul 25 05:57:13 PM PDT 24
Peak memory 273344 kb
Host smart-474c3e2e-bee0-4be7-b01e-f91eab908255
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969933163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.969933163
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1174496602
Short name T378
Test name
Test status
Simulation time 22351025761 ps
CPU time 287.54 seconds
Started Jul 25 05:26:19 PM PDT 24
Finished Jul 25 05:31:07 PM PDT 24
Peak memory 257144 kb
Host smart-ec4eea34-326c-4327-b83e-2ac8778027f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11744
96602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1174496602
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3774777213
Short name T660
Test name
Test status
Simulation time 3136041176 ps
CPU time 71.31 seconds
Started Jul 25 05:26:20 PM PDT 24
Finished Jul 25 05:27:31 PM PDT 24
Peak memory 256600 kb
Host smart-2a7579b5-8db6-47e5-bbd2-1d73c479bccd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37747
77213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3774777213
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.878429522
Short name T338
Test name
Test status
Simulation time 17675769337 ps
CPU time 1489.28 seconds
Started Jul 25 05:26:31 PM PDT 24
Finished Jul 25 05:51:20 PM PDT 24
Peak memory 289192 kb
Host smart-87ab154c-a756-4f8d-898c-abe5118301c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878429522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.878429522
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.89833074
Short name T64
Test name
Test status
Simulation time 65618121736 ps
CPU time 2197.82 seconds
Started Jul 25 05:26:32 PM PDT 24
Finished Jul 25 06:03:10 PM PDT 24
Peak memory 286548 kb
Host smart-50d129d6-e025-40f5-a7a4-b92f9176d06c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89833074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.89833074
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2515946724
Short name T311
Test name
Test status
Simulation time 9461821411 ps
CPU time 103.9 seconds
Started Jul 25 05:26:33 PM PDT 24
Finished Jul 25 05:28:17 PM PDT 24
Peak memory 248796 kb
Host smart-2155be73-92f4-4689-8968-e8a36083243a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515946724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2515946724
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1520478791
Short name T441
Test name
Test status
Simulation time 655804162 ps
CPU time 49.41 seconds
Started Jul 25 05:26:19 PM PDT 24
Finished Jul 25 05:27:08 PM PDT 24
Peak memory 256044 kb
Host smart-83fec293-3644-4a91-9922-c83b28826a6d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15204
78791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1520478791
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1423100756
Short name T432
Test name
Test status
Simulation time 10491436604 ps
CPU time 73.97 seconds
Started Jul 25 05:26:20 PM PDT 24
Finished Jul 25 05:27:34 PM PDT 24
Peak memory 248892 kb
Host smart-db626c4d-7fa6-435e-851f-8f3c9806f556
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14231
00756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1423100756
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.2878614424
Short name T590
Test name
Test status
Simulation time 372373299 ps
CPU time 30.39 seconds
Started Jul 25 05:26:17 PM PDT 24
Finished Jul 25 05:26:48 PM PDT 24
Peak memory 248416 kb
Host smart-fd101c29-49c0-48bb-abd7-c3ac4f10767f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28786
14424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.2878614424
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3157935100
Short name T369
Test name
Test status
Simulation time 706736100 ps
CPU time 17.32 seconds
Started Jul 25 05:26:21 PM PDT 24
Finished Jul 25 05:26:39 PM PDT 24
Peak memory 257036 kb
Host smart-a40962bb-fa60-4e3e-b3f7-c7fb61686271
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31579
35100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3157935100
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2926850412
Short name T686
Test name
Test status
Simulation time 190577262880 ps
CPU time 2862.5 seconds
Started Jul 25 05:26:32 PM PDT 24
Finished Jul 25 06:14:15 PM PDT 24
Peak memory 281724 kb
Host smart-0c0c318f-b09b-47c3-bd2c-02e6682d606f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926850412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2926850412
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.65703121
Short name T706
Test name
Test status
Simulation time 197523064392 ps
CPU time 4447.65 seconds
Started Jul 25 05:26:31 PM PDT 24
Finished Jul 25 06:40:39 PM PDT 24
Peak memory 339112 kb
Host smart-9849e740-bcf1-4c1b-8022-744b0cf36c6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65703121 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.65703121
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3118558487
Short name T45
Test name
Test status
Simulation time 23700955250 ps
CPU time 1547.75 seconds
Started Jul 25 05:26:45 PM PDT 24
Finished Jul 25 05:52:33 PM PDT 24
Peak memory 273364 kb
Host smart-31d684b8-b81b-4f5c-b448-fc700ce06ef5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118558487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3118558487
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2263660252
Short name T530
Test name
Test status
Simulation time 1395330138 ps
CPU time 26.13 seconds
Started Jul 25 05:26:44 PM PDT 24
Finished Jul 25 05:27:10 PM PDT 24
Peak memory 248604 kb
Host smart-bc8d020c-c69c-4225-b5b3-f50ef63247ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22636
60252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2263660252
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.4252188525
Short name T71
Test name
Test status
Simulation time 175025067 ps
CPU time 9.46 seconds
Started Jul 25 05:26:44 PM PDT 24
Finished Jul 25 05:26:54 PM PDT 24
Peak memory 248424 kb
Host smart-51c979d1-f775-4194-a244-919c8dd130ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42521
88525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.4252188525
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1518982943
Short name T324
Test name
Test status
Simulation time 150972335470 ps
CPU time 2185.37 seconds
Started Jul 25 05:26:46 PM PDT 24
Finished Jul 25 06:03:11 PM PDT 24
Peak memory 273440 kb
Host smart-0f70dfc0-9e2e-4926-89ff-1c837e66d7ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518982943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1518982943
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.250652904
Short name T444
Test name
Test status
Simulation time 149368639168 ps
CPU time 2194.77 seconds
Started Jul 25 05:26:45 PM PDT 24
Finished Jul 25 06:03:20 PM PDT 24
Peak memory 281660 kb
Host smart-3579440f-bedb-477d-9a1b-2d68691c9268
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250652904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.250652904
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1700579169
Short name T613
Test name
Test status
Simulation time 520728159 ps
CPU time 16.34 seconds
Started Jul 25 05:26:29 PM PDT 24
Finished Jul 25 05:26:46 PM PDT 24
Peak memory 248880 kb
Host smart-bb27c062-c7d6-4b41-bc9f-f28544dafdae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17005
79169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1700579169
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3895804837
Short name T210
Test name
Test status
Simulation time 671868674 ps
CPU time 14.09 seconds
Started Jul 25 05:26:30 PM PDT 24
Finished Jul 25 05:26:44 PM PDT 24
Peak memory 248312 kb
Host smart-50f489f7-69cd-43df-a62f-7eb906c912e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38958
04837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3895804837
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1234896770
Short name T77
Test name
Test status
Simulation time 698042831 ps
CPU time 31.71 seconds
Started Jul 25 05:26:44 PM PDT 24
Finished Jul 25 05:27:15 PM PDT 24
Peak memory 248128 kb
Host smart-f4b19b96-0995-45dd-8a1c-3039ed5e368e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12348
96770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1234896770
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.1587709373
Short name T403
Test name
Test status
Simulation time 109796761 ps
CPU time 17.53 seconds
Started Jul 25 05:26:31 PM PDT 24
Finished Jul 25 05:26:49 PM PDT 24
Peak memory 256928 kb
Host smart-8f42f4c0-f13f-42eb-88be-77d548a7f72d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15877
09373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1587709373
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.3292724951
Short name T620
Test name
Test status
Simulation time 543044843441 ps
CPU time 7821.65 seconds
Started Jul 25 05:26:44 PM PDT 24
Finished Jul 25 07:37:07 PM PDT 24
Peak memory 339108 kb
Host smart-fbfbfaf1-7ae2-4fbb-bdeb-0c013bd185ab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292724951 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.3292724951
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.2999765396
Short name T402
Test name
Test status
Simulation time 116412217493 ps
CPU time 2065.89 seconds
Started Jul 25 05:26:58 PM PDT 24
Finished Jul 25 06:01:24 PM PDT 24
Peak memory 287112 kb
Host smart-0c242890-526e-47f2-8f9c-1424ef04a1be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999765396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2999765396
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.1129865834
Short name T498
Test name
Test status
Simulation time 1908179109 ps
CPU time 31.05 seconds
Started Jul 25 05:26:56 PM PDT 24
Finished Jul 25 05:27:27 PM PDT 24
Peak memory 257008 kb
Host smart-732a0e1b-6c07-4457-83fb-328415d9f889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11298
65834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1129865834
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.856502728
Short name T69
Test name
Test status
Simulation time 4528679961 ps
CPU time 66.06 seconds
Started Jul 25 05:26:55 PM PDT 24
Finished Jul 25 05:28:01 PM PDT 24
Peak memory 248880 kb
Host smart-a0da60cc-1191-44a0-9826-3a19b5628d97
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85650
2728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.856502728
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.2773939341
Short name T337
Test name
Test status
Simulation time 28683356576 ps
CPU time 1516.64 seconds
Started Jul 25 05:26:58 PM PDT 24
Finished Jul 25 05:52:15 PM PDT 24
Peak memory 273336 kb
Host smart-d8b725c1-0260-4b98-a2a3-0a96ddfa677e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773939341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.2773939341
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2550522736
Short name T211
Test name
Test status
Simulation time 43299658564 ps
CPU time 823.82 seconds
Started Jul 25 05:27:08 PM PDT 24
Finished Jul 25 05:40:52 PM PDT 24
Peak memory 268344 kb
Host smart-878c3888-4fcc-4c13-9bd2-3fc31cd81ceb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550522736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2550522736
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3314832914
Short name T296
Test name
Test status
Simulation time 21565393342 ps
CPU time 472.91 seconds
Started Jul 25 05:26:57 PM PDT 24
Finished Jul 25 05:34:50 PM PDT 24
Peak memory 248712 kb
Host smart-c849fb60-4ad1-4fbb-a06a-24cebea89bdc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314832914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3314832914
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.1499486233
Short name T616
Test name
Test status
Simulation time 64765054 ps
CPU time 8.32 seconds
Started Jul 25 05:26:59 PM PDT 24
Finished Jul 25 05:27:07 PM PDT 24
Peak memory 254624 kb
Host smart-db01b36c-b5ff-4013-93da-66aeb510cd01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14994
86233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1499486233
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.3580927102
Short name T404
Test name
Test status
Simulation time 546066707 ps
CPU time 31.49 seconds
Started Jul 25 05:26:58 PM PDT 24
Finished Jul 25 05:27:29 PM PDT 24
Peak memory 256600 kb
Host smart-b0da8eb4-cc93-4ce3-9b61-4b7a04065776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35809
27102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3580927102
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.93729496
Short name T225
Test name
Test status
Simulation time 315149894 ps
CPU time 36.67 seconds
Started Jul 25 05:26:57 PM PDT 24
Finished Jul 25 05:27:34 PM PDT 24
Peak memory 256584 kb
Host smart-34e2720f-a663-4ace-ac63-94cb12fdb0d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93729
496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.93729496
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.2574940739
Short name T482
Test name
Test status
Simulation time 138403512 ps
CPU time 10.81 seconds
Started Jul 25 05:26:55 PM PDT 24
Finished Jul 25 05:27:06 PM PDT 24
Peak memory 248844 kb
Host smart-59e0deab-a188-4f1c-9f0d-d5cf4a99429d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25749
40739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2574940739
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.367325463
Short name T246
Test name
Test status
Simulation time 37174578420 ps
CPU time 3791.61 seconds
Started Jul 25 05:27:08 PM PDT 24
Finished Jul 25 06:30:20 PM PDT 24
Peak memory 338304 kb
Host smart-ad385499-8d51-4ac9-84b5-8ae5c5954ff1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367325463 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.367325463
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.3248920441
Short name T499
Test name
Test status
Simulation time 92495805878 ps
CPU time 1387.57 seconds
Started Jul 25 05:27:16 PM PDT 24
Finished Jul 25 05:50:24 PM PDT 24
Peak memory 272420 kb
Host smart-f1e9322f-bb50-4f33-9a72-a7c68f57fe73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248920441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.3248920441
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3563157339
Short name T425
Test name
Test status
Simulation time 3299045934 ps
CPU time 101.11 seconds
Started Jul 25 05:27:17 PM PDT 24
Finished Jul 25 05:28:59 PM PDT 24
Peak memory 257028 kb
Host smart-0710e261-4ca1-48b0-b0e8-8d77c428d3d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35631
57339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3563157339
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.545193604
Short name T80
Test name
Test status
Simulation time 1044990809 ps
CPU time 25.99 seconds
Started Jul 25 05:27:19 PM PDT 24
Finished Jul 25 05:27:45 PM PDT 24
Peak memory 257004 kb
Host smart-47611724-f58b-4576-a731-47f359624da5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54519
3604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.545193604
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.3428250696
Short name T38
Test name
Test status
Simulation time 139503349427 ps
CPU time 2685.7 seconds
Started Jul 25 05:27:20 PM PDT 24
Finished Jul 25 06:12:06 PM PDT 24
Peak memory 289520 kb
Host smart-255e13d9-d490-4a21-9b95-1fc6e90d127b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428250696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.3428250696
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.3089996490
Short name T695
Test name
Test status
Simulation time 12421053783 ps
CPU time 544.7 seconds
Started Jul 25 05:27:20 PM PDT 24
Finished Jul 25 05:36:25 PM PDT 24
Peak memory 247696 kb
Host smart-ad500380-cfce-4901-ad53-669fe3bc4367
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089996490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.3089996490
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.1022974919
Short name T592
Test name
Test status
Simulation time 287296969 ps
CPU time 27.04 seconds
Started Jul 25 05:27:07 PM PDT 24
Finished Jul 25 05:27:34 PM PDT 24
Peak memory 256944 kb
Host smart-7116fba7-3793-4cbf-be6d-55b20beac163
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10229
74919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1022974919
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3785872704
Short name T377
Test name
Test status
Simulation time 1778159598 ps
CPU time 50.72 seconds
Started Jul 25 05:27:09 PM PDT 24
Finished Jul 25 05:28:00 PM PDT 24
Peak memory 248856 kb
Host smart-0cae8739-473b-4b5f-b3ec-d12accca11ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37858
72704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3785872704
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.4290182825
Short name T248
Test name
Test status
Simulation time 2248213489 ps
CPU time 57.44 seconds
Started Jul 25 05:27:18 PM PDT 24
Finished Jul 25 05:28:16 PM PDT 24
Peak memory 257100 kb
Host smart-f5f09c4d-1ec4-47eb-9304-59b7a15d0539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42901
82825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.4290182825
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.2702180334
Short name T368
Test name
Test status
Simulation time 1931798609 ps
CPU time 13.61 seconds
Started Jul 25 05:27:08 PM PDT 24
Finished Jul 25 05:27:21 PM PDT 24
Peak memory 253800 kb
Host smart-2739809e-7e66-47b8-a2f9-a7d1f2d48c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27021
80334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.2702180334
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.483537080
Short name T83
Test name
Test status
Simulation time 1394085393 ps
CPU time 157.56 seconds
Started Jul 25 05:27:19 PM PDT 24
Finished Jul 25 05:29:57 PM PDT 24
Peak memory 256964 kb
Host smart-6a2651d9-3ad7-4e85-9b69-1fcdc391cdbc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483537080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_han
dler_stress_all.483537080
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.205953287
Short name T713
Test name
Test status
Simulation time 9552605653 ps
CPU time 1401.8 seconds
Started Jul 25 05:27:32 PM PDT 24
Finished Jul 25 05:50:54 PM PDT 24
Peak memory 287556 kb
Host smart-fcb2f95b-d72a-4007-8a93-39ef944a955b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205953287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.205953287
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.118031374
Short name T41
Test name
Test status
Simulation time 13228982188 ps
CPU time 199.6 seconds
Started Jul 25 05:27:38 PM PDT 24
Finished Jul 25 05:30:58 PM PDT 24
Peak memory 257140 kb
Host smart-16b36f24-da2b-47f4-a7f4-93260cbf3506
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11803
1374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.118031374
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2505923554
Short name T558
Test name
Test status
Simulation time 399914926 ps
CPU time 28.93 seconds
Started Jul 25 05:27:32 PM PDT 24
Finished Jul 25 05:28:01 PM PDT 24
Peak memory 248604 kb
Host smart-b07c422f-a1f3-4965-95aa-2841e82ec022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25059
23554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2505923554
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.1407418104
Short name T16
Test name
Test status
Simulation time 37158163730 ps
CPU time 1374.26 seconds
Started Jul 25 05:27:50 PM PDT 24
Finished Jul 25 05:50:44 PM PDT 24
Peak memory 281648 kb
Host smart-9c2b97ea-c73a-41c1-bc38-f64a0cfcc491
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407418104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.1407418104
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.496801876
Short name T568
Test name
Test status
Simulation time 116034353750 ps
CPU time 1614.93 seconds
Started Jul 25 05:27:46 PM PDT 24
Finished Jul 25 05:54:41 PM PDT 24
Peak memory 273524 kb
Host smart-5093fad6-e199-4af0-9a10-515793f1c9f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496801876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.496801876
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1460075144
Short name T3
Test name
Test status
Simulation time 35397908463 ps
CPU time 414.23 seconds
Started Jul 25 05:27:46 PM PDT 24
Finished Jul 25 05:34:41 PM PDT 24
Peak memory 247824 kb
Host smart-be5ff5ae-bef2-4de3-aadb-c826930fd879
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460075144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1460075144
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.3213101895
Short name T586
Test name
Test status
Simulation time 2753235997 ps
CPU time 32.81 seconds
Started Jul 25 05:27:30 PM PDT 24
Finished Jul 25 05:28:03 PM PDT 24
Peak memory 256376 kb
Host smart-f05f6084-6c53-4f11-9f63-f0de994710f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32131
01895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.3213101895
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.385313534
Short name T58
Test name
Test status
Simulation time 5995922761 ps
CPU time 55.32 seconds
Started Jul 25 05:27:31 PM PDT 24
Finished Jul 25 05:28:26 PM PDT 24
Peak memory 248528 kb
Host smart-da9546fa-bb47-4776-a21d-4da38d8a2acd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38531
3534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.385313534
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.2028054658
Short name T471
Test name
Test status
Simulation time 247186098 ps
CPU time 16.9 seconds
Started Jul 25 05:27:31 PM PDT 24
Finished Jul 25 05:27:48 PM PDT 24
Peak memory 255400 kb
Host smart-6f386600-4b40-434d-8cf0-9667161cfd32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20280
54658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2028054658
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.763708285
Short name T621
Test name
Test status
Simulation time 1799541887 ps
CPU time 54.56 seconds
Started Jul 25 05:27:32 PM PDT 24
Finished Jul 25 05:28:27 PM PDT 24
Peak memory 256876 kb
Host smart-2f9dc97c-e12e-4eae-bf8e-d1edfeaa95ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76370
8285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.763708285
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3906450628
Short name T492
Test name
Test status
Simulation time 3390046533 ps
CPU time 254.54 seconds
Started Jul 25 05:27:50 PM PDT 24
Finished Jul 25 05:32:04 PM PDT 24
Peak memory 257068 kb
Host smart-a7e26435-41e7-4eb2-bc9d-ceb49997bbb1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906450628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3906450628
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.4016357470
Short name T632
Test name
Test status
Simulation time 19924381104 ps
CPU time 1271.01 seconds
Started Jul 25 05:28:02 PM PDT 24
Finished Jul 25 05:49:13 PM PDT 24
Peak memory 289852 kb
Host smart-01c90e05-c601-4b1f-8bfd-f04a2010d49f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016357470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.4016357470
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1016188740
Short name T658
Test name
Test status
Simulation time 14707620521 ps
CPU time 246.78 seconds
Started Jul 25 05:28:02 PM PDT 24
Finished Jul 25 05:32:09 PM PDT 24
Peak memory 256348 kb
Host smart-d9efe446-5b8d-4d39-b763-4db8b759c9e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10161
88740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1016188740
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1871124337
Short name T218
Test name
Test status
Simulation time 236508587 ps
CPU time 9.25 seconds
Started Jul 25 05:28:03 PM PDT 24
Finished Jul 25 05:28:12 PM PDT 24
Peak memory 248488 kb
Host smart-2e13f9a4-a5d1-4cda-987e-96f14fb9e510
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18711
24337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1871124337
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3166473487
Short name T601
Test name
Test status
Simulation time 28585870206 ps
CPU time 818.33 seconds
Started Jul 25 05:28:01 PM PDT 24
Finished Jul 25 05:41:39 PM PDT 24
Peak memory 271564 kb
Host smart-2f179069-413d-4424-ae60-7f5665c6ecdb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166473487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3166473487
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.2874369192
Short name T100
Test name
Test status
Simulation time 39629398122 ps
CPU time 1335.6 seconds
Started Jul 25 05:28:16 PM PDT 24
Finished Jul 25 05:50:32 PM PDT 24
Peak memory 273364 kb
Host smart-944bc7bb-ec20-4bf7-aaf8-5c97998a35f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874369192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.2874369192
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3839851827
Short name T667
Test name
Test status
Simulation time 17128656115 ps
CPU time 177.18 seconds
Started Jul 25 05:28:02 PM PDT 24
Finished Jul 25 05:30:59 PM PDT 24
Peak memory 254472 kb
Host smart-a223b03d-8bdd-4200-996b-0b96b05bffe8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839851827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3839851827
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2552869257
Short name T700
Test name
Test status
Simulation time 297119174 ps
CPU time 31.02 seconds
Started Jul 25 05:27:50 PM PDT 24
Finished Jul 25 05:28:22 PM PDT 24
Peak memory 256080 kb
Host smart-1e9bfe51-bb6e-4f94-899a-8999e4b489d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25528
69257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2552869257
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.487488769
Short name T670
Test name
Test status
Simulation time 91799333 ps
CPU time 7.07 seconds
Started Jul 25 05:28:02 PM PDT 24
Finished Jul 25 05:28:09 PM PDT 24
Peak memory 251996 kb
Host smart-e2faf098-0de6-435a-93af-a20263a1e57d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48748
8769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.487488769
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.4066144148
Short name T516
Test name
Test status
Simulation time 289435950 ps
CPU time 30.74 seconds
Started Jul 25 05:28:03 PM PDT 24
Finished Jul 25 05:28:33 PM PDT 24
Peak memory 256564 kb
Host smart-5318349d-1bcd-4a11-807c-d0f5528b1532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40661
44148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.4066144148
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2951351903
Short name T569
Test name
Test status
Simulation time 1175066923 ps
CPU time 22.26 seconds
Started Jul 25 05:27:46 PM PDT 24
Finished Jul 25 05:28:09 PM PDT 24
Peak memory 248776 kb
Host smart-93e99457-6a36-4fb8-aee2-bd5a158fec6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29513
51903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2951351903
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3616362084
Short name T70
Test name
Test status
Simulation time 4408584491 ps
CPU time 54.31 seconds
Started Jul 25 05:28:15 PM PDT 24
Finished Jul 25 05:29:10 PM PDT 24
Peak memory 255844 kb
Host smart-79e220ad-62ec-4441-96f3-8c5dc9878774
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616362084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3616362084
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.1651260984
Short name T606
Test name
Test status
Simulation time 10190786857 ps
CPU time 171.36 seconds
Started Jul 25 05:28:17 PM PDT 24
Finished Jul 25 05:31:09 PM PDT 24
Peak memory 257116 kb
Host smart-3987256c-491e-4f3a-a0a8-071cbc8350c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16512
60984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.1651260984
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.822683799
Short name T442
Test name
Test status
Simulation time 2906703692 ps
CPU time 55.67 seconds
Started Jul 25 05:28:16 PM PDT 24
Finished Jul 25 05:29:11 PM PDT 24
Peak memory 248968 kb
Host smart-5b8e8eb3-7c3e-4d60-90ee-c325879d7b07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82268
3799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.822683799
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.3618086776
Short name T345
Test name
Test status
Simulation time 21187194159 ps
CPU time 1123.24 seconds
Started Jul 25 05:28:28 PM PDT 24
Finished Jul 25 05:47:12 PM PDT 24
Peak memory 285740 kb
Host smart-9ce34b38-d217-49e8-9234-e04b26038456
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618086776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.3618086776
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.2313190147
Short name T37
Test name
Test status
Simulation time 146073111143 ps
CPU time 2446.57 seconds
Started Jul 25 05:28:27 PM PDT 24
Finished Jul 25 06:09:14 PM PDT 24
Peak memory 288872 kb
Host smart-8b105ffb-d4c6-47ec-be8f-d5e7969f1c22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313190147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.2313190147
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.1808776341
Short name T572
Test name
Test status
Simulation time 5072919710 ps
CPU time 213.2 seconds
Started Jul 25 05:28:27 PM PDT 24
Finished Jul 25 05:32:00 PM PDT 24
Peak memory 248768 kb
Host smart-8353f915-ec7d-4d70-8667-e2a0fc6c55cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808776341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1808776341
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.3628688826
Short name T439
Test name
Test status
Simulation time 647254003 ps
CPU time 38.8 seconds
Started Jul 25 05:28:15 PM PDT 24
Finished Jul 25 05:28:54 PM PDT 24
Peak memory 248868 kb
Host smart-e84a9c68-1a47-49eb-8add-b45eb6a90866
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36286
88826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.3628688826
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2261692571
Short name T270
Test name
Test status
Simulation time 5100335165 ps
CPU time 69.95 seconds
Started Jul 25 05:28:16 PM PDT 24
Finished Jul 25 05:29:26 PM PDT 24
Peak memory 248832 kb
Host smart-9b209d8f-9f5d-4af8-9dba-b9836f28c7e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22616
92571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2261692571
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.3525479591
Short name T251
Test name
Test status
Simulation time 1160529972 ps
CPU time 26.45 seconds
Started Jul 25 05:28:15 PM PDT 24
Finished Jul 25 05:28:42 PM PDT 24
Peak memory 248684 kb
Host smart-00dcfed4-0928-4bad-9e16-7583f5f5d797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35254
79591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3525479591
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2208430821
Short name T374
Test name
Test status
Simulation time 1993956026 ps
CPU time 20.95 seconds
Started Jul 25 05:28:16 PM PDT 24
Finished Jul 25 05:28:37 PM PDT 24
Peak memory 255632 kb
Host smart-c5076d50-6999-4a28-99f8-76af4499158a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22084
30821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2208430821
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.3419433118
Short name T395
Test name
Test status
Simulation time 37973079518 ps
CPU time 901.14 seconds
Started Jul 25 05:28:49 PM PDT 24
Finished Jul 25 05:43:50 PM PDT 24
Peak memory 281592 kb
Host smart-b6ecc6af-a3e8-43ed-8035-5b6f4dcd5881
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419433118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.3419433118
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.1280989481
Short name T694
Test name
Test status
Simulation time 15199484889 ps
CPU time 290.31 seconds
Started Jul 25 05:28:48 PM PDT 24
Finished Jul 25 05:33:38 PM PDT 24
Peak memory 252052 kb
Host smart-6760ee97-6f99-4b3a-a199-d6dee6d1fdf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12809
89481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1280989481
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.3902234417
Short name T659
Test name
Test status
Simulation time 764289654 ps
CPU time 18.7 seconds
Started Jul 25 05:28:50 PM PDT 24
Finished Jul 25 05:29:09 PM PDT 24
Peak memory 248796 kb
Host smart-2a5365ce-7010-40ef-b857-52eaa6abc439
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39022
34417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.3902234417
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2509549542
Short name T335
Test name
Test status
Simulation time 164961106378 ps
CPU time 2211.87 seconds
Started Jul 25 05:29:19 PM PDT 24
Finished Jul 25 06:06:11 PM PDT 24
Peak memory 272856 kb
Host smart-4dd205fa-4fde-42e4-9e5b-45cb7caf969f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509549542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2509549542
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.809949863
Short name T208
Test name
Test status
Simulation time 523575773660 ps
CPU time 2815.12 seconds
Started Jul 25 05:29:04 PM PDT 24
Finished Jul 25 06:15:59 PM PDT 24
Peak memory 288884 kb
Host smart-67f08da8-dd31-4eab-ab67-8b8e728ec936
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809949863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.809949863
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1536227418
Short name T291
Test name
Test status
Simulation time 6785625005 ps
CPU time 301.03 seconds
Started Jul 25 05:29:01 PM PDT 24
Finished Jul 25 05:34:02 PM PDT 24
Peak memory 248920 kb
Host smart-5d356e58-7eb5-4c5f-a56d-4f90a0c9e7e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536227418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1536227418
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2037862057
Short name T566
Test name
Test status
Simulation time 113277528 ps
CPU time 10.79 seconds
Started Jul 25 05:28:40 PM PDT 24
Finished Jul 25 05:28:51 PM PDT 24
Peak memory 248816 kb
Host smart-dfd76830-de2d-439b-a5ce-8429e737d0c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20378
62057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2037862057
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.4186909943
Short name T274
Test name
Test status
Simulation time 4097686598 ps
CPU time 59.93 seconds
Started Jul 25 05:28:47 PM PDT 24
Finished Jul 25 05:29:47 PM PDT 24
Peak memory 248964 kb
Host smart-52865edd-315f-42d0-a4de-199174e9b353
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41869
09943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.4186909943
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.4157461180
Short name T111
Test name
Test status
Simulation time 495979513 ps
CPU time 56.24 seconds
Started Jul 25 05:28:48 PM PDT 24
Finished Jul 25 05:29:44 PM PDT 24
Peak memory 248436 kb
Host smart-d44b4cf8-5a49-4e48-a849-82718db9399b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41574
61180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.4157461180
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1586397115
Short name T15
Test name
Test status
Simulation time 3005865930 ps
CPU time 50.32 seconds
Started Jul 25 05:28:44 PM PDT 24
Finished Jul 25 05:29:34 PM PDT 24
Peak memory 257088 kb
Host smart-54ecbf11-bba6-4add-8fd0-7f81955472d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15863
97115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1586397115
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.4222866293
Short name T89
Test name
Test status
Simulation time 28974747049 ps
CPU time 1368.04 seconds
Started Jul 25 05:29:02 PM PDT 24
Finished Jul 25 05:51:51 PM PDT 24
Peak memory 289768 kb
Host smart-a31292a1-616a-4bb5-bb80-378c0cfe008a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222866293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.4222866293
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.4106482559
Short name T285
Test name
Test status
Simulation time 22900368806 ps
CPU time 1416.46 seconds
Started Jul 25 05:29:31 PM PDT 24
Finished Jul 25 05:53:08 PM PDT 24
Peak memory 265324 kb
Host smart-0c14bf66-c6ba-4215-9f5a-77bbeddc5c7b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106482559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.4106482559
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.846550663
Short name T461
Test name
Test status
Simulation time 1733282230 ps
CPU time 91.49 seconds
Started Jul 25 05:29:18 PM PDT 24
Finished Jul 25 05:30:50 PM PDT 24
Peak memory 256584 kb
Host smart-9b7731c4-9ac1-4995-abd6-c2d5bdd6df13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84655
0663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.846550663
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.165081880
Short name T559
Test name
Test status
Simulation time 2180302235 ps
CPU time 27.62 seconds
Started Jul 25 05:29:20 PM PDT 24
Finished Jul 25 05:29:48 PM PDT 24
Peak memory 255704 kb
Host smart-25647624-c28b-4eb2-900a-771d61d663aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16508
1880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.165081880
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.3213885152
Short name T614
Test name
Test status
Simulation time 34207193527 ps
CPU time 669.37 seconds
Started Jul 25 05:29:32 PM PDT 24
Finished Jul 25 05:40:41 PM PDT 24
Peak memory 272776 kb
Host smart-1d9e2a3d-93ec-4c14-a415-a9980951d6eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213885152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.3213885152
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.1989988624
Short name T625
Test name
Test status
Simulation time 28677295044 ps
CPU time 1932.39 seconds
Started Jul 25 05:29:30 PM PDT 24
Finished Jul 25 06:01:43 PM PDT 24
Peak memory 286660 kb
Host smart-16420508-ab59-440b-a9c6-ade1bf3757c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989988624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1989988624
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1338165119
Short name T543
Test name
Test status
Simulation time 9471228319 ps
CPU time 108.24 seconds
Started Jul 25 05:29:30 PM PDT 24
Finished Jul 25 05:31:18 PM PDT 24
Peak memory 255516 kb
Host smart-648ffdc7-a102-4be6-8f3d-1586fadf9ceb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338165119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1338165119
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1066686347
Short name T536
Test name
Test status
Simulation time 3197418279 ps
CPU time 56.17 seconds
Started Jul 25 05:29:02 PM PDT 24
Finished Jul 25 05:29:59 PM PDT 24
Peak memory 256684 kb
Host smart-e84c74b5-5801-4f26-8076-5736d8d3c994
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10666
86347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1066686347
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2648197962
Short name T685
Test name
Test status
Simulation time 231685275 ps
CPU time 7.27 seconds
Started Jul 25 05:29:19 PM PDT 24
Finished Jul 25 05:29:26 PM PDT 24
Peak memory 248320 kb
Host smart-8abd0b7c-e029-455e-8613-bd6dcc33e8cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26481
97962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2648197962
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.1084067190
Short name T390
Test name
Test status
Simulation time 119377744 ps
CPU time 4.7 seconds
Started Jul 25 05:29:20 PM PDT 24
Finished Jul 25 05:29:24 PM PDT 24
Peak memory 252300 kb
Host smart-570c5997-0d74-4f44-9700-f6b095da583e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10840
67190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1084067190
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.3013297519
Short name T436
Test name
Test status
Simulation time 832515934 ps
CPU time 51.71 seconds
Started Jul 25 05:29:03 PM PDT 24
Finished Jul 25 05:29:55 PM PDT 24
Peak memory 257036 kb
Host smart-c3fe2a65-cb0c-409a-a3be-d1df55db4dc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30132
97519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.3013297519
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2313065029
Short name T264
Test name
Test status
Simulation time 83082516974 ps
CPU time 1410.11 seconds
Started Jul 25 05:29:40 PM PDT 24
Finished Jul 25 05:53:10 PM PDT 24
Peak memory 288456 kb
Host smart-aca8bf74-2e44-4f86-8af0-b2f50f45fb97
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313065029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2313065029
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3838026841
Short name T712
Test name
Test status
Simulation time 3276690264 ps
CPU time 46.42 seconds
Started Jul 25 05:29:38 PM PDT 24
Finished Jul 25 05:30:24 PM PDT 24
Peak memory 256096 kb
Host smart-5a8eb96c-6513-4e4d-a4fe-a27c8eee5889
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38380
26841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3838026841
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3407488671
Short name T63
Test name
Test status
Simulation time 223662027 ps
CPU time 23.63 seconds
Started Jul 25 05:29:30 PM PDT 24
Finished Jul 25 05:29:54 PM PDT 24
Peak memory 256996 kb
Host smart-844a2564-e53b-40fb-acf3-aa9cb6af028e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34074
88671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3407488671
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.3375847150
Short name T212
Test name
Test status
Simulation time 86024535778 ps
CPU time 1290.77 seconds
Started Jul 25 05:29:39 PM PDT 24
Finished Jul 25 05:51:10 PM PDT 24
Peak memory 289656 kb
Host smart-701c813c-4cd7-40c8-8e54-135ce71ab497
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375847150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.3375847150
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1323801480
Short name T561
Test name
Test status
Simulation time 61365355271 ps
CPU time 1765.06 seconds
Started Jul 25 05:29:42 PM PDT 24
Finished Jul 25 05:59:07 PM PDT 24
Peak memory 273464 kb
Host smart-b23ee742-d34e-4240-96d1-ce0f68327f96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323801480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1323801480
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.1824189922
Short name T308
Test name
Test status
Simulation time 11085422212 ps
CPU time 332.58 seconds
Started Jul 25 05:29:39 PM PDT 24
Finished Jul 25 05:35:12 PM PDT 24
Peak memory 255312 kb
Host smart-f8aa4289-a2f0-42c1-8343-fff2a51ce5ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824189922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.1824189922
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.3060824323
Short name T500
Test name
Test status
Simulation time 2539018924 ps
CPU time 23.98 seconds
Started Jul 25 05:29:31 PM PDT 24
Finished Jul 25 05:29:55 PM PDT 24
Peak memory 248864 kb
Host smart-19e5c141-80a6-49b0-a318-d2aa69ad432b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30608
24323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3060824323
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.657426559
Short name T249
Test name
Test status
Simulation time 1942248409 ps
CPU time 40.04 seconds
Started Jul 25 05:29:31 PM PDT 24
Finished Jul 25 05:30:11 PM PDT 24
Peak memory 249852 kb
Host smart-e213869c-117c-4c12-8bf7-570d9062e4a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65742
6559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.657426559
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.2437354511
Short name T648
Test name
Test status
Simulation time 316037087 ps
CPU time 9.66 seconds
Started Jul 25 05:29:42 PM PDT 24
Finished Jul 25 05:29:52 PM PDT 24
Peak memory 248456 kb
Host smart-0057e84d-e0cd-43f5-bcb8-d80402895643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24373
54511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2437354511
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2056185692
Short name T682
Test name
Test status
Simulation time 2951825100 ps
CPU time 50.41 seconds
Started Jul 25 05:29:32 PM PDT 24
Finished Jul 25 05:30:22 PM PDT 24
Peak memory 257036 kb
Host smart-96e75144-89f6-431d-acb6-0c39b4d491b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20561
85692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2056185692
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3552962354
Short name T253
Test name
Test status
Simulation time 38519285250 ps
CPU time 2425.26 seconds
Started Jul 25 05:29:49 PM PDT 24
Finished Jul 25 06:10:15 PM PDT 24
Peak memory 284416 kb
Host smart-82abfadb-248d-4e14-8838-af5c3812ee9d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552962354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3552962354
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.2837115057
Short name T201
Test name
Test status
Simulation time 24362019 ps
CPU time 2.69 seconds
Started Jul 25 05:22:07 PM PDT 24
Finished Jul 25 05:22:10 PM PDT 24
Peak memory 249184 kb
Host smart-9f361fc1-04a9-4497-9b1a-c1afbdfe1755
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2837115057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2837115057
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1187926398
Short name T463
Test name
Test status
Simulation time 14236724137 ps
CPU time 1167.73 seconds
Started Jul 25 05:22:00 PM PDT 24
Finished Jul 25 05:41:28 PM PDT 24
Peak memory 288932 kb
Host smart-554c4133-1c5e-4f73-8fd8-2cf32ff9e6d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187926398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1187926398
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.2812989332
Short name T655
Test name
Test status
Simulation time 951864868 ps
CPU time 37.04 seconds
Started Jul 25 05:22:09 PM PDT 24
Finished Jul 25 05:22:46 PM PDT 24
Peak memory 248864 kb
Host smart-d7c686b8-1357-4229-be61-ed536cf3abb4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2812989332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.2812989332
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3948963211
Short name T182
Test name
Test status
Simulation time 3674329831 ps
CPU time 222.57 seconds
Started Jul 25 05:21:59 PM PDT 24
Finished Jul 25 05:25:42 PM PDT 24
Peak memory 256620 kb
Host smart-fdb82ef2-3be8-4d78-bb89-f3d5576c3270
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39489
63211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3948963211
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2466039245
Short name T59
Test name
Test status
Simulation time 969532412 ps
CPU time 54.57 seconds
Started Jul 25 05:22:01 PM PDT 24
Finished Jul 25 05:22:55 PM PDT 24
Peak memory 248460 kb
Host smart-e945ce91-7562-4fb9-b816-18b1602ac79a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24660
39245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2466039245
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.895865299
Short name T348
Test name
Test status
Simulation time 88125534265 ps
CPU time 2807.34 seconds
Started Jul 25 05:22:07 PM PDT 24
Finished Jul 25 06:08:55 PM PDT 24
Peak memory 289916 kb
Host smart-3531f931-2775-476e-9733-e7d7e8816681
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895865299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.895865299
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.4109104734
Short name T219
Test name
Test status
Simulation time 26794609765 ps
CPU time 1337.03 seconds
Started Jul 25 05:22:09 PM PDT 24
Finished Jul 25 05:44:26 PM PDT 24
Peak memory 282456 kb
Host smart-905cea12-6a5f-4372-80e8-a78921d35fc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109104734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.4109104734
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1689570591
Short name T321
Test name
Test status
Simulation time 5466748593 ps
CPU time 209.65 seconds
Started Jul 25 05:22:08 PM PDT 24
Finished Jul 25 05:25:38 PM PDT 24
Peak memory 247896 kb
Host smart-957e90b3-e366-4601-bad7-9fee4f84c9e6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689570591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1689570591
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.663047609
Short name T642
Test name
Test status
Simulation time 180703428 ps
CPU time 8.15 seconds
Started Jul 25 05:22:00 PM PDT 24
Finished Jul 25 05:22:09 PM PDT 24
Peak memory 253536 kb
Host smart-4bc16a45-3f9a-4ac2-90bc-8809a5eecf1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66304
7609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.663047609
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.951667113
Short name T611
Test name
Test status
Simulation time 589725596 ps
CPU time 38.01 seconds
Started Jul 25 05:22:02 PM PDT 24
Finished Jul 25 05:22:40 PM PDT 24
Peak memory 248364 kb
Host smart-ad5a79ca-ed3b-4ca1-9db7-a03eed0a6b2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95166
7113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.951667113
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.135299376
Short name T472
Test name
Test status
Simulation time 559727173 ps
CPU time 30.96 seconds
Started Jul 25 05:22:00 PM PDT 24
Finished Jul 25 05:22:31 PM PDT 24
Peak memory 257040 kb
Host smart-1201cecc-6597-4123-be9b-ad9a48385594
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13529
9376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.135299376
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.863575388
Short name T570
Test name
Test status
Simulation time 217689187033 ps
CPU time 3039.01 seconds
Started Jul 25 05:22:06 PM PDT 24
Finished Jul 25 06:12:45 PM PDT 24
Peak memory 289872 kb
Host smart-90b15182-fb12-4eee-84c8-f2488d5b0efd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863575388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_hand
ler_stress_all.863575388
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.3045003878
Short name T90
Test name
Test status
Simulation time 18254934130 ps
CPU time 805.5 seconds
Started Jul 25 05:30:15 PM PDT 24
Finished Jul 25 05:43:41 PM PDT 24
Peak memory 272828 kb
Host smart-1da348d6-c813-4074-9990-10c44d942b7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045003878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.3045003878
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.2779340689
Short name T454
Test name
Test status
Simulation time 1134584962 ps
CPU time 70.59 seconds
Started Jul 25 05:30:15 PM PDT 24
Finished Jul 25 05:31:26 PM PDT 24
Peak memory 256628 kb
Host smart-1cf4a23f-033a-4eee-ad11-e3e0be6231fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27793
40689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.2779340689
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.691113226
Short name T217
Test name
Test status
Simulation time 2541800530 ps
CPU time 28.9 seconds
Started Jul 25 05:29:59 PM PDT 24
Finished Jul 25 05:30:28 PM PDT 24
Peak memory 248620 kb
Host smart-fe7d9da9-a788-4ab8-831a-b78d7bd6328c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69111
3226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.691113226
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.836648728
Short name T336
Test name
Test status
Simulation time 15998466422 ps
CPU time 1554.46 seconds
Started Jul 25 05:30:14 PM PDT 24
Finished Jul 25 05:56:09 PM PDT 24
Peak memory 288500 kb
Host smart-7219020d-7149-450d-a903-1b173ceb0e85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836648728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.836648728
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.1376441392
Short name T533
Test name
Test status
Simulation time 109415768828 ps
CPU time 1974.27 seconds
Started Jul 25 05:30:26 PM PDT 24
Finished Jul 25 06:03:20 PM PDT 24
Peak memory 284848 kb
Host smart-d861820a-8991-4ca7-a8c2-5c4fc551bce6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376441392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.1376441392
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2456257205
Short name T312
Test name
Test status
Simulation time 7650984687 ps
CPU time 317.62 seconds
Started Jul 25 05:30:16 PM PDT 24
Finished Jul 25 05:35:33 PM PDT 24
Peak memory 248924 kb
Host smart-b17a35ba-4dc5-45f6-a51d-5a6cddb4d932
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456257205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2456257205
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.943712111
Short name T419
Test name
Test status
Simulation time 100687833 ps
CPU time 14.05 seconds
Started Jul 25 05:29:59 PM PDT 24
Finished Jul 25 05:30:13 PM PDT 24
Peak memory 248748 kb
Host smart-3c8223a6-945f-4d76-a2d0-ed317b6b8d8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94371
2111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.943712111
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2464779989
Short name T437
Test name
Test status
Simulation time 1997765198 ps
CPU time 63.55 seconds
Started Jul 25 05:29:59 PM PDT 24
Finished Jul 25 05:31:02 PM PDT 24
Peak memory 248324 kb
Host smart-2143caa5-2a16-4dcc-bb97-5d976e662f87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24647
79989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2464779989
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.485814785
Short name T489
Test name
Test status
Simulation time 339697464 ps
CPU time 21.12 seconds
Started Jul 25 05:30:14 PM PDT 24
Finished Jul 25 05:30:36 PM PDT 24
Peak memory 248820 kb
Host smart-e65348ac-a002-4048-b06a-0f4270f8f4a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48581
4785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.485814785
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3237687694
Short name T367
Test name
Test status
Simulation time 557934925 ps
CPU time 42.28 seconds
Started Jul 25 05:29:48 PM PDT 24
Finished Jul 25 05:30:30 PM PDT 24
Peak memory 257020 kb
Host smart-b839d8a4-1032-4ef6-a62a-8488029f00ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32376
87694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3237687694
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.2059446647
Short name T48
Test name
Test status
Simulation time 18387409929 ps
CPU time 1671.44 seconds
Started Jul 25 05:30:25 PM PDT 24
Finished Jul 25 05:58:17 PM PDT 24
Peak memory 289564 kb
Host smart-60d9d4d1-3a7a-4bab-8003-dedb01e52e3f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059446647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.2059446647
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3341775170
Short name T227
Test name
Test status
Simulation time 17559440999 ps
CPU time 1211.68 seconds
Started Jul 25 05:30:35 PM PDT 24
Finished Jul 25 05:50:47 PM PDT 24
Peak memory 283924 kb
Host smart-8cffb8dc-8b9c-4663-9583-12f14484d248
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341775170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3341775170
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.315416875
Short name T261
Test name
Test status
Simulation time 4015737645 ps
CPU time 267.3 seconds
Started Jul 25 05:30:35 PM PDT 24
Finished Jul 25 05:35:02 PM PDT 24
Peak memory 256584 kb
Host smart-a38fb050-e10b-4399-929d-93413ae37a18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31541
6875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.315416875
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1484970885
Short name T702
Test name
Test status
Simulation time 1307904774 ps
CPU time 29.34 seconds
Started Jul 25 05:30:25 PM PDT 24
Finished Jul 25 05:30:55 PM PDT 24
Peak memory 256920 kb
Host smart-9c164e37-8cd9-449e-98f9-aede8e8708fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14849
70885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1484970885
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.871889656
Short name T17
Test name
Test status
Simulation time 71991736894 ps
CPU time 1200.07 seconds
Started Jul 25 05:30:33 PM PDT 24
Finished Jul 25 05:50:34 PM PDT 24
Peak memory 273384 kb
Host smart-6f133206-db60-4986-a8b9-88e75922dcc3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=871889656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.871889656
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.3252117097
Short name T392
Test name
Test status
Simulation time 53920542388 ps
CPU time 1784.83 seconds
Started Jul 25 05:30:35 PM PDT 24
Finished Jul 25 06:00:20 PM PDT 24
Peak memory 284012 kb
Host smart-ba6c1a80-735f-4c54-9605-d2227a064c40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252117097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.3252117097
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1587791272
Short name T607
Test name
Test status
Simulation time 10966629550 ps
CPU time 116.21 seconds
Started Jul 25 05:30:35 PM PDT 24
Finished Jul 25 05:32:32 PM PDT 24
Peak memory 255588 kb
Host smart-0de97200-eb6e-4b9b-a68f-54a67f237562
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587791272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1587791272
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2892957699
Short name T565
Test name
Test status
Simulation time 1485599237 ps
CPU time 31.68 seconds
Started Jul 25 05:30:25 PM PDT 24
Finished Jul 25 05:30:57 PM PDT 24
Peak memory 256472 kb
Host smart-5c572486-37f6-43ec-a4e7-d4ea7dd20ac3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28929
57699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2892957699
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.4287324975
Short name T74
Test name
Test status
Simulation time 90180078 ps
CPU time 4.67 seconds
Started Jul 25 05:30:26 PM PDT 24
Finished Jul 25 05:30:31 PM PDT 24
Peak memory 240160 kb
Host smart-0e107ca0-ba2c-4825-b525-0a6906dd379c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42873
24975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.4287324975
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1680802425
Short name T250
Test name
Test status
Simulation time 871542547 ps
CPU time 20.58 seconds
Started Jul 25 05:30:33 PM PDT 24
Finished Jul 25 05:30:54 PM PDT 24
Peak memory 248864 kb
Host smart-aaa1da7d-97dd-451e-b665-d018bb05f638
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16808
02425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1680802425
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.3266224596
Short name T407
Test name
Test status
Simulation time 2575341980 ps
CPU time 75.63 seconds
Started Jul 25 05:30:23 PM PDT 24
Finished Jul 25 05:31:39 PM PDT 24
Peak memory 257104 kb
Host smart-41bde609-9edb-46aa-ba08-9000f6439bfb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32662
24596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.3266224596
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.4055172800
Short name T664
Test name
Test status
Simulation time 15634810405 ps
CPU time 1711.68 seconds
Started Jul 25 05:30:33 PM PDT 24
Finished Jul 25 05:59:05 PM PDT 24
Peak memory 298024 kb
Host smart-603c402f-c63b-4840-913a-eb0683e4f6e2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055172800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.4055172800
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.1223342493
Short name T633
Test name
Test status
Simulation time 199048299839 ps
CPU time 4402.84 seconds
Started Jul 25 05:30:32 PM PDT 24
Finished Jul 25 06:43:55 PM PDT 24
Peak memory 297972 kb
Host smart-b1a9c1dc-2de9-4a77-a139-62900078e046
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223342493 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.1223342493
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.454691381
Short name T57
Test name
Test status
Simulation time 28474561223 ps
CPU time 1649.66 seconds
Started Jul 25 05:30:43 PM PDT 24
Finished Jul 25 05:58:13 PM PDT 24
Peak memory 270432 kb
Host smart-b4613aa8-d4da-4bcc-99ef-1340760b81bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454691381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.454691381
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.2576297699
Short name T449
Test name
Test status
Simulation time 33217681858 ps
CPU time 165.06 seconds
Started Jul 25 05:30:43 PM PDT 24
Finished Jul 25 05:33:29 PM PDT 24
Peak memory 257024 kb
Host smart-aeed5310-515d-441e-881a-749429b659b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25762
97699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.2576297699
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2058402118
Short name T394
Test name
Test status
Simulation time 2582803416 ps
CPU time 37.15 seconds
Started Jul 25 05:30:34 PM PDT 24
Finished Jul 25 05:31:11 PM PDT 24
Peak memory 248932 kb
Host smart-1414f906-f0fa-4598-abaa-2ab07609cf7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20584
02118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2058402118
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.2671264359
Short name T534
Test name
Test status
Simulation time 200491476376 ps
CPU time 1429.48 seconds
Started Jul 25 05:30:42 PM PDT 24
Finished Jul 25 05:54:31 PM PDT 24
Peak memory 287160 kb
Host smart-b007ff74-2441-486f-8f07-2f07445bedc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671264359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.2671264359
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.1792551424
Short name T262
Test name
Test status
Simulation time 41666038146 ps
CPU time 2380.9 seconds
Started Jul 25 05:30:54 PM PDT 24
Finished Jul 25 06:10:35 PM PDT 24
Peak memory 289608 kb
Host smart-4b6e2b89-ee89-45e0-86e4-63df0942cf45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792551424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.1792551424
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.1519886817
Short name T88
Test name
Test status
Simulation time 16391712904 ps
CPU time 653.35 seconds
Started Jul 25 05:30:46 PM PDT 24
Finished Jul 25 05:41:40 PM PDT 24
Peak memory 248960 kb
Host smart-24f907e8-8846-43ff-82cc-b34809a276ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519886817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1519886817
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2588347431
Short name T679
Test name
Test status
Simulation time 10834115132 ps
CPU time 51.17 seconds
Started Jul 25 05:30:35 PM PDT 24
Finished Jul 25 05:31:26 PM PDT 24
Peak memory 257064 kb
Host smart-48a3718b-6457-4b96-bbb9-f44369252a33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25883
47431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2588347431
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.915051717
Short name T268
Test name
Test status
Simulation time 1105170091 ps
CPU time 50.92 seconds
Started Jul 25 05:30:35 PM PDT 24
Finished Jul 25 05:31:26 PM PDT 24
Peak memory 256320 kb
Host smart-017670cf-0d1a-4f71-87b0-76a79178e2b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91505
1717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.915051717
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.2788731978
Short name T545
Test name
Test status
Simulation time 4171176032 ps
CPU time 60.96 seconds
Started Jul 25 05:30:46 PM PDT 24
Finished Jul 25 05:31:47 PM PDT 24
Peak memory 256640 kb
Host smart-600a56c4-f20f-43de-b720-c64c450abab1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27887
31978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.2788731978
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2645814744
Short name T588
Test name
Test status
Simulation time 918744969 ps
CPU time 54.95 seconds
Started Jul 25 05:30:39 PM PDT 24
Finished Jul 25 05:31:34 PM PDT 24
Peak memory 256016 kb
Host smart-a2265e73-4720-45aa-90e1-73a4469d81e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26458
14744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2645814744
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.848633323
Short name T284
Test name
Test status
Simulation time 29820692657 ps
CPU time 2226.68 seconds
Started Jul 25 05:31:05 PM PDT 24
Finished Jul 25 06:08:12 PM PDT 24
Peak memory 289656 kb
Host smart-5b2b8247-1165-41b3-b776-44a1841c6d29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848633323 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.848633323
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.3765047524
Short name T99
Test name
Test status
Simulation time 86745777077 ps
CPU time 2691.4 seconds
Started Jul 25 05:31:11 PM PDT 24
Finished Jul 25 06:16:03 PM PDT 24
Peak memory 281564 kb
Host smart-883442b6-0d81-4d82-bef5-a1cf981b6526
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765047524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.3765047524
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.114893130
Short name T618
Test name
Test status
Simulation time 1915214735 ps
CPU time 121.15 seconds
Started Jul 25 05:31:12 PM PDT 24
Finished Jul 25 05:33:13 PM PDT 24
Peak memory 257076 kb
Host smart-412e9b3b-683f-4f5b-bfa8-a748dd0c7696
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11489
3130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.114893130
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.4153625883
Short name T238
Test name
Test status
Simulation time 671110989 ps
CPU time 43.91 seconds
Started Jul 25 05:31:11 PM PDT 24
Finished Jul 25 05:31:55 PM PDT 24
Peak memory 256708 kb
Host smart-80aaa94c-af3b-4c30-a1a9-156d579e5e92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41536
25883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.4153625883
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3231854493
Short name T333
Test name
Test status
Simulation time 320352344238 ps
CPU time 2006.83 seconds
Started Jul 25 05:31:12 PM PDT 24
Finished Jul 25 06:04:39 PM PDT 24
Peak memory 282020 kb
Host smart-989bab43-1ab6-45fc-bb4b-ed460904948c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231854493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3231854493
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1339274905
Short name T553
Test name
Test status
Simulation time 33117504310 ps
CPU time 2062.4 seconds
Started Jul 25 05:31:21 PM PDT 24
Finished Jul 25 06:05:44 PM PDT 24
Peak memory 289140 kb
Host smart-cb3b74d6-4f88-4fe4-903a-d74a96c13b95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339274905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1339274905
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.987916535
Short name T294
Test name
Test status
Simulation time 9902376142 ps
CPU time 428.88 seconds
Started Jul 25 05:31:10 PM PDT 24
Finished Jul 25 05:38:19 PM PDT 24
Peak memory 248900 kb
Host smart-20fcb2b6-6a7c-45e7-af40-72283355cdfe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=987916535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.987916535
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.2487436376
Short name T389
Test name
Test status
Simulation time 399480502 ps
CPU time 17.84 seconds
Started Jul 25 05:31:11 PM PDT 24
Finished Jul 25 05:31:29 PM PDT 24
Peak memory 256168 kb
Host smart-5a45ea10-7a03-408b-84fb-cab2e0e38df6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24874
36376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2487436376
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2100184762
Short name T497
Test name
Test status
Simulation time 180473902 ps
CPU time 24.09 seconds
Started Jul 25 05:31:11 PM PDT 24
Finished Jul 25 05:31:35 PM PDT 24
Peak memory 248224 kb
Host smart-7ec7bd28-daa6-4f1b-9fb2-9bdcdffaecbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21001
84762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2100184762
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.544201375
Short name T647
Test name
Test status
Simulation time 1122235475 ps
CPU time 71.48 seconds
Started Jul 25 05:33:57 PM PDT 24
Finished Jul 25 05:35:09 PM PDT 24
Peak memory 256064 kb
Host smart-0c5cca58-8ac6-4e6e-8fd4-00c71ec4e0e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54420
1375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.544201375
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2482444963
Short name T525
Test name
Test status
Simulation time 380000257 ps
CPU time 30.82 seconds
Started Jul 25 05:31:05 PM PDT 24
Finished Jul 25 05:31:36 PM PDT 24
Peak memory 256092 kb
Host smart-bd05afcb-6cfe-4bf1-8085-e791dd042eb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24824
44963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2482444963
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3855100112
Short name T557
Test name
Test status
Simulation time 52568539934 ps
CPU time 1861.64 seconds
Started Jul 25 05:31:21 PM PDT 24
Finished Jul 25 06:02:22 PM PDT 24
Peak memory 284804 kb
Host smart-ed595bd5-96b1-4047-a014-b73cb3080657
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855100112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3855100112
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.2202003249
Short name T237
Test name
Test status
Simulation time 41600059726 ps
CPU time 4416.57 seconds
Started Jul 25 05:31:21 PM PDT 24
Finished Jul 25 06:44:58 PM PDT 24
Peak memory 330940 kb
Host smart-16af8b9c-1ac6-4256-afe9-cf83c9d9354b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202003249 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.2202003249
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2802248469
Short name T674
Test name
Test status
Simulation time 35583234394 ps
CPU time 1013.59 seconds
Started Jul 25 05:31:46 PM PDT 24
Finished Jul 25 05:48:40 PM PDT 24
Peak memory 270444 kb
Host smart-7a189e86-461b-4b15-bdd8-a9ed23a1049c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802248469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2802248469
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.2044855318
Short name T487
Test name
Test status
Simulation time 2911343605 ps
CPU time 118.64 seconds
Started Jul 25 05:31:46 PM PDT 24
Finished Jul 25 05:33:44 PM PDT 24
Peak memory 257140 kb
Host smart-a13452aa-10dc-4270-8899-94b2690f07d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20448
55318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2044855318
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3808761909
Short name T501
Test name
Test status
Simulation time 1176114757 ps
CPU time 29.54 seconds
Started Jul 25 05:31:35 PM PDT 24
Finished Jul 25 05:32:05 PM PDT 24
Peak memory 248392 kb
Host smart-3dda184b-8ec3-48ac-bc55-335fd42cf068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38087
61909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3808761909
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.3852305372
Short name T571
Test name
Test status
Simulation time 19319172951 ps
CPU time 1182.22 seconds
Started Jul 25 05:31:53 PM PDT 24
Finished Jul 25 05:51:36 PM PDT 24
Peak memory 272896 kb
Host smart-cfd0cfbd-abb6-44c7-96ab-b96fd18dc172
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852305372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.3852305372
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.4161063018
Short name T297
Test name
Test status
Simulation time 15271347115 ps
CPU time 332.61 seconds
Started Jul 25 05:31:48 PM PDT 24
Finished Jul 25 05:37:20 PM PDT 24
Peak memory 248748 kb
Host smart-10157744-7247-4bcf-af81-ade18a5d0744
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161063018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.4161063018
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.454717716
Short name T507
Test name
Test status
Simulation time 1215583833 ps
CPU time 32.33 seconds
Started Jul 25 05:31:32 PM PDT 24
Finished Jul 25 05:32:05 PM PDT 24
Peak memory 256268 kb
Host smart-1a6d2ffe-ed03-4642-92c1-7cb171cfe2a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45471
7716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.454717716
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.3956754182
Short name T243
Test name
Test status
Simulation time 426436493 ps
CPU time 27.65 seconds
Started Jul 25 05:31:32 PM PDT 24
Finished Jul 25 05:32:00 PM PDT 24
Peak memory 248176 kb
Host smart-8f05d1a0-d7b4-4d53-b4b6-e2479dc6901d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39567
54182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.3956754182
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.394025380
Short name T457
Test name
Test status
Simulation time 19214270 ps
CPU time 3.22 seconds
Started Jul 25 05:31:46 PM PDT 24
Finished Jul 25 05:31:49 PM PDT 24
Peak memory 240616 kb
Host smart-9009878e-20d0-4bd3-8b6f-b23e0578c788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39402
5380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.394025380
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.36070659
Short name T529
Test name
Test status
Simulation time 193700642 ps
CPU time 19.25 seconds
Started Jul 25 05:31:22 PM PDT 24
Finished Jul 25 05:31:41 PM PDT 24
Peak memory 256484 kb
Host smart-0d7d635b-486c-409e-b93b-a3d5767562d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36070
659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.36070659
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.3658030058
Short name T108
Test name
Test status
Simulation time 73333946332 ps
CPU time 3602.71 seconds
Started Jul 25 05:31:45 PM PDT 24
Finished Jul 25 06:31:49 PM PDT 24
Peak memory 321804 kb
Host smart-4578c752-7fec-46aa-988a-049fd66fcf56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658030058 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.3658030058
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.241587493
Short name T573
Test name
Test status
Simulation time 12574585717 ps
CPU time 1218 seconds
Started Jul 25 05:32:08 PM PDT 24
Finished Jul 25 05:52:26 PM PDT 24
Peak memory 289276 kb
Host smart-47d1ded0-8248-4554-ab5d-5d8805453187
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=241587493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.241587493
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.3568257628
Short name T409
Test name
Test status
Simulation time 2738244232 ps
CPU time 61.88 seconds
Started Jul 25 05:31:55 PM PDT 24
Finished Jul 25 05:32:57 PM PDT 24
Peak memory 256628 kb
Host smart-5fa6c406-b4ac-49fa-8217-e1c1f8a0c384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35682
57628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.3568257628
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.1636568045
Short name T514
Test name
Test status
Simulation time 22030757 ps
CPU time 3.25 seconds
Started Jul 25 05:31:54 PM PDT 24
Finished Jul 25 05:31:57 PM PDT 24
Peak memory 240672 kb
Host smart-debac7b5-24b2-4846-a4a1-756d4caa0a70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16365
68045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.1636568045
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.2333398582
Short name T331
Test name
Test status
Simulation time 53337407378 ps
CPU time 1369.63 seconds
Started Jul 25 05:32:15 PM PDT 24
Finished Jul 25 05:55:05 PM PDT 24
Peak memory 283036 kb
Host smart-8b3534c0-c72b-4c00-adc2-d9b7fa85dc54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333398582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.2333398582
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.1193135630
Short name T640
Test name
Test status
Simulation time 18233260261 ps
CPU time 1156.16 seconds
Started Jul 25 05:32:17 PM PDT 24
Finished Jul 25 05:51:33 PM PDT 24
Peak memory 273072 kb
Host smart-2319262f-bbbd-4592-b699-65b285e2960c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193135630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1193135630
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1409040656
Short name T502
Test name
Test status
Simulation time 10675387518 ps
CPU time 443.1 seconds
Started Jul 25 05:32:09 PM PDT 24
Finished Jul 25 05:39:32 PM PDT 24
Peak memory 248928 kb
Host smart-385d2344-7890-4cb4-891e-baf655cf0f15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409040656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1409040656
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.1277610200
Short name T421
Test name
Test status
Simulation time 196252957 ps
CPU time 14.05 seconds
Started Jul 25 05:31:57 PM PDT 24
Finished Jul 25 05:32:11 PM PDT 24
Peak memory 248868 kb
Host smart-c8e449c6-2e77-4d59-914c-ebecd0f1f35c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12776
10200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.1277610200
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.3710529755
Short name T283
Test name
Test status
Simulation time 2200915556 ps
CPU time 36.8 seconds
Started Jul 25 05:31:55 PM PDT 24
Finished Jul 25 05:32:32 PM PDT 24
Peak memory 256656 kb
Host smart-521e3bdb-428b-42dd-acdf-f8ddde3ca2f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37105
29755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.3710529755
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.2963368115
Short name T397
Test name
Test status
Simulation time 2973401023 ps
CPU time 49.42 seconds
Started Jul 25 05:32:08 PM PDT 24
Finished Jul 25 05:32:57 PM PDT 24
Peak memory 248664 kb
Host smart-6d7cfdde-f75a-46d3-80b6-c0c5ee47a732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29633
68115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2963368115
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.4207717126
Short name T504
Test name
Test status
Simulation time 540539125 ps
CPU time 11.7 seconds
Started Jul 25 05:31:54 PM PDT 24
Finished Jul 25 05:32:06 PM PDT 24
Peak memory 253712 kb
Host smart-bb53d3af-a0f2-4547-a9fb-a4e484137c6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42077
17126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.4207717126
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.932842549
Short name T541
Test name
Test status
Simulation time 163997462410 ps
CPU time 2536.53 seconds
Started Jul 25 05:32:15 PM PDT 24
Finished Jul 25 06:14:32 PM PDT 24
Peak memory 281660 kb
Host smart-3dd12f2a-4299-4c21-b10f-e8bca3f3c192
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932842549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_han
dler_stress_all.932842549
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.2854409104
Short name T109
Test name
Test status
Simulation time 515239172261 ps
CPU time 9508.99 seconds
Started Jul 25 05:32:18 PM PDT 24
Finished Jul 25 08:10:49 PM PDT 24
Peak memory 354552 kb
Host smart-c60b55c5-ecd4-40c7-9406-215ad2cf944e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854409104 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.2854409104
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.1071963431
Short name T510
Test name
Test status
Simulation time 6647771603 ps
CPU time 807.25 seconds
Started Jul 25 05:32:30 PM PDT 24
Finished Jul 25 05:45:57 PM PDT 24
Peak memory 273340 kb
Host smart-447ee179-5fcb-4e5c-9dad-a43b7cf871d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071963431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.1071963431
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1171606696
Short name T585
Test name
Test status
Simulation time 4525837420 ps
CPU time 73.95 seconds
Started Jul 25 05:32:30 PM PDT 24
Finished Jul 25 05:33:44 PM PDT 24
Peak memory 256484 kb
Host smart-1a82968f-7a2e-45d6-8234-683a1b3d3d29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11716
06696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1171606696
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2696032239
Short name T494
Test name
Test status
Simulation time 264494200 ps
CPU time 24.26 seconds
Started Jul 25 05:32:15 PM PDT 24
Finished Jul 25 05:32:40 PM PDT 24
Peak memory 248820 kb
Host smart-ec9de265-bf71-45d8-9ae7-bce54c08f133
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26960
32239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2696032239
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.1827178798
Short name T332
Test name
Test status
Simulation time 42830253845 ps
CPU time 1264.37 seconds
Started Jul 25 05:32:31 PM PDT 24
Finished Jul 25 05:53:35 PM PDT 24
Peak memory 272868 kb
Host smart-7efe1e10-1ef1-4009-8f28-cf51a1a0a4a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827178798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.1827178798
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.339075653
Short name T65
Test name
Test status
Simulation time 11627903730 ps
CPU time 1133.46 seconds
Started Jul 25 05:32:38 PM PDT 24
Finished Jul 25 05:51:32 PM PDT 24
Peak memory 272936 kb
Host smart-c87cf16a-72fe-483d-a98e-ae1b1235286e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339075653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.339075653
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2384762020
Short name T289
Test name
Test status
Simulation time 23702443734 ps
CPU time 559.83 seconds
Started Jul 25 05:32:30 PM PDT 24
Finished Jul 25 05:41:50 PM PDT 24
Peak memory 247824 kb
Host smart-a0a1b08a-401d-46da-9bae-95845174a78f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384762020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2384762020
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.1515175057
Short name T598
Test name
Test status
Simulation time 5188990800 ps
CPU time 66.23 seconds
Started Jul 25 05:32:18 PM PDT 24
Finished Jul 25 05:33:25 PM PDT 24
Peak memory 256308 kb
Host smart-cea2d83a-76b1-40a3-950d-b6e9d9b4700e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15151
75057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1515175057
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2331523590
Short name T680
Test name
Test status
Simulation time 1329343733 ps
CPU time 44.19 seconds
Started Jul 25 05:32:15 PM PDT 24
Finished Jul 25 05:33:00 PM PDT 24
Peak memory 248160 kb
Host smart-120cc155-6cd3-4b66-b55a-8bdbaf2894d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23315
23590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2331523590
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1921075377
Short name T75
Test name
Test status
Simulation time 847721746 ps
CPU time 23.97 seconds
Started Jul 25 05:32:32 PM PDT 24
Finished Jul 25 05:32:56 PM PDT 24
Peak memory 256340 kb
Host smart-449bc90f-5c0c-46b3-838a-6d4f04b5c3d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19210
75377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1921075377
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.1512633763
Short name T440
Test name
Test status
Simulation time 3068886485 ps
CPU time 58.54 seconds
Started Jul 25 05:32:14 PM PDT 24
Finished Jul 25 05:33:13 PM PDT 24
Peak memory 257088 kb
Host smart-10e71991-d265-490d-8846-d9f56374764a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15126
33763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.1512633763
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.477972759
Short name T711
Test name
Test status
Simulation time 47316025754 ps
CPU time 2845.19 seconds
Started Jul 25 05:32:39 PM PDT 24
Finished Jul 25 06:20:04 PM PDT 24
Peak memory 289424 kb
Host smart-fcf0bd89-2e85-4893-8344-4c407c8fb4f3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477972759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han
dler_stress_all.477972759
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1078161417
Short name T474
Test name
Test status
Simulation time 21549065348 ps
CPU time 562.09 seconds
Started Jul 25 05:32:52 PM PDT 24
Finished Jul 25 05:42:14 PM PDT 24
Peak memory 273336 kb
Host smart-205495e8-2cb7-423c-9001-4cc1e07d84d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078161417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1078161417
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.3549380552
Short name T676
Test name
Test status
Simulation time 1834280919 ps
CPU time 161.11 seconds
Started Jul 25 05:32:47 PM PDT 24
Finished Jul 25 05:35:29 PM PDT 24
Peak memory 257084 kb
Host smart-f6cba47e-a1b8-4a5e-bc09-c38365a7ef93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35493
80552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.3549380552
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.2573022109
Short name T31
Test name
Test status
Simulation time 571496437 ps
CPU time 31.68 seconds
Started Jul 25 05:32:47 PM PDT 24
Finished Jul 25 05:33:19 PM PDT 24
Peak memory 256776 kb
Host smart-3ac2fa4e-a956-4a08-9728-5699a0eaad63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25730
22109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.2573022109
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.1706736924
Short name T668
Test name
Test status
Simulation time 18760310991 ps
CPU time 1497.03 seconds
Started Jul 25 05:32:47 PM PDT 24
Finished Jul 25 05:57:45 PM PDT 24
Peak memory 281624 kb
Host smart-5d1e36c6-fcb2-445b-824f-a504803d6b26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706736924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1706736924
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.4219542941
Short name T600
Test name
Test status
Simulation time 77355417947 ps
CPU time 2563.18 seconds
Started Jul 25 05:32:51 PM PDT 24
Finished Jul 25 06:15:35 PM PDT 24
Peak memory 289608 kb
Host smart-00dc4a16-490b-4ff7-9927-7d24bac18528
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219542941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.4219542941
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.635533304
Short name T292
Test name
Test status
Simulation time 2756455764 ps
CPU time 112.89 seconds
Started Jul 25 05:32:49 PM PDT 24
Finished Jul 25 05:34:42 PM PDT 24
Peak memory 248924 kb
Host smart-e16c816c-ebd6-446e-b072-30558439ae6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635533304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.635533304
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.208759330
Short name T470
Test name
Test status
Simulation time 1117275501 ps
CPU time 18.65 seconds
Started Jul 25 05:32:38 PM PDT 24
Finished Jul 25 05:32:57 PM PDT 24
Peak memory 248772 kb
Host smart-4da2691a-e39a-401a-b226-74d6d4543b6b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20875
9330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.208759330
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.874501097
Short name T79
Test name
Test status
Simulation time 234100475 ps
CPU time 36.48 seconds
Started Jul 25 05:32:48 PM PDT 24
Finished Jul 25 05:33:25 PM PDT 24
Peak memory 248720 kb
Host smart-6054a96a-faa1-4bad-a10f-9f3ff3f566d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87450
1097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.874501097
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.599361452
Short name T567
Test name
Test status
Simulation time 247589280 ps
CPU time 6.59 seconds
Started Jul 25 05:32:40 PM PDT 24
Finished Jul 25 05:32:46 PM PDT 24
Peak memory 254880 kb
Host smart-efb4361d-65a2-4e7f-8e4e-7a6ba4dbee50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59936
1452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.599361452
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2045083585
Short name T68
Test name
Test status
Simulation time 78953051539 ps
CPU time 1438.48 seconds
Started Jul 25 05:32:48 PM PDT 24
Finished Jul 25 05:56:47 PM PDT 24
Peak memory 289200 kb
Host smart-81aa0e8b-8a46-405a-a9f1-c049a7b0b0d3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045083585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2045083585
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.2171533761
Short name T30
Test name
Test status
Simulation time 46952856254 ps
CPU time 724.81 seconds
Started Jul 25 05:35:00 PM PDT 24
Finished Jul 25 05:47:05 PM PDT 24
Peak memory 270364 kb
Host smart-baede402-011f-45db-9e16-170720fa3620
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171533761 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.2171533761
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3224041344
Short name T562
Test name
Test status
Simulation time 2444192368 ps
CPU time 37.26 seconds
Started Jul 25 05:32:56 PM PDT 24
Finished Jul 25 05:33:33 PM PDT 24
Peak memory 256416 kb
Host smart-841f64e5-646a-47b6-9949-f5ec1cd5f4ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32240
41344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3224041344
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.1150411918
Short name T542
Test name
Test status
Simulation time 525832953 ps
CPU time 19.28 seconds
Started Jul 25 05:32:57 PM PDT 24
Finished Jul 25 05:33:16 PM PDT 24
Peak memory 257108 kb
Host smart-dc4814dc-718d-402c-ae9f-8c8fb3c466c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11504
11918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1150411918
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.2641727499
Short name T329
Test name
Test status
Simulation time 212496049086 ps
CPU time 1432.3 seconds
Started Jul 25 05:33:12 PM PDT 24
Finished Jul 25 05:57:04 PM PDT 24
Peak memory 288984 kb
Host smart-eb429918-ceec-447e-90fe-809669e1c9b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641727499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2641727499
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.236867365
Short name T564
Test name
Test status
Simulation time 8987771384 ps
CPU time 974.99 seconds
Started Jul 25 05:33:11 PM PDT 24
Finished Jul 25 05:49:26 PM PDT 24
Peak memory 273448 kb
Host smart-b7783bee-d0f6-4d1d-8b51-f95cc8eef12c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236867365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.236867365
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.287062286
Short name T307
Test name
Test status
Simulation time 10894081801 ps
CPU time 470.03 seconds
Started Jul 25 05:33:02 PM PDT 24
Finished Jul 25 05:40:53 PM PDT 24
Peak memory 247736 kb
Host smart-db810abd-c6fe-463a-8bd8-f670a86c5f4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287062286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.287062286
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.4111734623
Short name T410
Test name
Test status
Simulation time 720983892 ps
CPU time 26.45 seconds
Started Jul 25 05:32:54 PM PDT 24
Finished Jul 25 05:33:21 PM PDT 24
Peak memory 255348 kb
Host smart-acd1fa04-2e90-4ddb-ad26-32eb71a6f038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41117
34623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.4111734623
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.3517387067
Short name T506
Test name
Test status
Simulation time 56334896 ps
CPU time 8.2 seconds
Started Jul 25 05:32:56 PM PDT 24
Finished Jul 25 05:33:04 PM PDT 24
Peak memory 248256 kb
Host smart-13fe186d-2bf7-48ec-9eee-3ad1afb39350
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35173
87067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.3517387067
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.3750913324
Short name T672
Test name
Test status
Simulation time 1073685225 ps
CPU time 37.34 seconds
Started Jul 25 05:32:55 PM PDT 24
Finished Jul 25 05:33:33 PM PDT 24
Peak memory 256972 kb
Host smart-f2e5e3c3-b5bd-4813-bd15-46515003858c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37509
13324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.3750913324
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.4254866949
Short name T114
Test name
Test status
Simulation time 36227855901 ps
CPU time 1278.32 seconds
Started Jul 25 05:33:12 PM PDT 24
Finished Jul 25 05:54:30 PM PDT 24
Peak memory 273520 kb
Host smart-7b00da7b-16bb-4454-93b0-d61b6f2bf791
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254866949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.4254866949
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.4248893492
Short name T101
Test name
Test status
Simulation time 203765398567 ps
CPU time 1831.18 seconds
Started Jul 25 05:33:31 PM PDT 24
Finished Jul 25 06:04:02 PM PDT 24
Peak memory 273480 kb
Host smart-8ddc8a72-0640-4654-95ee-409a82b54e01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248893492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.4248893492
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1024217425
Short name T176
Test name
Test status
Simulation time 13079036570 ps
CPU time 197.58 seconds
Started Jul 25 05:33:26 PM PDT 24
Finished Jul 25 05:36:44 PM PDT 24
Peak memory 251088 kb
Host smart-7603d331-3cae-4ba8-98d4-a4178fea3d24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10242
17425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1024217425
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.2091309887
Short name T556
Test name
Test status
Simulation time 376768643 ps
CPU time 27.84 seconds
Started Jul 25 05:33:26 PM PDT 24
Finished Jul 25 05:33:54 PM PDT 24
Peak memory 248892 kb
Host smart-5cf23fda-3fc6-4c5c-a16a-44728168341f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20913
09887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.2091309887
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.3186950888
Short name T699
Test name
Test status
Simulation time 10030117993 ps
CPU time 1025.17 seconds
Started Jul 25 05:33:41 PM PDT 24
Finished Jul 25 05:50:46 PM PDT 24
Peak memory 273096 kb
Host smart-2f2774d4-b2e3-4076-b8c5-a4a292fa6c9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186950888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3186950888
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.2288741942
Short name T295
Test name
Test status
Simulation time 7986930875 ps
CPU time 154.41 seconds
Started Jul 25 05:33:32 PM PDT 24
Finished Jul 25 05:36:07 PM PDT 24
Peak memory 248676 kb
Host smart-8a296d08-de1d-4e10-a525-ee8b5f1246b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288741942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.2288741942
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.3075342736
Short name T86
Test name
Test status
Simulation time 37653516 ps
CPU time 5.96 seconds
Started Jul 25 05:33:17 PM PDT 24
Finished Jul 25 05:33:23 PM PDT 24
Peak memory 248868 kb
Host smart-0bc3b654-2c53-4611-bda3-08f5f55f929c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30753
42736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.3075342736
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.3695582842
Short name T538
Test name
Test status
Simulation time 1339202125 ps
CPU time 41.69 seconds
Started Jul 25 05:33:20 PM PDT 24
Finished Jul 25 05:34:02 PM PDT 24
Peak memory 256260 kb
Host smart-077cc732-18a9-4958-bb7c-fda8b55354a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36955
82842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.3695582842
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.4185328273
Short name T656
Test name
Test status
Simulation time 797059281 ps
CPU time 58.49 seconds
Started Jul 25 05:33:27 PM PDT 24
Finished Jul 25 05:34:25 PM PDT 24
Peak memory 248908 kb
Host smart-b430e46b-30ab-4551-877a-153e020f4da1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41853
28273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.4185328273
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.3902018424
Short name T540
Test name
Test status
Simulation time 626275234 ps
CPU time 10.24 seconds
Started Jul 25 05:33:17 PM PDT 24
Finished Jul 25 05:33:28 PM PDT 24
Peak memory 252660 kb
Host smart-731070aa-75f7-425b-84b1-b77aec409e4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39020
18424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.3902018424
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2666707787
Short name T698
Test name
Test status
Simulation time 1633210020 ps
CPU time 104.82 seconds
Started Jul 25 05:33:40 PM PDT 24
Finished Jul 25 05:35:25 PM PDT 24
Peak memory 257004 kb
Host smart-5455ab7e-7b01-4d76-ac92-0904a13accf2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666707787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2666707787
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1505425918
Short name T195
Test name
Test status
Simulation time 39203815 ps
CPU time 4.41 seconds
Started Jul 25 05:22:32 PM PDT 24
Finished Jul 25 05:22:37 PM PDT 24
Peak memory 249092 kb
Host smart-bef0a5f0-005c-4d97-acef-fda06074ad31
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1505425918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1505425918
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.1233188052
Short name T6
Test name
Test status
Simulation time 30317195078 ps
CPU time 1211.1 seconds
Started Jul 25 05:22:23 PM PDT 24
Finished Jul 25 05:42:34 PM PDT 24
Peak memory 289248 kb
Host smart-108cc5c8-2a74-4cea-8a6c-9f6b6d3f38e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233188052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1233188052
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.1069329340
Short name T524
Test name
Test status
Simulation time 857884220 ps
CPU time 39.1 seconds
Started Jul 25 05:22:30 PM PDT 24
Finished Jul 25 05:23:10 PM PDT 24
Peak memory 248812 kb
Host smart-d5458868-290e-43cb-b901-5ec2b8da6dea
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1069329340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.1069329340
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1029029461
Short name T484
Test name
Test status
Simulation time 1250923657 ps
CPU time 62.03 seconds
Started Jul 25 05:22:23 PM PDT 24
Finished Jul 25 05:23:25 PM PDT 24
Peak memory 256728 kb
Host smart-ae803de1-d80c-4ef7-9d37-aba10e3a8d60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10290
29461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1029029461
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3963264499
Short name T24
Test name
Test status
Simulation time 1755536583 ps
CPU time 66.32 seconds
Started Jul 25 05:22:16 PM PDT 24
Finished Jul 25 05:23:22 PM PDT 24
Peak memory 248424 kb
Host smart-749507d5-6c9e-4ca2-85e8-0e52a88f7fb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39632
64499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3963264499
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.2793423129
Short name T316
Test name
Test status
Simulation time 18430900086 ps
CPU time 1422.65 seconds
Started Jul 25 05:22:23 PM PDT 24
Finished Jul 25 05:46:06 PM PDT 24
Peak memory 284768 kb
Host smart-fb1eb934-c641-433f-97a2-68af6db6a14c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793423129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.2793423129
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.3805557110
Short name T258
Test name
Test status
Simulation time 33021934480 ps
CPU time 2003.26 seconds
Started Jul 25 05:22:26 PM PDT 24
Finished Jul 25 05:55:50 PM PDT 24
Peak memory 282872 kb
Host smart-cbc1301f-0f1d-4f09-8d18-de79b70035f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805557110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3805557110
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.3975877663
Short name T317
Test name
Test status
Simulation time 3946920564 ps
CPU time 168.91 seconds
Started Jul 25 05:22:27 PM PDT 24
Finished Jul 25 05:25:16 PM PDT 24
Peak memory 248948 kb
Host smart-3cb790e5-5880-48c2-a03f-e373170628e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975877663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.3975877663
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1166384417
Short name T49
Test name
Test status
Simulation time 460274211 ps
CPU time 27.77 seconds
Started Jul 25 05:22:16 PM PDT 24
Finished Jul 25 05:22:44 PM PDT 24
Peak memory 248908 kb
Host smart-b142d495-e6f6-4449-a31d-96a822a70bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11663
84417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1166384417
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.4228738124
Short name T414
Test name
Test status
Simulation time 1036250251 ps
CPU time 22.73 seconds
Started Jul 25 05:22:15 PM PDT 24
Finished Jul 25 05:22:37 PM PDT 24
Peak memory 248112 kb
Host smart-35cfee25-cc0b-4c01-a3f9-2c62c3c82b6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42287
38124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.4228738124
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.3166613138
Short name T8
Test name
Test status
Simulation time 2434113807 ps
CPU time 11.58 seconds
Started Jul 25 05:22:31 PM PDT 24
Finished Jul 25 05:22:43 PM PDT 24
Peak memory 270876 kb
Host smart-8a28d49f-d226-408a-8eeb-014bc052e9aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3166613138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3166613138
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.993032028
Short name T416
Test name
Test status
Simulation time 747309626 ps
CPU time 20.26 seconds
Started Jul 25 05:22:24 PM PDT 24
Finished Jul 25 05:22:44 PM PDT 24
Peak memory 256392 kb
Host smart-5c3ed74b-e071-48af-baa9-9b832ba2a742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99303
2028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.993032028
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.1894597030
Short name T703
Test name
Test status
Simulation time 5933960209 ps
CPU time 47.12 seconds
Started Jul 25 05:22:15 PM PDT 24
Finished Jul 25 05:23:02 PM PDT 24
Peak memory 257064 kb
Host smart-be19d8e5-34c8-43c7-9fe0-10c8463c4a72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18945
97030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.1894597030
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.399333604
Short name T464
Test name
Test status
Simulation time 243134288 ps
CPU time 26.78 seconds
Started Jul 25 05:22:29 PM PDT 24
Finished Jul 25 05:22:56 PM PDT 24
Peak memory 248832 kb
Host smart-e803c0d5-8287-4310-baa6-e5011dbc014c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399333604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand
ler_stress_all.399333604
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3909103983
Short name T479
Test name
Test status
Simulation time 22248911007 ps
CPU time 1123.57 seconds
Started Jul 25 05:33:48 PM PDT 24
Finished Jul 25 05:52:32 PM PDT 24
Peak memory 270368 kb
Host smart-65eab7ba-4b39-45e3-bc8f-250075a9bc5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909103983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3909103983
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.2964037584
Short name T527
Test name
Test status
Simulation time 53242856602 ps
CPU time 230.24 seconds
Started Jul 25 05:33:47 PM PDT 24
Finished Jul 25 05:37:38 PM PDT 24
Peak memory 257072 kb
Host smart-e829a820-07b0-48a0-8c72-210c57878fb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29640
37584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2964037584
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.97457239
Short name T223
Test name
Test status
Simulation time 346250853 ps
CPU time 12.57 seconds
Started Jul 25 05:33:41 PM PDT 24
Finished Jul 25 05:33:54 PM PDT 24
Peak memory 254480 kb
Host smart-8422117d-4bc0-4516-b027-e9436a9b6721
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97457
239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.97457239
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.173241809
Short name T347
Test name
Test status
Simulation time 36746267825 ps
CPU time 735.24 seconds
Started Jul 25 05:33:54 PM PDT 24
Finished Jul 25 05:46:10 PM PDT 24
Peak memory 272432 kb
Host smart-ce582e73-6f8a-4976-aade-342776371a7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173241809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.173241809
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.215816641
Short name T418
Test name
Test status
Simulation time 44491674690 ps
CPU time 1822.42 seconds
Started Jul 25 05:33:56 PM PDT 24
Finished Jul 25 06:04:19 PM PDT 24
Peak memory 289692 kb
Host smart-44308584-b5b5-4826-8da6-e74cdbb38cf4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215816641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.215816641
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.4031286549
Short name T455
Test name
Test status
Simulation time 944983892 ps
CPU time 12.17 seconds
Started Jul 25 05:33:42 PM PDT 24
Finished Jul 25 05:33:54 PM PDT 24
Peak memory 248792 kb
Host smart-25f6bb0d-bcd8-4411-9b32-cc6a7ca59280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40312
86549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.4031286549
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.301210270
Short name T691
Test name
Test status
Simulation time 336531361 ps
CPU time 29.39 seconds
Started Jul 25 05:33:41 PM PDT 24
Finished Jul 25 05:34:11 PM PDT 24
Peak memory 248448 kb
Host smart-6ac936d0-cf46-4908-88cb-ff05f9d22534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30121
0270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.301210270
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3582849205
Short name T550
Test name
Test status
Simulation time 359088016 ps
CPU time 29.33 seconds
Started Jul 25 05:33:50 PM PDT 24
Finished Jul 25 05:34:19 PM PDT 24
Peak memory 248592 kb
Host smart-2d592c9a-c433-4b55-b308-e509a6692e3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35828
49205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3582849205
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.485358269
Short name T379
Test name
Test status
Simulation time 1455063948 ps
CPU time 33.07 seconds
Started Jul 25 05:33:39 PM PDT 24
Finished Jul 25 05:34:13 PM PDT 24
Peak memory 249264 kb
Host smart-c0845924-44c5-4f9e-a652-36427e733637
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48535
8269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.485358269
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.838351990
Short name T265
Test name
Test status
Simulation time 9877089777 ps
CPU time 189.88 seconds
Started Jul 25 05:33:57 PM PDT 24
Finished Jul 25 05:37:07 PM PDT 24
Peak memory 257060 kb
Host smart-fff23f36-b60c-4400-80aa-cdd5ca84273a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838351990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.838351990
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.3544375533
Short name T174
Test name
Test status
Simulation time 122234263817 ps
CPU time 3978.75 seconds
Started Jul 25 05:33:55 PM PDT 24
Finished Jul 25 06:40:14 PM PDT 24
Peak memory 288980 kb
Host smart-ab013316-c2e9-413d-8dd3-8cd7f1a3f009
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544375533 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.3544375533
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2768782485
Short name T213
Test name
Test status
Simulation time 35608395423 ps
CPU time 1495.31 seconds
Started Jul 25 05:34:04 PM PDT 24
Finished Jul 25 05:59:00 PM PDT 24
Peak memory 265220 kb
Host smart-98ffd8ba-4d66-4673-b1c2-8889e7927c37
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768782485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2768782485
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3688680126
Short name T610
Test name
Test status
Simulation time 28675557390 ps
CPU time 162.75 seconds
Started Jul 25 05:33:56 PM PDT 24
Finished Jul 25 05:36:39 PM PDT 24
Peak memory 256232 kb
Host smart-9f1f9c04-b9cf-44bd-ab16-b8a69e37785d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36886
80126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3688680126
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.1586534894
Short name T595
Test name
Test status
Simulation time 3754446932 ps
CPU time 32.68 seconds
Started Jul 25 05:33:56 PM PDT 24
Finished Jul 25 05:34:29 PM PDT 24
Peak memory 248936 kb
Host smart-b436e9b7-7d0a-4769-9355-a4309cc7e974
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15865
34894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.1586534894
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.65766252
Short name T643
Test name
Test status
Simulation time 32027295106 ps
CPU time 776.71 seconds
Started Jul 25 05:34:04 PM PDT 24
Finished Jul 25 05:47:01 PM PDT 24
Peak memory 273376 kb
Host smart-0fdd39b3-a318-4794-a0b5-9eed22d18ba5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65766252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.65766252
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.250366515
Short name T96
Test name
Test status
Simulation time 24500482102 ps
CPU time 1638.38 seconds
Started Jul 25 05:34:08 PM PDT 24
Finished Jul 25 06:01:27 PM PDT 24
Peak memory 273436 kb
Host smart-6103b7b6-0992-4567-b3f2-af1b3936eb8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250366515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.250366515
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.1032504552
Short name T313
Test name
Test status
Simulation time 10129981016 ps
CPU time 424.6 seconds
Started Jul 25 05:34:05 PM PDT 24
Finished Jul 25 05:41:09 PM PDT 24
Peak memory 248712 kb
Host smart-fad4771d-9681-4dfd-bcda-386d1c65efbd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032504552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1032504552
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1834146741
Short name T638
Test name
Test status
Simulation time 176808986 ps
CPU time 14.4 seconds
Started Jul 25 05:33:56 PM PDT 24
Finished Jul 25 05:34:10 PM PDT 24
Peak memory 248856 kb
Host smart-80f6e848-357b-4163-a591-441f6353a261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18341
46741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1834146741
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.4061392482
Short name T281
Test name
Test status
Simulation time 2203259537 ps
CPU time 36.77 seconds
Started Jul 25 05:33:54 PM PDT 24
Finished Jul 25 05:34:31 PM PDT 24
Peak memory 256100 kb
Host smart-bac62edd-053f-4853-8262-c6c6ba58b01b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40613
92482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.4061392482
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.970105015
Short name T522
Test name
Test status
Simulation time 854961332 ps
CPU time 27.79 seconds
Started Jul 25 05:33:55 PM PDT 24
Finished Jul 25 05:34:23 PM PDT 24
Peak memory 256320 kb
Host smart-6a5ea6b1-63f1-43ae-987f-2647ca8d2650
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97010
5015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.970105015
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.30773809
Short name T391
Test name
Test status
Simulation time 3288077107 ps
CPU time 62.6 seconds
Started Jul 25 05:33:56 PM PDT 24
Finished Jul 25 05:34:59 PM PDT 24
Peak memory 256104 kb
Host smart-dad79d50-9e9c-471f-8185-d41a3f2cb034
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30773
809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.30773809
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1662364211
Short name T240
Test name
Test status
Simulation time 23241646321 ps
CPU time 1286.12 seconds
Started Jul 25 05:34:08 PM PDT 24
Finished Jul 25 05:55:34 PM PDT 24
Peak memory 289212 kb
Host smart-91443ac6-3fd2-4f87-998d-5c95c23986be
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662364211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1662364211
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.3112692630
Short name T184
Test name
Test status
Simulation time 35330994025 ps
CPU time 1218.72 seconds
Started Jul 25 05:34:04 PM PDT 24
Finished Jul 25 05:54:23 PM PDT 24
Peak memory 273604 kb
Host smart-2d11447f-4d53-4c5c-94a9-8e6dcb9692ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112692630 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.3112692630
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.2284243690
Short name T381
Test name
Test status
Simulation time 120083400615 ps
CPU time 944.63 seconds
Started Jul 25 05:34:10 PM PDT 24
Finished Jul 25 05:49:55 PM PDT 24
Peak memory 273032 kb
Host smart-6d103a48-e09e-42b4-af1d-b275f7ac6bc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284243690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.2284243690
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.969229195
Short name T393
Test name
Test status
Simulation time 9498693493 ps
CPU time 103.33 seconds
Started Jul 25 05:34:12 PM PDT 24
Finished Jul 25 05:35:56 PM PDT 24
Peak memory 256320 kb
Host smart-69a4283c-ee22-4dd4-9209-81dc7e95e786
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96922
9195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.969229195
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.3422463686
Short name T661
Test name
Test status
Simulation time 128434282354 ps
CPU time 1958.32 seconds
Started Jul 25 05:34:12 PM PDT 24
Finished Jul 25 06:06:51 PM PDT 24
Peak memory 283664 kb
Host smart-b63cb3e7-4f8e-4c8c-8ab2-58f82bc671fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422463686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.3422463686
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.3893418851
Short name T435
Test name
Test status
Simulation time 55887035964 ps
CPU time 1657.98 seconds
Started Jul 25 05:34:13 PM PDT 24
Finished Jul 25 06:01:51 PM PDT 24
Peak memory 269428 kb
Host smart-86f61e0d-e7bc-4676-84a4-d7adad46b50f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893418851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3893418851
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1689268390
Short name T634
Test name
Test status
Simulation time 9271979941 ps
CPU time 187.97 seconds
Started Jul 25 05:34:14 PM PDT 24
Finished Jul 25 05:37:22 PM PDT 24
Peak memory 248952 kb
Host smart-4a57951a-fbee-401d-b829-9447f4f11a4c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689268390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1689268390
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.3165362005
Short name T430
Test name
Test status
Simulation time 561581422 ps
CPU time 17.43 seconds
Started Jul 25 05:34:04 PM PDT 24
Finished Jul 25 05:34:21 PM PDT 24
Peak memory 256212 kb
Host smart-3e1e36ea-9329-4630-943b-a0b7310dd426
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31653
62005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.3165362005
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.1499563845
Short name T584
Test name
Test status
Simulation time 489857588 ps
CPU time 29.13 seconds
Started Jul 25 05:34:05 PM PDT 24
Finished Jul 25 05:34:34 PM PDT 24
Peak memory 256572 kb
Host smart-9d48a853-86eb-47c0-837d-d5c6a5312f98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14995
63845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.1499563845
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.2122750792
Short name T675
Test name
Test status
Simulation time 621781377 ps
CPU time 45.76 seconds
Started Jul 25 05:34:10 PM PDT 24
Finished Jul 25 05:34:56 PM PDT 24
Peak memory 256448 kb
Host smart-ec245f9a-5fca-4da3-93ff-ac2492fa9632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21227
50792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.2122750792
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.627417884
Short name T532
Test name
Test status
Simulation time 4881642826 ps
CPU time 78.05 seconds
Started Jul 25 05:34:04 PM PDT 24
Finished Jul 25 05:35:22 PM PDT 24
Peak memory 256936 kb
Host smart-57853624-795e-47b2-95fd-ac4c01cc6bc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62741
7884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.627417884
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.573867119
Short name T696
Test name
Test status
Simulation time 39429316568 ps
CPU time 2706.16 seconds
Started Jul 25 05:34:23 PM PDT 24
Finished Jul 25 06:19:30 PM PDT 24
Peak memory 289904 kb
Host smart-fc88a39c-916c-4f83-b57e-dfed29389c8b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=573867119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.573867119
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.1065535736
Short name T609
Test name
Test status
Simulation time 32323263221 ps
CPU time 1884.71 seconds
Started Jul 25 05:34:21 PM PDT 24
Finished Jul 25 06:05:46 PM PDT 24
Peak memory 305692 kb
Host smart-c3219165-2834-4c82-ac49-179c0e83c251
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065535736 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.1065535736
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2662740427
Short name T528
Test name
Test status
Simulation time 62915875116 ps
CPU time 1514.97 seconds
Started Jul 25 05:34:27 PM PDT 24
Finished Jul 25 05:59:43 PM PDT 24
Peak memory 289508 kb
Host smart-2aa39b12-504a-472b-8fef-2bc9161c1706
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662740427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2662740427
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.247056931
Short name T526
Test name
Test status
Simulation time 584438116 ps
CPU time 47.86 seconds
Started Jul 25 05:34:22 PM PDT 24
Finished Jul 25 05:35:10 PM PDT 24
Peak memory 256912 kb
Host smart-13608503-13e4-4e01-b343-d6eaedbc6697
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24705
6931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.247056931
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3320480646
Short name T687
Test name
Test status
Simulation time 87261344 ps
CPU time 4.96 seconds
Started Jul 25 05:34:19 PM PDT 24
Finished Jul 25 05:34:24 PM PDT 24
Peak memory 252252 kb
Host smart-0d8a1264-5fcc-4e30-b988-49fb3f2d3054
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33204
80646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3320480646
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1388023584
Short name T576
Test name
Test status
Simulation time 78567716651 ps
CPU time 1371.48 seconds
Started Jul 25 05:34:28 PM PDT 24
Finished Jul 25 05:57:20 PM PDT 24
Peak memory 285360 kb
Host smart-1c178864-7a7d-4446-a8e4-1ee94d01bc41
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388023584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1388023584
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3894949091
Short name T578
Test name
Test status
Simulation time 20579938334 ps
CPU time 1449.27 seconds
Started Jul 25 05:34:28 PM PDT 24
Finished Jul 25 05:58:38 PM PDT 24
Peak memory 273344 kb
Host smart-d1f44b3c-f718-4667-b443-deabeaa8eaf4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894949091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3894949091
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.1780416908
Short name T636
Test name
Test status
Simulation time 13408319509 ps
CPU time 143.25 seconds
Started Jul 25 05:34:28 PM PDT 24
Finished Jul 25 05:36:52 PM PDT 24
Peak memory 248836 kb
Host smart-80c4cecd-f8ec-4ba2-8ee2-6ae7a0e7de13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780416908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.1780416908
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.460611477
Short name T462
Test name
Test status
Simulation time 5078222429 ps
CPU time 16.07 seconds
Started Jul 25 05:34:21 PM PDT 24
Finished Jul 25 05:34:37 PM PDT 24
Peak memory 248792 kb
Host smart-1740e478-b08b-4d26-bc92-5d2741d16106
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46061
1477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.460611477
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3907000047
Short name T491
Test name
Test status
Simulation time 890341553 ps
CPU time 37.85 seconds
Started Jul 25 05:34:29 PM PDT 24
Finished Jul 25 05:35:07 PM PDT 24
Peak memory 248388 kb
Host smart-efff7f9d-783d-4521-8e76-20df159c2f9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39070
00047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3907000047
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.1725063367
Short name T370
Test name
Test status
Simulation time 323379819 ps
CPU time 31.52 seconds
Started Jul 25 05:34:19 PM PDT 24
Finished Jul 25 05:34:51 PM PDT 24
Peak memory 256272 kb
Host smart-77f5354f-40fa-47da-9396-c6bf15da204e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17250
63367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.1725063367
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1034213729
Short name T388
Test name
Test status
Simulation time 11401750177 ps
CPU time 1114.56 seconds
Started Jul 25 05:34:38 PM PDT 24
Finished Jul 25 05:53:13 PM PDT 24
Peak memory 285168 kb
Host smart-9aef2295-b67a-4db5-ba21-f86da2bd92f9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034213729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1034213729
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.565483683
Short name T95
Test name
Test status
Simulation time 90609688405 ps
CPU time 3630.07 seconds
Started Jul 25 05:34:40 PM PDT 24
Finished Jul 25 06:35:10 PM PDT 24
Peak memory 338192 kb
Host smart-e027f35d-f3e4-48d1-9426-b66497795335
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565483683 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.565483683
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3160900878
Short name T456
Test name
Test status
Simulation time 48340878596 ps
CPU time 1059.44 seconds
Started Jul 25 05:34:48 PM PDT 24
Finished Jul 25 05:52:28 PM PDT 24
Peak memory 270320 kb
Host smart-b86994b2-df51-42be-9709-9f6e531d59d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160900878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3160900878
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.2258358255
Short name T372
Test name
Test status
Simulation time 896378100 ps
CPU time 97.26 seconds
Started Jul 25 05:34:39 PM PDT 24
Finished Jul 25 05:36:16 PM PDT 24
Peak memory 256636 kb
Host smart-9717f66a-a74f-4fe5-aa12-1f6625b66c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22583
58255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2258358255
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.4163554026
Short name T678
Test name
Test status
Simulation time 1448901540 ps
CPU time 31.35 seconds
Started Jul 25 05:34:40 PM PDT 24
Finished Jul 25 05:35:12 PM PDT 24
Peak memory 248816 kb
Host smart-e5e1a814-2978-4260-9f9d-0e05340762a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41635
54026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.4163554026
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.339060991
Short name T180
Test name
Test status
Simulation time 29396950402 ps
CPU time 1252.86 seconds
Started Jul 25 05:34:54 PM PDT 24
Finished Jul 25 05:55:47 PM PDT 24
Peak memory 288644 kb
Host smart-6249c806-55ec-4e15-bb4e-5c2aeb85666f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339060991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.339060991
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.4165711260
Short name T276
Test name
Test status
Simulation time 89109976812 ps
CPU time 1556.48 seconds
Started Jul 25 05:34:52 PM PDT 24
Finished Jul 25 06:00:49 PM PDT 24
Peak memory 266372 kb
Host smart-acb7bf5e-fefd-44fd-8f28-b175577c125d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165711260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.4165711260
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.475969382
Short name T681
Test name
Test status
Simulation time 14886978758 ps
CPU time 548.32 seconds
Started Jul 25 05:34:46 PM PDT 24
Finished Jul 25 05:43:55 PM PDT 24
Peak memory 248736 kb
Host smart-b149aba9-b132-449d-95a3-3786e433ad21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475969382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.475969382
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3609939588
Short name T623
Test name
Test status
Simulation time 846783144 ps
CPU time 51.63 seconds
Started Jul 25 05:34:40 PM PDT 24
Finished Jul 25 05:35:32 PM PDT 24
Peak memory 256980 kb
Host smart-8af2e0d7-f25f-4eda-98b3-1d214ea49a7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36099
39588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3609939588
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.3797957105
Short name T279
Test name
Test status
Simulation time 704727641 ps
CPU time 51.76 seconds
Started Jul 25 05:34:40 PM PDT 24
Finished Jul 25 05:35:32 PM PDT 24
Peak memory 248216 kb
Host smart-25ca1143-d1b4-4479-8785-6e1761d2d8dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37979
57105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3797957105
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.4254139458
Short name T508
Test name
Test status
Simulation time 2571076121 ps
CPU time 50.32 seconds
Started Jul 25 05:34:47 PM PDT 24
Finished Jul 25 05:35:37 PM PDT 24
Peak memory 248848 kb
Host smart-ab340ca2-69c8-41f0-a724-0cb4604e4319
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42541
39458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.4254139458
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1070526749
Short name T481
Test name
Test status
Simulation time 168463480 ps
CPU time 8.86 seconds
Started Jul 25 05:34:41 PM PDT 24
Finished Jul 25 05:34:50 PM PDT 24
Peak memory 252000 kb
Host smart-dd61a481-c4ea-4bd8-b076-5b6394e09c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10705
26749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1070526749
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2530228170
Short name T495
Test name
Test status
Simulation time 171236300151 ps
CPU time 1584.07 seconds
Started Jul 25 05:34:54 PM PDT 24
Finished Jul 25 06:01:18 PM PDT 24
Peak memory 289396 kb
Host smart-007443fe-87a2-450e-995e-4a52e5159d33
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530228170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2530228170
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.4160639093
Short name T396
Test name
Test status
Simulation time 21219256798 ps
CPU time 1233.53 seconds
Started Jul 25 05:35:01 PM PDT 24
Finished Jul 25 05:55:34 PM PDT 24
Peak memory 289480 kb
Host smart-a0d0ab3e-3f49-4624-be96-5a50bc444821
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160639093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.4160639093
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.4264048069
Short name T408
Test name
Test status
Simulation time 16695153206 ps
CPU time 222.7 seconds
Started Jul 25 05:34:57 PM PDT 24
Finished Jul 25 05:38:40 PM PDT 24
Peak memory 257120 kb
Host smart-fb338f0e-9e56-4bcc-abe6-7c5e0946fa40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42640
48069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.4264048069
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2753989692
Short name T450
Test name
Test status
Simulation time 3286068909 ps
CPU time 54.34 seconds
Started Jul 25 05:34:59 PM PDT 24
Finished Jul 25 05:35:53 PM PDT 24
Peak memory 257144 kb
Host smart-7ddfca14-2939-4a53-8302-f68bfe82555d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27539
89692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2753989692
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.4286883085
Short name T224
Test name
Test status
Simulation time 10833307253 ps
CPU time 1344.11 seconds
Started Jul 25 05:35:05 PM PDT 24
Finished Jul 25 05:57:30 PM PDT 24
Peak memory 289708 kb
Host smart-f7a8a6d5-3a12-4f56-91aa-c6732d0acbc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286883085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.4286883085
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.1121587996
Short name T300
Test name
Test status
Simulation time 6229594304 ps
CPU time 246.89 seconds
Started Jul 25 05:34:58 PM PDT 24
Finished Jul 25 05:39:05 PM PDT 24
Peak memory 247792 kb
Host smart-e7584b1b-03c4-4a47-b757-fd2a79ee884e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121587996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.1121587996
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.3416269515
Short name T509
Test name
Test status
Simulation time 159573973 ps
CPU time 12.34 seconds
Started Jul 25 05:34:59 PM PDT 24
Finished Jul 25 05:35:12 PM PDT 24
Peak memory 248800 kb
Host smart-dba141f7-a0b0-4d6e-b929-626ef1c0637d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34162
69515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.3416269515
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.960112487
Short name T689
Test name
Test status
Simulation time 1768779412 ps
CPU time 33.14 seconds
Started Jul 25 05:35:02 PM PDT 24
Finished Jul 25 05:35:35 PM PDT 24
Peak memory 256608 kb
Host smart-49b2b745-faee-475b-988e-e9b1c2b08466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96011
2487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.960112487
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.1686138086
Short name T513
Test name
Test status
Simulation time 157008325 ps
CPU time 11.17 seconds
Started Jul 25 05:34:59 PM PDT 24
Finished Jul 25 05:35:10 PM PDT 24
Peak memory 248480 kb
Host smart-6e82ce20-ea29-412f-ada6-917438d2c7a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16861
38086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.1686138086
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3909385895
Short name T443
Test name
Test status
Simulation time 289045451 ps
CPU time 21.64 seconds
Started Jul 25 05:34:52 PM PDT 24
Finished Jul 25 05:35:14 PM PDT 24
Peak memory 255376 kb
Host smart-7b653d55-3e97-4b6b-8c94-c92fa284eb53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39093
85895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3909385895
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3542267610
Short name T603
Test name
Test status
Simulation time 82413051648 ps
CPU time 1876.95 seconds
Started Jul 25 05:35:06 PM PDT 24
Finished Jul 25 06:06:23 PM PDT 24
Peak memory 289188 kb
Host smart-1e9c0eed-ab41-4244-9845-aea52296afe9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542267610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3542267610
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.1661899336
Short name T56
Test name
Test status
Simulation time 39480916363 ps
CPU time 2933.16 seconds
Started Jul 25 05:35:06 PM PDT 24
Finished Jul 25 06:23:59 PM PDT 24
Peak memory 298216 kb
Host smart-dd3da51e-0cf9-4590-9cf0-8898efbed2bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661899336 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.1661899336
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.3072305596
Short name T512
Test name
Test status
Simulation time 31730151944 ps
CPU time 2088.54 seconds
Started Jul 25 05:35:20 PM PDT 24
Finished Jul 25 06:10:09 PM PDT 24
Peak memory 288832 kb
Host smart-33e5e5b0-6567-4908-9745-1acde4b2b990
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072305596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.3072305596
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1982860651
Short name T28
Test name
Test status
Simulation time 7574998855 ps
CPU time 231.71 seconds
Started Jul 25 05:35:14 PM PDT 24
Finished Jul 25 05:39:06 PM PDT 24
Peak memory 257152 kb
Host smart-98519dae-fd43-4731-87cb-148cbd5d89cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19828
60651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1982860651
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.2813738904
Short name T602
Test name
Test status
Simulation time 119834135 ps
CPU time 7.36 seconds
Started Jul 25 05:35:15 PM PDT 24
Finished Jul 25 05:35:22 PM PDT 24
Peak memory 248424 kb
Host smart-2bc8c13f-fd36-47c7-8c18-010edca638a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28137
38904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2813738904
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.747700689
Short name T376
Test name
Test status
Simulation time 11184622370 ps
CPU time 1000.26 seconds
Started Jul 25 05:35:22 PM PDT 24
Finished Jul 25 05:52:02 PM PDT 24
Peak memory 281636 kb
Host smart-a8ae0ad8-933d-4226-a71c-48c4f92b6f6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747700689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.747700689
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.2824474166
Short name T386
Test name
Test status
Simulation time 429905819 ps
CPU time 47.98 seconds
Started Jul 25 05:35:13 PM PDT 24
Finished Jul 25 05:36:01 PM PDT 24
Peak memory 257004 kb
Host smart-f88bbf81-7ec9-4153-8015-d61f545b696d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28244
74166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2824474166
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.1281837063
Short name T644
Test name
Test status
Simulation time 784259092 ps
CPU time 49.37 seconds
Started Jul 25 05:35:13 PM PDT 24
Finished Jul 25 05:36:03 PM PDT 24
Peak memory 256468 kb
Host smart-91d92fa7-5b38-4f08-8c08-786e086eecd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12818
37063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.1281837063
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3462476477
Short name T581
Test name
Test status
Simulation time 88089784 ps
CPU time 9.4 seconds
Started Jul 25 05:35:18 PM PDT 24
Finished Jul 25 05:35:27 PM PDT 24
Peak memory 255492 kb
Host smart-36007107-8d88-4571-9a80-983397759490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34624
76477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3462476477
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.2183341776
Short name T629
Test name
Test status
Simulation time 544179525 ps
CPU time 40.05 seconds
Started Jul 25 05:35:12 PM PDT 24
Finished Jul 25 05:35:52 PM PDT 24
Peak memory 256808 kb
Host smart-cdb3e286-e20b-457c-85df-08149b02d2c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21833
41776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.2183341776
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.4108492896
Short name T282
Test name
Test status
Simulation time 318547034928 ps
CPU time 1759.92 seconds
Started Jul 25 05:35:19 PM PDT 24
Finished Jul 25 06:04:39 PM PDT 24
Peak memory 301472 kb
Host smart-41dd67f7-89b9-46b0-9367-77607d7ffab2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108492896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.4108492896
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.1278710410
Short name T103
Test name
Test status
Simulation time 79989497723 ps
CPU time 4371.52 seconds
Started Jul 25 05:35:20 PM PDT 24
Finished Jul 25 06:48:11 PM PDT 24
Peak memory 289960 kb
Host smart-dc226db1-96bb-41c4-b7cc-6ed308638290
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278710410 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.1278710410
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1035546762
Short name T651
Test name
Test status
Simulation time 7621038250 ps
CPU time 1047.34 seconds
Started Jul 25 05:36:05 PM PDT 24
Finished Jul 25 05:53:33 PM PDT 24
Peak memory 273452 kb
Host smart-24ffb1eb-edb7-44a3-81b0-de6fdfca7f6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035546762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1035546762
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1653735620
Short name T552
Test name
Test status
Simulation time 8558867869 ps
CPU time 248.62 seconds
Started Jul 25 05:35:32 PM PDT 24
Finished Jul 25 05:39:40 PM PDT 24
Peak memory 256440 kb
Host smart-1fa00df0-4f10-44ec-b731-2716a195b3de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16537
35620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1653735620
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3847304930
Short name T560
Test name
Test status
Simulation time 1824291090 ps
CPU time 13.31 seconds
Started Jul 25 05:35:25 PM PDT 24
Finished Jul 25 05:35:38 PM PDT 24
Peak memory 248428 kb
Host smart-936deec9-e075-4f08-8dc5-22421e270774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38473
04930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3847304930
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3275743585
Short name T341
Test name
Test status
Simulation time 22950200205 ps
CPU time 1564.47 seconds
Started Jul 25 05:36:04 PM PDT 24
Finished Jul 25 06:02:09 PM PDT 24
Peak memory 273176 kb
Host smart-ad08db09-bb9a-46b4-88a9-46aac02f67f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275743585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3275743585
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3663378236
Short name T707
Test name
Test status
Simulation time 18741454765 ps
CPU time 1357.71 seconds
Started Jul 25 05:36:04 PM PDT 24
Finished Jul 25 05:58:42 PM PDT 24
Peak memory 273028 kb
Host smart-ca3d93c6-f4ed-4fa9-b771-c85d0127609a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663378236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3663378236
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.355292857
Short name T305
Test name
Test status
Simulation time 84009940207 ps
CPU time 354.6 seconds
Started Jul 25 05:36:04 PM PDT 24
Finished Jul 25 05:41:59 PM PDT 24
Peak memory 248924 kb
Host smart-acabb44d-67f3-49fc-8e71-726be3e0be7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355292857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.355292857
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2069326269
Short name T44
Test name
Test status
Simulation time 4450717337 ps
CPU time 43.71 seconds
Started Jul 25 05:35:25 PM PDT 24
Finished Jul 25 05:36:09 PM PDT 24
Peak memory 256900 kb
Host smart-35b84469-7897-463f-8cc3-027c215b876e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20693
26269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2069326269
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2389606738
Short name T405
Test name
Test status
Simulation time 275140611 ps
CPU time 36.91 seconds
Started Jul 25 05:35:25 PM PDT 24
Finished Jul 25 05:36:02 PM PDT 24
Peak memory 248416 kb
Host smart-ce96f96d-7795-4435-8efc-49f9ceaacacb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23896
06738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2389606738
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3242530273
Short name T665
Test name
Test status
Simulation time 975521737 ps
CPU time 28.88 seconds
Started Jul 25 05:35:33 PM PDT 24
Finished Jul 25 05:36:02 PM PDT 24
Peak memory 248584 kb
Host smart-c69fa271-21a9-4963-a558-e9e4fb244b0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32425
30273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3242530273
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1142162453
Short name T406
Test name
Test status
Simulation time 694907713 ps
CPU time 51.77 seconds
Started Jul 25 05:35:18 PM PDT 24
Finished Jul 25 05:36:10 PM PDT 24
Peak memory 256140 kb
Host smart-9c899269-fb35-4eb5-a9f7-85871e32a6ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11421
62453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1142162453
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1156461543
Short name T81
Test name
Test status
Simulation time 45397140922 ps
CPU time 2706.81 seconds
Started Jul 25 05:36:04 PM PDT 24
Finished Jul 25 06:21:11 PM PDT 24
Peak memory 289880 kb
Host smart-9d16f4b1-919a-47f7-9596-41b33d523245
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156461543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1156461543
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3121418833
Short name T519
Test name
Test status
Simulation time 134406379766 ps
CPU time 1628.59 seconds
Started Jul 25 05:36:10 PM PDT 24
Finished Jul 25 06:03:18 PM PDT 24
Peak memory 273312 kb
Host smart-cfd3033d-28fc-4ba2-b209-f652f15d2305
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121418833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3121418833
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.4157831327
Short name T12
Test name
Test status
Simulation time 4814510373 ps
CPU time 133.88 seconds
Started Jul 25 05:36:07 PM PDT 24
Finished Jul 25 05:38:21 PM PDT 24
Peak memory 257076 kb
Host smart-1bd6609a-a66b-4682-afd2-74aa4cd5e07d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41578
31327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.4157831327
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.3132609750
Short name T673
Test name
Test status
Simulation time 4243568800 ps
CPU time 28.16 seconds
Started Jul 25 05:36:07 PM PDT 24
Finished Jul 25 05:36:35 PM PDT 24
Peak memory 256196 kb
Host smart-07ac51c0-cabb-412f-8ac2-3ba32e7715de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31326
09750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.3132609750
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3615102243
Short name T306
Test name
Test status
Simulation time 103784772503 ps
CPU time 1510.83 seconds
Started Jul 25 05:36:08 PM PDT 24
Finished Jul 25 06:01:19 PM PDT 24
Peak memory 265168 kb
Host smart-78909f90-eda9-4158-a9e2-ae2bdd10b696
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615102243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3615102243
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.3216407651
Short name T467
Test name
Test status
Simulation time 178215233812 ps
CPU time 1676.69 seconds
Started Jul 25 05:36:07 PM PDT 24
Finished Jul 25 06:04:04 PM PDT 24
Peak memory 271964 kb
Host smart-4842f655-1ed8-433d-b91d-e24d958e19c1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216407651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.3216407651
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.1436737718
Short name T318
Test name
Test status
Simulation time 5764206440 ps
CPU time 239.1 seconds
Started Jul 25 05:36:08 PM PDT 24
Finished Jul 25 05:40:07 PM PDT 24
Peak memory 248916 kb
Host smart-d5de2628-9e3f-46ff-9528-9999cf46e54b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436737718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.1436737718
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3834316104
Short name T594
Test name
Test status
Simulation time 124081084 ps
CPU time 4.38 seconds
Started Jul 25 05:36:07 PM PDT 24
Finished Jul 25 05:36:12 PM PDT 24
Peak memory 248864 kb
Host smart-9a3d657c-f592-4447-9e6c-d2457882fb4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38343
16104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3834316104
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2970032962
Short name T511
Test name
Test status
Simulation time 242711836 ps
CPU time 15.52 seconds
Started Jul 25 05:36:10 PM PDT 24
Finished Jul 25 05:36:26 PM PDT 24
Peak memory 248292 kb
Host smart-1fe59585-365d-482e-b779-4c646a02cf23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29700
32962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2970032962
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2356826670
Short name T426
Test name
Test status
Simulation time 2589523106 ps
CPU time 32.76 seconds
Started Jul 25 05:36:06 PM PDT 24
Finished Jul 25 05:36:39 PM PDT 24
Peak memory 256976 kb
Host smart-6a91e8c9-1822-456b-af71-dc783f3f5ce1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23568
26670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2356826670
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.853109012
Short name T209
Test name
Test status
Simulation time 240058829 ps
CPU time 8.17 seconds
Started Jul 25 05:36:03 PM PDT 24
Finished Jul 25 05:36:12 PM PDT 24
Peak memory 248828 kb
Host smart-3ced32fa-7327-40c3-bba1-754a80a39529
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85310
9012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.853109012
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.138231941
Short name T273
Test name
Test status
Simulation time 42692368304 ps
CPU time 2575.23 seconds
Started Jul 25 05:36:10 PM PDT 24
Finished Jul 25 06:19:06 PM PDT 24
Peak memory 289132 kb
Host smart-43495e45-49d2-4372-b35a-4335966f1b85
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=138231941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_han
dler_stress_all.138231941
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.4143233634
Short name T539
Test name
Test status
Simulation time 69730810115 ps
CPU time 2606.86 seconds
Started Jul 25 05:36:09 PM PDT 24
Finished Jul 25 06:19:36 PM PDT 24
Peak memory 289364 kb
Host smart-5be5cbe6-04ea-41ff-bbc9-df91cad2de49
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143233634 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.4143233634
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.1536825036
Short name T98
Test name
Test status
Simulation time 27315063895 ps
CPU time 1490.03 seconds
Started Jul 25 05:36:22 PM PDT 24
Finished Jul 25 06:01:12 PM PDT 24
Peak memory 272956 kb
Host smart-acafd83a-6d95-4877-83b4-c8d3d3fd71af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536825036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1536825036
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.3698980104
Short name T87
Test name
Test status
Simulation time 813071242 ps
CPU time 40.27 seconds
Started Jul 25 05:36:12 PM PDT 24
Finished Jul 25 05:36:52 PM PDT 24
Peak memory 256604 kb
Host smart-aaeb8809-73fd-4446-9b39-110d8cc67e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36989
80104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.3698980104
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.299983965
Short name T39
Test name
Test status
Simulation time 904177603 ps
CPU time 60.87 seconds
Started Jul 25 05:36:16 PM PDT 24
Finished Jul 25 05:37:17 PM PDT 24
Peak memory 248512 kb
Host smart-74922cac-2039-48e5-a73f-b8b435586dec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29998
3965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.299983965
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.782541832
Short name T334
Test name
Test status
Simulation time 169395429916 ps
CPU time 2537.6 seconds
Started Jul 25 05:36:16 PM PDT 24
Finished Jul 25 06:18:34 PM PDT 24
Peak memory 288988 kb
Host smart-f9d51181-28b2-42f6-9c82-5cd56d15df09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782541832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.782541832
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2899457419
Short name T93
Test name
Test status
Simulation time 86429787988 ps
CPU time 1351.9 seconds
Started Jul 25 05:36:24 PM PDT 24
Finished Jul 25 05:58:56 PM PDT 24
Peak memory 289096 kb
Host smart-8dda093a-474f-40a5-b9fc-22de20b16dd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899457419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2899457419
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2962928697
Short name T320
Test name
Test status
Simulation time 7246222535 ps
CPU time 284.64 seconds
Started Jul 25 05:36:23 PM PDT 24
Finished Jul 25 05:41:08 PM PDT 24
Peak memory 247772 kb
Host smart-3e186924-0668-450e-8146-ba49c847e60e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962928697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2962928697
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.659523615
Short name T62
Test name
Test status
Simulation time 832560123 ps
CPU time 46.96 seconds
Started Jul 25 05:36:16 PM PDT 24
Finished Jul 25 05:37:03 PM PDT 24
Peak memory 248860 kb
Host smart-4bf6cc31-3904-4fc8-af25-b975fe3a124e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65952
3615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.659523615
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.3447682672
Short name T563
Test name
Test status
Simulation time 808145923 ps
CPU time 55.64 seconds
Started Jul 25 05:36:15 PM PDT 24
Finished Jul 25 05:37:11 PM PDT 24
Peak memory 248900 kb
Host smart-fa208507-2397-454c-b3fd-73123730e853
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34476
82672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.3447682672
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.1970166549
Short name T596
Test name
Test status
Simulation time 487261956 ps
CPU time 32.05 seconds
Started Jul 25 05:36:14 PM PDT 24
Finished Jul 25 05:36:46 PM PDT 24
Peak memory 248892 kb
Host smart-a70e2412-8908-4925-ac53-33ea18738518
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19701
66549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1970166549
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.2419729313
Short name T483
Test name
Test status
Simulation time 929724819 ps
CPU time 62.56 seconds
Started Jul 25 05:36:10 PM PDT 24
Finished Jul 25 05:37:13 PM PDT 24
Peak memory 256044 kb
Host smart-f393129e-ecf8-4ef5-b47c-7a3c0fe124c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24197
29313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.2419729313
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2031638257
Short name T61
Test name
Test status
Simulation time 140111064 ps
CPU time 3.2 seconds
Started Jul 25 05:22:47 PM PDT 24
Finished Jul 25 05:22:50 PM PDT 24
Peak memory 249160 kb
Host smart-e7601926-55b5-4642-90ea-686466208cc3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2031638257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2031638257
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.2744795005
Short name T480
Test name
Test status
Simulation time 52421932886 ps
CPU time 1611.98 seconds
Started Jul 25 05:22:38 PM PDT 24
Finished Jul 25 05:49:30 PM PDT 24
Peak memory 272848 kb
Host smart-13bf30e8-12aa-4fa1-8371-f60b1c64e62c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744795005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.2744795005
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2707862934
Short name T587
Test name
Test status
Simulation time 839844876 ps
CPU time 9.89 seconds
Started Jul 25 05:22:44 PM PDT 24
Finished Jul 25 05:22:54 PM PDT 24
Peak memory 248872 kb
Host smart-aa4d08f3-023b-4c5c-9d69-a3c13f88e32c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2707862934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2707862934
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.2184586395
Short name T382
Test name
Test status
Simulation time 10083947143 ps
CPU time 142.66 seconds
Started Jul 25 05:22:41 PM PDT 24
Finished Jul 25 05:25:04 PM PDT 24
Peak memory 257080 kb
Host smart-ce6e3f91-b7a7-4709-8bc0-ce6c6c2a8d71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21845
86395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.2184586395
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3397611239
Short name T666
Test name
Test status
Simulation time 574302913 ps
CPU time 8.28 seconds
Started Jul 25 05:22:38 PM PDT 24
Finished Jul 25 05:22:46 PM PDT 24
Peak memory 248120 kb
Host smart-d9a84b0a-ab38-446d-8c39-a012ed7fc6eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33976
11239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3397611239
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.4026342493
Short name T709
Test name
Test status
Simulation time 84573613489 ps
CPU time 1393.99 seconds
Started Jul 25 05:22:38 PM PDT 24
Finished Jul 25 05:45:52 PM PDT 24
Peak memory 265316 kb
Host smart-f377a959-be25-4ba3-b187-874b71af2137
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026342493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.4026342493
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.4094799458
Short name T429
Test name
Test status
Simulation time 87069885602 ps
CPU time 2707.38 seconds
Started Jul 25 05:22:39 PM PDT 24
Finished Jul 25 06:07:47 PM PDT 24
Peak memory 289156 kb
Host smart-5bcea6c1-117d-475f-bb0b-9184be0de8fa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094799458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.4094799458
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.3465671369
Short name T304
Test name
Test status
Simulation time 14110355965 ps
CPU time 292.64 seconds
Started Jul 25 05:22:39 PM PDT 24
Finished Jul 25 05:27:32 PM PDT 24
Peak memory 248836 kb
Host smart-06411936-914f-4a06-bbe5-add8cd7ae977
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3465671369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3465671369
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3771635368
Short name T466
Test name
Test status
Simulation time 167528612 ps
CPU time 11.51 seconds
Started Jul 25 05:22:31 PM PDT 24
Finished Jul 25 05:22:43 PM PDT 24
Peak memory 248820 kb
Host smart-e760b91d-0d6f-451c-9fdc-de53b5e99290
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37716
35368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3771635368
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.1095223211
Short name T178
Test name
Test status
Simulation time 113570068 ps
CPU time 4.08 seconds
Started Jul 25 05:22:31 PM PDT 24
Finished Jul 25 05:22:35 PM PDT 24
Peak memory 240212 kb
Host smart-8574bd8a-a19c-458b-9c9b-2e6c2ca90810
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10952
23211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.1095223211
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.2948640315
Short name T42
Test name
Test status
Simulation time 634534955 ps
CPU time 40.09 seconds
Started Jul 25 05:22:39 PM PDT 24
Finished Jul 25 05:23:19 PM PDT 24
Peak memory 249908 kb
Host smart-ef1b1c65-989e-40c8-889c-bebd83112b15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29486
40315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.2948640315
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.3884263924
Short name T453
Test name
Test status
Simulation time 406615411 ps
CPU time 32.89 seconds
Started Jul 25 05:22:31 PM PDT 24
Finished Jul 25 05:23:04 PM PDT 24
Peak memory 256892 kb
Host smart-61613d9b-cbc9-4f9e-b0e5-38e44052f097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38842
63924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3884263924
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3305058376
Short name T257
Test name
Test status
Simulation time 21074305490 ps
CPU time 2215.96 seconds
Started Jul 25 05:22:44 PM PDT 24
Finished Jul 25 05:59:41 PM PDT 24
Peak memory 304648 kb
Host smart-56763f21-74c2-4112-a35b-5b70925dbc6f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305058376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3305058376
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1751239738
Short name T192
Test name
Test status
Simulation time 21062468 ps
CPU time 2.73 seconds
Started Jul 25 05:22:57 PM PDT 24
Finished Jul 25 05:22:59 PM PDT 24
Peak memory 249088 kb
Host smart-eaf3f794-a838-496c-8782-98840109aa42
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1751239738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1751239738
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.810247673
Short name T66
Test name
Test status
Simulation time 18891157982 ps
CPU time 882.98 seconds
Started Jul 25 05:22:45 PM PDT 24
Finished Jul 25 05:37:29 PM PDT 24
Peak memory 265332 kb
Host smart-21a07e0d-7ec4-44de-83d3-bcaeb5bf58b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810247673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.810247673
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.998556854
Short name T422
Test name
Test status
Simulation time 14228928687 ps
CPU time 59.8 seconds
Started Jul 25 05:22:58 PM PDT 24
Finished Jul 25 05:23:57 PM PDT 24
Peak memory 248908 kb
Host smart-d0206ad4-3280-47ef-8a73-6f79412cff29
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=998556854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.998556854
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.2820960680
Short name T704
Test name
Test status
Simulation time 3986627825 ps
CPU time 122.86 seconds
Started Jul 25 05:22:45 PM PDT 24
Finished Jul 25 05:24:48 PM PDT 24
Peak memory 256684 kb
Host smart-98000b64-5eec-45dd-9a85-42438f05c68b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28209
60680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.2820960680
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1665816296
Short name T383
Test name
Test status
Simulation time 794534062 ps
CPU time 53.61 seconds
Started Jul 25 05:22:46 PM PDT 24
Finished Jul 25 05:23:40 PM PDT 24
Peak memory 257028 kb
Host smart-2c72e875-73ae-4718-9da8-44c35723eb3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16658
16296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1665816296
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.205799856
Short name T346
Test name
Test status
Simulation time 100441558180 ps
CPU time 1939.97 seconds
Started Jul 25 05:22:57 PM PDT 24
Finished Jul 25 05:55:18 PM PDT 24
Peak memory 289312 kb
Host smart-f5b8b5db-dcbf-4c46-8e87-499c1e473502
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205799856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.205799856
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1114731802
Short name T627
Test name
Test status
Simulation time 25691393135 ps
CPU time 1450.33 seconds
Started Jul 25 05:22:58 PM PDT 24
Finished Jul 25 05:47:09 PM PDT 24
Peak memory 281728 kb
Host smart-a4374960-904a-4955-9b97-34455e527600
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114731802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1114731802
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.4125415584
Short name T322
Test name
Test status
Simulation time 19220456253 ps
CPU time 420.98 seconds
Started Jul 25 05:22:46 PM PDT 24
Finished Jul 25 05:29:47 PM PDT 24
Peak memory 248928 kb
Host smart-d60502ed-f318-4744-a2bf-164658cf79a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125415584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.4125415584
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.1571974979
Short name T593
Test name
Test status
Simulation time 2844379049 ps
CPU time 53.06 seconds
Started Jul 25 05:22:45 PM PDT 24
Finished Jul 25 05:23:38 PM PDT 24
Peak memory 256300 kb
Host smart-95787e21-1254-40e4-b661-6039cda2c277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15719
74979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.1571974979
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3178343800
Short name T221
Test name
Test status
Simulation time 144928786 ps
CPU time 9.22 seconds
Started Jul 25 05:22:46 PM PDT 24
Finished Jul 25 05:22:55 PM PDT 24
Peak memory 248416 kb
Host smart-afa5e99e-076e-4ef6-ac6f-7db1b846c709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31783
43800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3178343800
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1437471116
Short name T531
Test name
Test status
Simulation time 617761646 ps
CPU time 5.75 seconds
Started Jul 25 05:22:45 PM PDT 24
Finished Jul 25 05:22:51 PM PDT 24
Peak memory 250724 kb
Host smart-af17dc5f-fb68-4e6e-81fe-2a1f9697d955
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14374
71116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1437471116
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.1502025105
Short name T272
Test name
Test status
Simulation time 73758903031 ps
CPU time 1661.09 seconds
Started Jul 25 05:22:58 PM PDT 24
Finished Jul 25 05:50:39 PM PDT 24
Peak memory 289872 kb
Host smart-018d1a57-fcb7-48da-b1e5-f4fd0869823d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502025105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.1502025105
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.2669622101
Short name T204
Test name
Test status
Simulation time 87011560 ps
CPU time 3.38 seconds
Started Jul 25 05:23:09 PM PDT 24
Finished Jul 25 05:23:12 PM PDT 24
Peak memory 249168 kb
Host smart-7cb15f20-bbc1-48e1-b2f0-a9ca925d7d3d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2669622101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2669622101
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.2930659596
Short name T53
Test name
Test status
Simulation time 6765854196 ps
CPU time 807.89 seconds
Started Jul 25 05:23:00 PM PDT 24
Finished Jul 25 05:36:28 PM PDT 24
Peak memory 272796 kb
Host smart-ce7235e2-8141-4810-a93b-49232c9ea51b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930659596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2930659596
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2527908264
Short name T710
Test name
Test status
Simulation time 1487571837 ps
CPU time 18.68 seconds
Started Jul 25 05:23:08 PM PDT 24
Finished Jul 25 05:23:26 PM PDT 24
Peak memory 248856 kb
Host smart-e97eea19-0729-4ad6-aad3-25743404e915
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2527908264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2527908264
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.3521956723
Short name T579
Test name
Test status
Simulation time 768723799 ps
CPU time 64.18 seconds
Started Jul 25 05:22:56 PM PDT 24
Finished Jul 25 05:24:00 PM PDT 24
Peak memory 256424 kb
Host smart-18e675ae-cd21-4ca6-8916-ef50ecd28253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35219
56723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3521956723
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.1480918265
Short name T631
Test name
Test status
Simulation time 1165812812 ps
CPU time 43.56 seconds
Started Jul 25 05:22:59 PM PDT 24
Finished Jul 25 05:23:43 PM PDT 24
Peak memory 249928 kb
Host smart-ddc6a5a0-fe69-44b7-b6fd-ebb5b57aff57
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14809
18265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.1480918265
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.4068228096
Short name T310
Test name
Test status
Simulation time 53631533673 ps
CPU time 1093.48 seconds
Started Jul 25 05:23:08 PM PDT 24
Finished Jul 25 05:41:22 PM PDT 24
Peak memory 284344 kb
Host smart-65262f15-aa49-48e0-a02d-ffdb7e17ec0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068228096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.4068228096
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2583004261
Short name T21
Test name
Test status
Simulation time 40740562873 ps
CPU time 1204.92 seconds
Started Jul 25 05:23:07 PM PDT 24
Finished Jul 25 05:43:12 PM PDT 24
Peak memory 273296 kb
Host smart-f699fbaa-b925-411a-ad15-048a36e9d21a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583004261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2583004261
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.1141730413
Short name T36
Test name
Test status
Simulation time 967863831 ps
CPU time 25.27 seconds
Started Jul 25 05:22:59 PM PDT 24
Finished Jul 25 05:23:24 PM PDT 24
Peak memory 248900 kb
Host smart-a70b9051-c2cd-4d58-81ad-df101e373bb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11417
30413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.1141730413
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2250866154
Short name T646
Test name
Test status
Simulation time 1408467815 ps
CPU time 27.53 seconds
Started Jul 25 05:22:59 PM PDT 24
Finished Jul 25 05:23:26 PM PDT 24
Peak memory 248224 kb
Host smart-128dd9ed-b743-4a91-80c8-257e37c03c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22508
66154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2250866154
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.568522116
Short name T269
Test name
Test status
Simulation time 214786147 ps
CPU time 25.07 seconds
Started Jul 25 05:22:59 PM PDT 24
Finished Jul 25 05:23:25 PM PDT 24
Peak memory 248824 kb
Host smart-eec4dfe2-08c5-4e12-934c-9db57ef58ea9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56852
2116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.568522116
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3765797639
Short name T505
Test name
Test status
Simulation time 808440948 ps
CPU time 8.54 seconds
Started Jul 25 05:22:58 PM PDT 24
Finished Jul 25 05:23:06 PM PDT 24
Peak memory 254696 kb
Host smart-507b146e-aefa-4135-aaf9-835504cb8666
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37657
97639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3765797639
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1671697157
Short name T523
Test name
Test status
Simulation time 46202032429 ps
CPU time 1225.15 seconds
Started Jul 25 05:23:07 PM PDT 24
Finished Jul 25 05:43:32 PM PDT 24
Peak memory 281708 kb
Host smart-f474e893-a608-4f79-a8c8-931be946f232
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671697157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1671697157
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.2714676630
Short name T55
Test name
Test status
Simulation time 431882088682 ps
CPU time 7197.44 seconds
Started Jul 25 05:23:20 PM PDT 24
Finished Jul 25 07:23:18 PM PDT 24
Peak memory 369280 kb
Host smart-830414a8-6990-46c1-bf1d-390ac90ec20c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714676630 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.2714676630
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2719556346
Short name T202
Test name
Test status
Simulation time 31297838 ps
CPU time 3.5 seconds
Started Jul 25 05:23:26 PM PDT 24
Finished Jul 25 05:23:30 PM PDT 24
Peak memory 249184 kb
Host smart-f4be5e12-232d-409b-b661-c39c9832a78e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2719556346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2719556346
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.1388664438
Short name T626
Test name
Test status
Simulation time 102463616533 ps
CPU time 1088.47 seconds
Started Jul 25 05:23:27 PM PDT 24
Finished Jul 25 05:41:35 PM PDT 24
Peak memory 271768 kb
Host smart-459c5cd3-7bb6-4bb6-9fc7-2c9a81288163
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388664438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1388664438
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1404365984
Short name T657
Test name
Test status
Simulation time 123592786 ps
CPU time 8.3 seconds
Started Jul 25 05:23:29 PM PDT 24
Finished Jul 25 05:23:37 PM PDT 24
Peak memory 248780 kb
Host smart-93298dc5-cd44-4c2b-aa71-68b64ee9aa45
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1404365984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1404365984
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.1544333828
Short name T520
Test name
Test status
Simulation time 343863443 ps
CPU time 11.15 seconds
Started Jul 25 05:23:19 PM PDT 24
Finished Jul 25 05:23:30 PM PDT 24
Peak memory 256200 kb
Host smart-15f73c18-4b14-4721-b95c-0fad45bfd0da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15443
33828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.1544333828
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.1571682804
Short name T515
Test name
Test status
Simulation time 2484637940 ps
CPU time 36.49 seconds
Started Jul 25 05:23:24 PM PDT 24
Finished Jul 25 05:24:01 PM PDT 24
Peak memory 255980 kb
Host smart-02f50b38-623b-44bc-b0f4-882567e17587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15716
82804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.1571682804
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.489140167
Short name T287
Test name
Test status
Simulation time 66358574215 ps
CPU time 1251.45 seconds
Started Jul 25 05:23:27 PM PDT 24
Finished Jul 25 05:44:18 PM PDT 24
Peak memory 272884 kb
Host smart-00fa0cf7-ec61-4260-b6df-2f0a5ba2d65e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489140167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.489140167
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.470070450
Short name T14
Test name
Test status
Simulation time 65695186181 ps
CPU time 2413.76 seconds
Started Jul 25 05:23:28 PM PDT 24
Finished Jul 25 06:03:42 PM PDT 24
Peak memory 289752 kb
Host smart-8b2da9c1-f7ca-4542-93ad-c59b6b49a254
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470070450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.470070450
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3923974265
Short name T301
Test name
Test status
Simulation time 24516278385 ps
CPU time 260.65 seconds
Started Jul 25 05:23:27 PM PDT 24
Finished Jul 25 05:27:48 PM PDT 24
Peak memory 249084 kb
Host smart-015b29af-a9de-4ba6-ae1d-949926dce27a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923974265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3923974265
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.3727702926
Short name T387
Test name
Test status
Simulation time 344092857 ps
CPU time 30.65 seconds
Started Jul 25 05:23:18 PM PDT 24
Finished Jul 25 05:23:49 PM PDT 24
Peak memory 248900 kb
Host smart-d201d5c0-e9cd-4c95-80f2-f3fc3bd036db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37277
02926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.3727702926
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2820338669
Short name T67
Test name
Test status
Simulation time 1550238941 ps
CPU time 52.81 seconds
Started Jul 25 05:23:19 PM PDT 24
Finished Jul 25 05:24:12 PM PDT 24
Peak memory 256604 kb
Host smart-68f20b48-be91-4dce-a2ac-292f6fe196c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28203
38669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2820338669
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.2269990158
Short name T72
Test name
Test status
Simulation time 900243409 ps
CPU time 14.49 seconds
Started Jul 25 05:23:17 PM PDT 24
Finished Jul 25 05:23:32 PM PDT 24
Peak memory 248380 kb
Host smart-464d62a5-11aa-4fc3-8de6-b4ff69c504ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22699
90158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.2269990158
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.424983014
Short name T630
Test name
Test status
Simulation time 102502913 ps
CPU time 14.43 seconds
Started Jul 25 05:23:17 PM PDT 24
Finished Jul 25 05:23:32 PM PDT 24
Peak memory 257048 kb
Host smart-c3217366-28f9-42cd-a57c-59fef63ed845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42498
3014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.424983014
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.307697263
Short name T5
Test name
Test status
Simulation time 162776085498 ps
CPU time 1234.44 seconds
Started Jul 25 05:23:28 PM PDT 24
Finished Jul 25 05:44:03 PM PDT 24
Peak memory 288744 kb
Host smart-6d76e383-b086-4892-920d-1745b5818bfb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307697263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_hand
ler_stress_all.307697263
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.1779229930
Short name T183
Test name
Test status
Simulation time 101583955400 ps
CPU time 2933.57 seconds
Started Jul 25 05:23:26 PM PDT 24
Finished Jul 25 06:12:20 PM PDT 24
Peak memory 321572 kb
Host smart-09b28302-1a36-40a4-8263-9dfd76c2ba33
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779229930 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.1779229930
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.3359712622
Short name T194
Test name
Test status
Simulation time 163227965 ps
CPU time 3.08 seconds
Started Jul 25 05:23:36 PM PDT 24
Finished Jul 25 05:23:39 PM PDT 24
Peak memory 249032 kb
Host smart-54da89a8-b0ba-4bf6-8a0b-caea194a97d3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3359712622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3359712622
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1058963993
Short name T605
Test name
Test status
Simulation time 70402090076 ps
CPU time 1634.65 seconds
Started Jul 25 05:23:40 PM PDT 24
Finished Jul 25 05:50:55 PM PDT 24
Peak memory 289664 kb
Host smart-d7803d86-dfe5-4012-a22f-a9be7cd8f449
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058963993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1058963993
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1603660426
Short name T411
Test name
Test status
Simulation time 1240143367 ps
CPU time 31.14 seconds
Started Jul 25 05:23:34 PM PDT 24
Finished Jul 25 05:24:05 PM PDT 24
Peak memory 248820 kb
Host smart-74877c8f-cd55-4479-8c91-4d245e162062
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1603660426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1603660426
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.204377691
Short name T478
Test name
Test status
Simulation time 1759833930 ps
CPU time 101.47 seconds
Started Jul 25 05:23:26 PM PDT 24
Finished Jul 25 05:25:08 PM PDT 24
Peak memory 256200 kb
Host smart-b961faac-b34e-43ab-a263-9649e64713b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20437
7691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.204377691
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.873696301
Short name T693
Test name
Test status
Simulation time 184507714 ps
CPU time 15.5 seconds
Started Jul 25 05:23:27 PM PDT 24
Finished Jul 25 05:23:42 PM PDT 24
Peak memory 255316 kb
Host smart-6c9c5baa-802b-489a-8b98-ff0a94f8df24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87369
6301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.873696301
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2837999439
Short name T328
Test name
Test status
Simulation time 66728353030 ps
CPU time 1937.8 seconds
Started Jul 25 05:23:35 PM PDT 24
Finished Jul 25 05:55:53 PM PDT 24
Peak memory 273420 kb
Host smart-f156ca62-b3e6-4558-ac88-78e4cd71ba17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837999439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2837999439
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2983432449
Short name T496
Test name
Test status
Simulation time 114316231953 ps
CPU time 3470.89 seconds
Started Jul 25 05:23:36 PM PDT 24
Finished Jul 25 06:21:27 PM PDT 24
Peak memory 289508 kb
Host smart-12686fea-3763-47db-89cb-b47f70ff905a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983432449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2983432449
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1992315993
Short name T298
Test name
Test status
Simulation time 14759244271 ps
CPU time 303.4 seconds
Started Jul 25 05:23:36 PM PDT 24
Finished Jul 25 05:28:40 PM PDT 24
Peak memory 248900 kb
Host smart-aa2590c3-6282-474d-9ba5-3c832537746d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992315993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1992315993
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1312696894
Short name T597
Test name
Test status
Simulation time 122863014 ps
CPU time 8.11 seconds
Started Jul 25 05:23:28 PM PDT 24
Finished Jul 25 05:23:36 PM PDT 24
Peak memory 248844 kb
Host smart-ec32ee40-3844-497b-8bb7-9957ef647e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13126
96894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1312696894
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.3364804336
Short name T574
Test name
Test status
Simulation time 1174330652 ps
CPU time 35.72 seconds
Started Jul 25 05:23:26 PM PDT 24
Finished Jul 25 05:24:02 PM PDT 24
Peak memory 248116 kb
Host smart-4f79d6f3-e965-4e3f-a465-55350cdd8f3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33648
04336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3364804336
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.2835467330
Short name T617
Test name
Test status
Simulation time 1481977471 ps
CPU time 53.22 seconds
Started Jul 25 05:23:27 PM PDT 24
Finished Jul 25 05:24:20 PM PDT 24
Peak memory 249236 kb
Host smart-cf777dc4-f0cc-4f44-bf0f-f7ac57b3e18d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28354
67330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2835467330
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.3274308870
Short name T373
Test name
Test status
Simulation time 10723211727 ps
CPU time 54.12 seconds
Started Jul 25 05:23:26 PM PDT 24
Finished Jul 25 05:24:21 PM PDT 24
Peak memory 256844 kb
Host smart-93601f09-24c8-4030-8f31-e885dde30113
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32743
08870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3274308870
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.2816538024
Short name T228
Test name
Test status
Simulation time 62870159758 ps
CPU time 3664.34 seconds
Started Jul 25 05:23:35 PM PDT 24
Finished Jul 25 06:24:40 PM PDT 24
Peak memory 288384 kb
Host smart-31474733-1510-4e93-96c9-f8128f898100
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816538024 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.2816538024
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%