Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T45,T109,T219
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	14681	0	0
DisabledNoTrigBkwd_A	2147483647	806173	0	0
DisabledNoTrigFwd_A	2147483647	1421799341	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	14681	0	0
T13	19208	0	0	0
T14	14959	0	0	0
T15	665332	0	0	0
T16	893948	0	0	0
T45	3552	1178	0	0
T46	7054	0	0	0
T47	87990	0	0	0
T48	112513	0	0	0
T66	13281	0	0	0
T74	24240	0	0	0
T75	114111	0	0	0
T78	92903	0	0	0
T109	1137	402	0	0
T110	99802	0	0	0
T111	128419	0	0	0
T129	238560	0	0	0
T219	0	581	0	0
T220	0	218	0	0
T221	0	796	0	0
T222	4693	1049	0	0
T223	0	233	0	0
T224	0	1317	0	0
T225	0	523	0	0
T226	0	601	0	0
T227	0	792	0	0
T228	0	1247	0	0
T229	0	416	0	0
T230	0	1174	0	0
T231	0	776	0	0
T232	0	1049	0	0
T233	0	303	0	0
T234	0	689	0	0
T235	0	709	0	0
T236	0	628	0	0
T237	79905	0	0	0
T238	31149	0	0	0
T239	67766	0	0	0
T240	700665	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	806173	0	0
T1	2271856	8982	0	0
T2	91700	0	0	0
T3	141772	9	0	0
T4	1485236	11	0	0
T5	569600	1516	0	0
T6	3256668	10	0	0
T7	424176	0	0	0
T11	1494948	1040	0	0
T15	0	4433	0	0
T16	0	3205	0	0
T18	50180	56	0	0
T19	103332	113	0	0
T28	0	824	0	0
T43	0	3	0	0
T44	0	23	0	0
T45	0	30	0	0
T46	0	1	0	0
T47	0	78	0	0
T48	0	22	0	0
T49	0	2	0	0
T50	0	369	0	0
T51	0	69	0	0
T66	0	15	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1421799341	0	0
T1	2271856	1645011	0	0
T2	91700	68910	0	0
T3	141772	106965	0	0
T4	1485236	753885	0	0
T5	569600	497164	0	0
T6	3256668	2339181	0	0
T7	424176	242156	0	0
T11	1494948	757632	0	0
T18	50180	31334	0	0
T19	103332	47108	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T3,T6

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T45,T219,T224
1	1	Covered	T1,T3,T6

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	660610922	6042	0	0
DisabledNoTrigBkwd_A	660610922	236499	0	0
DisabledNoTrigFwd_A	660610922	334843196	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	6042	0	0
T13	19208	0	0	0
T14	14959	0	0	0
T15	665332	0	0	0
T16	893948	0	0	0
T45	3552	1178	0	0
T46	7054	0	0	0
T47	87990	0	0	0
T48	112513	0	0	0
T66	13281	0	0	0
T219	0	581	0	0
T224	0	1317	0	0
T227	0	792	0	0
T229	0	416	0	0
T232	0	1049	0	0
T235	0	709	0	0
T237	79905	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	236499	0	0
T1	567964	1525	0	0
T2	22925	0	0	0
T3	35443	9	0	0
T4	371309	0	0	0
T5	142400	536	0	0
T6	814167	1	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T18	12545	1	0	0
T19	25833	74	0	0
T44	0	23	0	0
T45	0	30	0	0
T46	0	1	0	0
T47	0	78	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	334843196	0	0
T1	567964	423775	0	0
T2	22925	22853	0	0
T3	35443	795	0	0
T4	371309	254613	0	0
T5	142400	102786	0	0
T6	814167	708806	0	0
T7	106044	101640	0	0
T11	373737	373732	0	0
T18	12545	6306	0	0
T19	25833	5919	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T109,T223,T225
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	660610922	5286	0	0
DisabledNoTrigBkwd_A	660610922	170850	0	0
DisabledNoTrigFwd_A	660610922	387264415	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	5286	0	0
T74	24240	0	0	0
T75	114111	0	0	0
T78	92903	0	0	0
T109	1137	402	0	0
T110	99802	0	0	0
T111	128419	0	0	0
T129	238560	0	0	0
T223	0	233	0	0
T225	0	523	0	0
T228	0	1247	0	0
T230	0	1174	0	0
T231	0	776	0	0
T233	0	303	0	0
T236	0	628	0	0
T238	31149	0	0	0
T239	67766	0	0	0
T240	700665	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	170850	0	0
T1	567964	6383	0	0
T2	22925	0	0	0
T3	35443	0	0	0
T4	371309	11	0	0
T5	142400	82	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	667	0	0
T15	0	2187	0	0
T16	0	1702	0	0
T18	12545	0	0	0
T19	25833	30	0	0
T28	0	3	0	0
T48	0	4	0	0
T50	0	160	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	387264415	0	0
T1	567964	203333	0	0
T2	22925	19506	0	0
T3	35443	35390	0	0
T4	371309	54133	0	0
T5	142400	133424	0	0
T6	814167	814111	0	0
T7	106044	31802	0	0
T11	373737	7511	0	0
T18	12545	12472	0	0
T19	25833	3207	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T6

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T222
1	1	Covered	T1,T2,T6

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T6,T18

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	660610922	1049	0	0
DisabledNoTrigBkwd_A	660610922	185675	0	0
DisabledNoTrigFwd_A	660610922	340622889	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	1049	0	0
T222	4693	1049	0	0
T241	27082	0	0	0
T242	56862	0	0	0
T243	35854	0	0	0
T244	228777	0	0	0
T245	241361	0	0	0
T246	55169	0	0	0
T247	137278	0	0	0
T248	137349	0	0	0
T249	4083	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	185675	0	0
T1	567964	1020	0	0
T2	22925	0	0	0
T3	35443	0	0	0
T4	371309	0	0	0
T5	142400	134	0	0
T6	814167	9	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T15	0	1039	0	0
T16	0	1503	0	0
T18	12545	54	0	0
T19	25833	3	0	0
T48	0	18	0	0
T49	0	2	0	0
T66	0	15	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	340622889	0	0
T1	567964	470487	0	0
T2	22925	9083	0	0
T3	35443	35390	0	0
T4	371309	215507	0	0
T5	142400	126523	0	0
T6	814167	2153	0	0
T7	106044	2677	0	0
T11	373737	373732	0	0
T18	12545	2491	0	0
T19	25833	19166	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T4

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T220,T221,T226
1	1	Covered	T1,T2,T4

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T18,T5

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	660610922	2304	0	0
DisabledNoTrigBkwd_A	660610922	213149	0	0
DisabledNoTrigFwd_A	660610922	359068841	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	2304	0	0
T62	614387	0	0	0
T220	2336	218	0	0
T221	0	796	0	0
T226	0	601	0	0
T234	0	689	0	0
T250	186047	0	0	0
T251	154527	0	0	0
T252	1678	0	0	0
T253	6480	0	0	0
T254	127736	0	0	0
T255	470845	0	0	0
T256	28469	0	0	0
T257	156540	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	213149	0	0
T1	567964	54	0	0
T2	22925	0	0	0
T3	35443	0	0	0
T4	371309	0	0	0
T5	142400	764	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	373	0	0
T15	0	1207	0	0
T18	12545	1	0	0
T19	25833	6	0	0
T28	0	821	0	0
T43	0	3	0	0
T50	0	209	0	0
T51	0	69	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	359068841	0	0
T1	567964	547416	0	0
T2	22925	17468	0	0
T3	35443	35390	0	0
T4	371309	229632	0	0
T5	142400	134431	0	0
T6	814167	814111	0	0
T7	106044	106037	0	0
T11	373737	2657	0	0
T18	12545	10065	0	0
T19	25833	18816	0	0