Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T6,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T6,T4
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T2,T3

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T4
1	0	Covered	T18,T5,T20

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T18,T5,T20

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21
1	1	Covered	T1,T3,T4

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T6,T18

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T5,T19

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T6,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T4
1	Covered	T1,T3,T4

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T6,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T3,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T3,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T18

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T6
Phase1St	198	Covered	T1,T3,T6
Phase2St	215	Covered	T1,T3,T6
Phase3St	233	Covered	T1,T3,T6
TerminalSt	249	Covered	T1,T3,T6
TimeoutSt	159	Covered	T1,T2,T3

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T6,T4
IdleSt->TimeoutSt	159	Covered	T1,T2,T3
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T1,T22,T23
Phase0St->Phase1St	198	Covered	T1,T3,T6
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T1,T24,T25
Phase1St->Phase2St	215	Covered	T1,T3,T6
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T5,T26,T27
Phase2St->Phase3St	233	Covered	T1,T3,T6
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T15,T28,T29
Phase3St->TerminalSt	249	Covered	T1,T3,T6
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T4,T18
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T1,T2,T4
TimeoutSt->Phase0St	172	Covered	T1,T3,T4

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T22,T23,T30
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T24,T31
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T26,T27
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T15,T28,T29
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T18,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	793	0	0
CheckAccumTrig0_A	2147483647	2341	0	0
CheckAccumTrig1_A	2147483647	109	0	0
CheckClr_A	2147483647	1129	0	0
CheckEn_A	2147483647	1138514063	0	0
CheckPhase0_A	2147483647	2619	0	0
CheckPhase1_A	2147483647	2578	0	0
CheckPhase2_A	2147483647	2527	0	0
CheckPhase3_A	2147483647	2474	0	0
CheckTimeout0_A	2147483647	2914	0	0
CheckTimeoutSt1_A	2147483647	358133	0	0
CheckTimeoutSt2_A	2147483647	2579	0	0
CheckTimeoutStTrig_A	2147483647	220	0	0
ErrorStAllEscAsserted_A	2147483647	4363	0	0
ErrorStIsTerminal_A	2147483647	3523	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	793	0	0
T8	62608	126	0	0
T9	0	241	0	0
T10	0	241	0	0
T32	0	94	0	0
T33	0	91	0	0
T34	1026724	0	0	0
T35	166084	0	0	0
T36	371288	0	0	0
T37	1272720	0	0	0
T38	434864	0	0	0
T39	27152	0	0	0
T40	2982860	0	0	0
T41	247004	0	0	0
T42	965832	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2341	0	0
T1	2271856	25	0	0
T2	91700	0	0	0
T3	141772	0	0	0
T4	1485236	1	0	0
T5	569600	16	0	0
T6	3256668	2	0	0
T7	424176	0	0	0
T11	1494948	3	0	0
T15	0	4	0	0
T16	0	4	0	0
T18	50180	3	0	0
T19	103332	4	0	0
T28	0	4	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	109	0	0
T5	142400	4	0	0
T7	106044	0	0	0
T8	15652	0	0	0
T11	373737	0	0	0
T18	12545	1	0	0
T19	25833	0	0	0
T20	0	2	0	0
T22	0	1	0	0
T24	0	1	0	0
T25	0	2	0	0
T26	0	1	0	0
T34	256681	0	0	0
T35	41521	0	0	0
T36	92822	0	0	0
T37	318180	0	0	0
T38	108716	0	0	0
T39	6788	0	0	0
T40	745715	0	0	0
T43	5015	0	0	0
T44	15966	0	0	0
T45	3552	0	0	0
T46	7054	0	0	0
T52	380640	1	0	0
T53	67931	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	13281	0	0	0
T67	12980	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1129	0	0
T1	1703892	7	0	0
T2	68775	0	0	0
T3	106329	0	0	0
T4	1113927	0	0	0
T5	569600	15	0	0
T6	2442501	0	0	0
T7	318132	0	0	0
T11	1494948	1	0	0
T13	19208	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	37635	1	0	0
T19	103332	0	0	0
T20	0	1	0	0
T24	0	2	0	0
T28	0	5	0	0
T29	0	3	0	0
T31	0	2	0	0
T34	0	4	0	0
T35	0	3	0	0
T43	5015	0	0	0
T44	15966	0	0	0
T45	3552	0	0	0
T46	7054	1	0	0
T47	87990	0	0	0
T49	0	1	0	0
T52	0	3	0	0
T66	13281	0	0	0
T68	0	5	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	3	0	0
T72	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1138514063	0	0
T1	2271856	1029156	0	0
T2	91700	68908	0	0
T3	141772	106962	0	0
T4	1485236	753877	0	0
T5	569600	1116509	0	0
T6	3256668	1761346	0	0
T7	424176	242156	0	0
T11	1494948	757630	0	0
T18	50180	31333	0	0
T19	103332	21507	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2619	0	0
T1	2271856	25	0	0
T2	91700	0	0	0
T3	141772	1	0	0
T4	1485236	3	0	0
T5	569600	25	0	0
T6	3256668	2	0	0
T7	424176	0	0	0
T11	1494948	3	0	0
T15	0	4	0	0
T16	0	2	0	0
T18	50180	4	0	0
T19	103332	4	0	0
T28	0	3	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	2	0	0
T66	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2578	0	0
T1	2271856	23	0	0
T2	91700	0	0	0
T3	141772	1	0	0
T4	1485236	3	0	0
T5	569600	25	0	0
T6	3256668	2	0	0
T7	424176	0	0	0
T11	1494948	3	0	0
T15	0	4	0	0
T16	0	2	0	0
T18	50180	4	0	0
T19	103332	4	0	0
T28	0	3	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	2	0	0
T66	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2527	0	0
T1	2271856	23	0	0
T2	91700	0	0	0
T3	141772	1	0	0
T4	1485236	3	0	0
T5	569600	22	0	0
T6	3256668	2	0	0
T7	424176	0	0	0
T11	1494948	3	0	0
T15	0	4	0	0
T16	0	2	0	0
T18	50180	4	0	0
T19	103332	4	0	0
T28	0	3	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	2	0	0
T66	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2474	0	0
T1	2271856	23	0	0
T2	91700	0	0	0
T3	141772	1	0	0
T4	1485236	3	0	0
T5	569600	22	0	0
T6	3256668	2	0	0
T7	424176	0	0	0
T11	1494948	3	0	0
T15	0	3	0	0
T16	0	2	0	0
T18	50180	4	0	0
T19	103332	4	0	0
T28	0	2	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	2	0	0
T66	0	1	0	0
T68	0	4	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2914	0	0
T1	2271856	22	0	0
T2	91700	4	0	0
T3	141772	1	0	0
T4	1485236	38	0	0
T5	569600	18	0	0
T6	3256668	0	0	0
T7	424176	0	0	0
T11	1494948	0	0	0
T16	0	1	0	0
T18	50180	1	0	0
T19	103332	0	0	0
T20	0	2	0	0
T31	0	1	0	0
T34	0	2	0	0
T35	0	2	0	0
T38	0	1	0	0
T41	0	3	0	0
T44	0	1	0	0
T52	0	33	0	0
T66	0	2	0	0
T68	0	1	0	0
T69	0	3	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	5	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	358133	0	0
T1	2271856	5493	0	0
T2	91700	789	0	0
T3	141772	18	0	0
T4	1485236	5231	0	0
T5	569600	1906	0	0
T6	3256668	0	0	0
T7	424176	0	0	0
T11	1494948	0	0	0
T16	0	45	0	0
T18	50180	5	0	0
T19	103332	0	0	0
T20	0	3	0	0
T31	0	185	0	0
T34	0	88	0	0
T35	0	791	0	0
T38	0	87	0	0
T41	0	449	0	0
T44	0	107	0	0
T52	0	4816	0	0
T66	0	836	0	0
T68	0	802	0	0
T69	0	603	0	0
T72	0	96	0	0
T73	0	421	0	0
T74	0	485	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2579	0	0
T1	2271856	19	0	0
T2	91700	4	0	0
T3	141772	0	0	0
T4	1485236	36	0	0
T5	569600	9	0	0
T6	3256668	0	0	0
T7	424176	0	0	0
T11	1494948	0	0	0
T16	0	1	0	0
T18	50180	0	0	0
T19	103332	0	0	0
T24	0	1	0	0
T31	0	1	0	0
T34	0	2	0	0
T35	0	1	0	0
T38	0	1	0	0
T41	0	3	0	0
T44	0	1	0	0
T52	0	32	0	0
T66	0	1	0	0
T69	0	3	0	0
T72	0	1	0	0
T73	0	2	0	0
T74	0	7	0	0
T75	0	2	0	0
T76	0	2	0	0
T77	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	220	0	0
T1	1135928	2	0	0
T2	45850	0	0	0
T3	70886	1	0	0
T4	1113927	1	0	0
T5	569600	5	0	0
T6	1628334	0	0	0
T7	318132	0	0	0
T11	1494948	0	0	0
T13	19208	0	0	0
T18	37635	0	0	0
T19	103332	0	0	0
T30	0	1	0	0
T35	0	1	0	0
T43	10030	0	0	0
T44	31932	0	0	0
T45	7104	0	0	0
T46	7054	0	0	0
T47	87990	0	0	0
T54	0	2	0	0
T58	0	2	0	0
T66	26562	1	0	0
T69	0	1	0	0
T72	0	3	0	0
T73	0	1	0	0
T74	0	1	0	0
T77	0	4	0	0
T78	0	2	0	0
T79	0	1	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	3	0	0
T83	0	2	0	0
T84	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4363	0	0
T8	62608	637	0	0
T9	0	1287	0	0
T10	0	1225	0	0
T32	0	638	0	0
T33	0	576	0	0
T34	1026724	0	0	0
T35	166084	0	0	0
T36	371288	0	0	0
T37	1272720	0	0	0
T38	434864	0	0	0
T39	27152	0	0	0
T40	2982860	0	0	0
T41	247004	0	0	0
T42	965832	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3523	0	0
T8	62608	517	0	0
T9	0	1047	0	0
T10	0	985	0	0
T32	0	518	0	0
T33	0	456	0	0
T34	1026724	0	0	0
T35	166084	0	0	0
T36	371288	0	0	0
T37	1272720	0	0	0
T38	434864	0	0	0
T39	27152	0	0	0
T40	2982860	0	0	0
T41	247004	0	0	0
T42	965832	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2271856	2271812	0	0
T2	91700	91412	0	0
T3	141772	141560	0	0
T4	1485236	1483376	0	0
T5	569600	569336	0	0
T6	3256668	3256444	0	0
T7	424176	424148	0	0
T11	1494948	1494928	0	0
T18	50180	49888	0	0
T19	103332	103116	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2271856	2271812	0	0
T2	91700	91412	0	0
T3	141772	141560	0	0
T4	1485236	1483376	0	0
T5	569600	569336	0	0
T6	3256668	3256444	0	0
T7	424176	424148	0	0
T11	1494948	1494928	0	0
T18	50180	49888	0	0
T19	103332	103116	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T2,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T4,T35,T72
1	0	Covered	T52,T54,T56

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T52,T54,T56

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T4,T35,T72

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T68,T52,T35

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T5,T19,T38

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T15

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T19
1	Covered	T1,T4,T11

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T4,T5
Phase1St	198	Covered	T1,T4,T5
Phase2St	215	Covered	T1,T4,T5
Phase3St	233	Covered	T1,T4,T5
TerminalSt	249	Covered	T1,T4,T5
TimeoutSt	159	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T4,T5
IdleSt->TimeoutSt	159	Covered	T1,T2,T4
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T85,T25,T56
Phase0St->Phase1St	198	Covered	T1,T4,T5
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T1,T56,T86
Phase1St->Phase2St	215	Covered	T1,T4,T5
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T87,T88,T89
Phase2St->Phase3St	233	Covered	T1,T4,T5
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T15,T28,T29
Phase3St->TerminalSt	249	Covered	T1,T4,T5
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T4,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T2,T4
TimeoutSt->Phase0St	172	Covered	T4,T52,T35

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T52,T35
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T85,T25,T90
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T5
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T5
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T56,T86,T91
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T5
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T5
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T87,T88,T89
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T5
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T15,T28,T29
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T5
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T5,T68,T70
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T5
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	660610922	211	0	0
CheckAccumTrig0_A	660610922	471	0	0
CheckAccumTrig1_A	660610922	20	0	0
CheckClr_A	660610922	204	0	0
CheckEn_A	660481657	309931166	0	0
CheckPhase0_A	660610922	528	0	0
CheckPhase1_A	660610922	519	0	0
CheckPhase2_A	660610922	511	0	0
CheckPhase3_A	660610922	502	0	0
CheckTimeout0_A	660610922	399	0	0
CheckTimeoutSt1_A	660610922	52494	0	0
CheckTimeoutSt2_A	660610922	330	0	0
CheckTimeoutStTrig_A	660610922	47	0	0
ErrorStAllEscAsserted_A	660610922	1139	0	0
ErrorStIsTerminal_A	660610922	929	0	0
EscStateOut_A	660481012	660412814	0	0
u_state_regs_A	660610922	660453283	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	211	0	0
T8	15652	36	0	0
T9	0	72	0	0
T10	0	62	0	0
T32	0	14	0	0
T33	0	27	0	0
T34	256681	0	0	0
T35	41521	0	0	0
T36	92822	0	0	0
T37	318180	0	0	0
T38	108716	0	0	0
T39	6788	0	0	0
T40	745715	0	0	0
T41	61751	0	0	0
T42	241458	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	471	0	0
T1	567964	3	0	0
T2	22925	0	0	0
T3	35443	0	0	0
T4	371309	1	0	0
T5	142400	4	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	1	0	0
T15	0	2	0	0
T16	0	1	0	0
T18	12545	0	0	0
T19	25833	1	0	0
T28	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	20	0	0
T8	15652	0	0	0
T34	256681	0	0	0
T35	41521	0	0	0
T36	92822	0	0	0
T37	318180	0	0	0
T38	108716	0	0	0
T39	6788	0	0	0
T40	745715	0	0	0
T52	380640	1	0	0
T54	0	1	0	0
T56	0	2	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	2	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T67	12980	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	204	0	0
T5	142400	2	0	0
T11	373737	0	0	0
T13	19208	0	0	0
T15	0	1	0	0
T19	25833	0	0	0
T24	0	1	0	0
T28	0	1	0	0
T29	0	3	0	0
T31	0	1	0	0
T43	5015	0	0	0
T44	15966	0	0	0
T45	3552	0	0	0
T46	7054	0	0	0
T47	87990	0	0	0
T66	13281	0	0	0
T68	0	3	0	0
T70	0	1	0	0
T71	0	1	0	0
T72	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660481657	309931166	0	0
T1	567964	202720	0	0
T2	22925	19506	0	0
T3	35443	35389	0	0
T4	371309	54132	0	0
T5	142400	439653	0	0
T6	814167	814110	0	0
T7	106044	31802	0	0
T11	373737	7511	0	0
T18	12545	12471	0	0
T19	25833	3207	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	528	0	0
T1	567964	3	0	0
T2	22925	0	0	0
T3	35443	0	0	0
T4	371309	2	0	0
T5	142400	4	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	1	0	0
T15	0	2	0	0
T16	0	1	0	0
T18	12545	0	0	0
T19	25833	1	0	0
T28	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	519	0	0
T1	567964	2	0	0
T2	22925	0	0	0
T3	35443	0	0	0
T4	371309	2	0	0
T5	142400	4	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	1	0	0
T15	0	2	0	0
T16	0	1	0	0
T18	12545	0	0	0
T19	25833	1	0	0
T28	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	511	0	0
T1	567964	2	0	0
T2	22925	0	0	0
T3	35443	0	0	0
T4	371309	2	0	0
T5	142400	4	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	1	0	0
T15	0	2	0	0
T16	0	1	0	0
T18	12545	0	0	0
T19	25833	1	0	0
T28	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	502	0	0
T1	567964	2	0	0
T2	22925	0	0	0
T3	35443	0	0	0
T4	371309	2	0	0
T5	142400	4	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	12545	0	0	0
T19	25833	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T68	0	4	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	399	0	0
T1	567964	1	0	0
T2	22925	1	0	0
T3	35443	0	0	0
T4	371309	9	0	0
T5	142400	0	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T18	12545	0	0	0
T19	25833	0	0	0
T31	0	1	0	0
T35	0	1	0	0
T41	0	1	0	0
T52	0	19	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	52494	0	0
T1	567964	257	0	0
T2	22925	203	0	0
T3	35443	0	0	0
T4	371309	1173	0	0
T5	142400	0	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T18	12545	0	0	0
T19	25833	0	0	0
T31	0	185	0	0
T35	0	753	0	0
T41	0	150	0	0
T52	0	3238	0	0
T72	0	96	0	0
T73	0	210	0	0
T74	0	111	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	330	0	0
T1	567964	1	0	0
T2	22925	1	0	0
T3	35443	0	0	0
T4	371309	8	0	0
T5	142400	0	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T18	12545	0	0	0
T19	25833	0	0	0
T31	0	1	0	0
T41	0	1	0	0
T52	0	18	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	47	0	0
T4	371309	1	0	0
T5	142400	0	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T18	12545	0	0	0
T19	25833	0	0	0
T35	0	1	0	0
T43	5015	0	0	0
T44	15966	0	0	0
T45	3552	0	0	0
T54	0	2	0	0
T58	0	1	0	0
T66	13281	0	0	0
T72	0	1	0	0
T74	0	1	0	0
T79	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	2	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	1139	0	0
T8	15652	151	0	0
T9	0	324	0	0
T10	0	312	0	0
T32	0	184	0	0
T33	0	168	0	0
T34	256681	0	0	0
T35	41521	0	0	0
T36	92822	0	0	0
T37	318180	0	0	0
T38	108716	0	0	0
T39	6788	0	0	0
T40	745715	0	0	0
T41	61751	0	0	0
T42	241458	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	929	0	0
T8	15652	121	0	0
T9	0	264	0	0
T10	0	252	0	0
T32	0	154	0	0
T33	0	138	0	0
T34	256681	0	0	0
T35	41521	0	0	0
T36	92822	0	0	0
T37	318180	0	0	0
T38	108716	0	0	0
T39	6788	0	0	0
T40	745715	0	0	0
T41	61751	0	0	0
T42	241458	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660481012	660412814	0	0
T1	567964	567953	0	0
T2	22925	22853	0	0
T3	35443	35390	0	0
T4	371309	370844	0	0
T5	142400	142334	0	0
T6	814167	814111	0	0
T7	106044	106037	0	0
T11	373737	373732	0	0
T18	12545	12472	0	0
T19	25833	25779	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	660453283	0	0
T1	567964	567953	0	0
T2	22925	22853	0	0
T3	35443	35390	0	0
T4	371309	370844	0	0
T5	142400	142334	0	0
T6	814167	814111	0	0
T7	106044	106037	0	0
T11	373737	373732	0	0
T18	12545	12472	0	0
T19	25833	25779	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T6,T18

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T4,T7
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T2,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T5,T66,T69
1	0	Covered	T53,T92,T25

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T53,T92,T25

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T5,T66,T69

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T5
1	Covered	T1,T18,T5

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T18
1	Covered	T1,T5,T48

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T18,T5
1	Covered	T1,T6,T66

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T18
1	Covered	T1,T34,T35

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T6,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T18,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T6,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T18,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T6,T18
Phase1St	198	Covered	T1,T6,T18
Phase2St	215	Covered	T1,T6,T18
Phase3St	233	Covered	T1,T6,T18
TerminalSt	249	Covered	T1,T6,T18
TimeoutSt	159	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T6,T18
IdleSt->TimeoutSt	159	Covered	T1,T2,T4
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T1,T30,T93
Phase0St->Phase1St	198	Covered	T1,T6,T18
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T1,T86,T94
Phase1St->Phase2St	215	Covered	T1,T6,T18
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T26,T27,T95
Phase2St->Phase3St	233	Covered	T1,T6,T18
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T26,T96,T97
Phase3St->TerminalSt	249	Covered	T1,T6,T18
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T18,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T2,T4
TimeoutSt->Phase0St	172	Covered	T5,T66,T69

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T18
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T66,T69
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T30,T93,T98
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T6,T18
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T6,T18
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T1,T86,T94
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T6,T18
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T6,T18
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T26,T27,T95
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T6,T18
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T6,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T26,T96,T97
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T6,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T6,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T18,T49
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T6,T18
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	660610922	179	0	0
CheckAccumTrig0_A	660610922	480	0	0
CheckAccumTrig1_A	660610922	21	0	0
CheckClr_A	660610922	230	0	0
CheckEn_A	660481657	282449620	0	0
CheckPhase0_A	660610922	562	0	0
CheckPhase1_A	660610922	556	0	0
CheckPhase2_A	660610922	548	0	0
CheckPhase3_A	660610922	534	0	0
CheckTimeout0_A	660610922	725	0	0
CheckTimeoutSt1_A	660610922	97831	0	0
CheckTimeoutSt2_A	660610922	634	0	0
CheckTimeoutStTrig_A	660610922	70	0	0
ErrorStAllEscAsserted_A	660610922	1050	0	0
ErrorStIsTerminal_A	660610922	840	0	0
EscStateOut_A	660481012	660412814	0	0
u_state_regs_A	660610922	660453283	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	179	0	0
T8	15652	19	0	0
T9	0	60	0	0
T10	0	46	0	0
T32	0	21	0	0
T33	0	33	0	0
T34	256681	0	0	0
T35	41521	0	0	0
T36	92822	0	0	0
T37	318180	0	0	0
T38	108716	0	0	0
T39	6788	0	0	0
T40	745715	0	0	0
T41	61751	0	0	0
T42	241458	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	480	0	0
T1	567964	8	0	0
T2	22925	0	0	0
T3	35443	0	0	0
T4	371309	0	0	0
T5	142400	1	0	0
T6	814167	1	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	12545	2	0	0
T19	25833	1	0	0
T28	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	21	0	0
T25	0	1	0	0
T30	26407	0	0	0
T53	67931	1	0	0
T74	24240	0	0	0
T75	114111	0	0	0
T92	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	2	0	0
T102	0	1	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	386544	0	0	0
T107	100143	0	0	0
T108	246389	0	0	0
T109	1137	0	0	0
T110	99802	0	0	0
T111	128419	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	230	0	0
T1	567964	2	0	0
T2	22925	0	0	0
T3	35443	0	0	0
T4	371309	0	0	0
T5	142400	0	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T18	12545	1	0	0
T19	25833	0	0	0
T24	0	1	0	0
T28	0	1	0	0
T34	0	1	0	0
T35	0	2	0	0
T49	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T71	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660481657	282449620	0	0
T1	567964	138349	0	0
T2	22925	9083	0	0
T3	35443	35389	0	0
T4	371309	215505	0	0
T5	142400	126523	0	0
T6	814167	2153	0	0
T7	106044	2677	0	0
T11	373737	373731	0	0
T18	12545	2491	0	0
T19	25833	7704	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	562	0	0
T1	567964	7	0	0
T2	22925	0	0	0
T3	35443	0	0	0
T4	371309	0	0	0
T5	142400	2	0	0
T6	814167	1	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	12545	2	0	0
T19	25833	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T66	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	556	0	0
T1	567964	6	0	0
T2	22925	0	0	0
T3	35443	0	0	0
T4	371309	0	0	0
T5	142400	2	0	0
T6	814167	1	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	12545	2	0	0
T19	25833	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T66	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	548	0	0
T1	567964	6	0	0
T2	22925	0	0	0
T3	35443	0	0	0
T4	371309	0	0	0
T5	142400	2	0	0
T6	814167	1	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	12545	2	0	0
T19	25833	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T66	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	534	0	0
T1	567964	6	0	0
T2	22925	0	0	0
T3	35443	0	0	0
T4	371309	0	0	0
T5	142400	2	0	0
T6	814167	1	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T18	12545	2	0	0
T19	25833	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T66	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	725	0	0
T1	567964	5	0	0
T2	22925	2	0	0
T3	35443	0	0	0
T4	371309	11	0	0
T5	142400	2	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T18	12545	0	0	0
T19	25833	0	0	0
T35	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T52	0	12	0	0
T66	0	1	0	0
T69	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	97831	0	0
T1	567964	1346	0	0
T2	22925	396	0	0
T3	35443	0	0	0
T4	371309	1578	0	0
T5	142400	760	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T18	12545	0	0	0
T19	25833	0	0	0
T35	0	38	0	0
T38	0	87	0	0
T41	0	119	0	0
T52	0	1316	0	0
T66	0	367	0	0
T69	0	603	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	634	0	0
T1	567964	5	0	0
T2	22925	2	0	0
T3	35443	0	0	0
T4	371309	11	0	0
T5	142400	1	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T18	12545	0	0	0
T19	25833	0	0	0
T35	0	1	0	0
T38	0	1	0	0
T41	0	1	0	0
T52	0	12	0	0
T69	0	2	0	0
T72	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	70	0	0
T5	142400	1	0	0
T11	373737	0	0	0
T13	19208	0	0	0
T19	25833	0	0	0
T30	0	1	0	0
T43	5015	0	0	0
T44	15966	0	0	0
T45	3552	0	0	0
T46	7054	0	0	0
T47	87990	0	0	0
T66	13281	1	0	0
T69	0	1	0	0
T73	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0
T80	0	1	0	0
T82	0	1	0	0
T112	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	1050	0	0
T8	15652	157	0	0
T9	0	344	0	0
T10	0	273	0	0
T32	0	145	0	0
T33	0	131	0	0
T34	256681	0	0	0
T35	41521	0	0	0
T36	92822	0	0	0
T37	318180	0	0	0
T38	108716	0	0	0
T39	6788	0	0	0
T40	745715	0	0	0
T41	61751	0	0	0
T42	241458	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	840	0	0
T8	15652	127	0	0
T9	0	284	0	0
T10	0	213	0	0
T32	0	115	0	0
T33	0	101	0	0
T34	256681	0	0	0
T35	41521	0	0	0
T36	92822	0	0	0
T37	318180	0	0	0
T38	108716	0	0	0
T39	6788	0	0	0
T40	745715	0	0	0
T41	61751	0	0	0
T42	241458	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660481012	660412814	0	0
T1	567964	567953	0	0
T2	22925	22853	0	0
T3	35443	35390	0	0
T4	371309	370844	0	0
T5	142400	142334	0	0
T6	814167	814111	0	0
T7	106044	106037	0	0
T11	373737	373732	0	0
T18	12545	12472	0	0
T19	25833	25779	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	660453283	0	0
T1	567964	567953	0	0
T2	22925	22853	0	0
T3	35443	35390	0	0
T4	371309	370844	0	0
T5	142400	142334	0	0
T6	814167	814111	0	0
T7	106044	106037	0	0
T11	373737	373732	0	0
T18	12545	12472	0	0
T19	25833	25779	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T4
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T4

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T18,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T4
1	0	1	Covered	T1,T4,T5
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T2,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T4
0	1	Covered	T1,T4,T68
1	0	Covered	T92,T96,T113

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T92,T96,T113

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T4
1	0	Not Covered
1	1	Covered	T1,T4,T68

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T18
1	Covered	T43,T52,T34

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T18
1	Covered	T1,T68,T51

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T5,T11
1	Covered	T1,T4,T18

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T4,T18
1	Covered	T1,T5,T11

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T18,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T5,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T18,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T4,T18
Phase1St	198	Covered	T1,T4,T18
Phase2St	215	Covered	T1,T4,T18
Phase3St	233	Covered	T1,T4,T18
TerminalSt	249	Covered	T1,T4,T18
TimeoutSt	159	Covered	T1,T2,T4

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T18,T5
IdleSt->TimeoutSt	159	Covered	T1,T2,T4
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T1,T80,T58
Phase0St->Phase1St	198	Covered	T1,T4,T18
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T31,T89,T114
Phase1St->Phase2St	215	Covered	T1,T4,T18
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T115,T86,T89
Phase2St->Phase3St	233	Covered	T1,T4,T18
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T85,T54,T56
Phase3St->TerminalSt	249	Covered	T1,T4,T18
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T4,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T2,T4
TimeoutSt->Phase0St	172	Covered	T1,T4,T68

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T18,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T68
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T98,T116,T105
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T4,T18
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T4,T18
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T31,T89,T114
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T4,T18
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T4,T18
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T115,T86,T114
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T4,T18
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T4,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T85,T54,T56
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T4,T18
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T4,T18
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T5,T11
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T4,T18
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	660610922	200	0	0
CheckAccumTrig0_A	660610922	535	0	0
CheckAccumTrig1_A	660610922	13	0	0
CheckClr_A	660610922	245	0	0
CheckEn_A	660481657	284287234	0	0
CheckPhase0_A	660610922	580	0	0
CheckPhase1_A	660610922	569	0	0
CheckPhase2_A	660610922	556	0	0
CheckPhase3_A	660610922	547	0	0
CheckTimeout0_A	660610922	887	0	0
CheckTimeoutSt1_A	660610922	104840	0	0
CheckTimeoutSt2_A	660610922	831	0	0
CheckTimeoutStTrig_A	660610922	41	0	0
ErrorStAllEscAsserted_A	660610922	1039	0	0
ErrorStIsTerminal_A	660610922	829	0	0
EscStateOut_A	660481012	660412814	0	0
u_state_regs_A	660610922	660453283	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	200	0	0
T8	15652	39	0	0
T9	0	61	0	0
T10	0	67	0	0
T32	0	16	0	0
T33	0	17	0	0
T34	256681	0	0	0
T35	41521	0	0	0
T36	92822	0	0	0
T37	318180	0	0	0
T38	108716	0	0	0
T39	6788	0	0	0
T40	745715	0	0	0
T41	61751	0	0	0
T42	241458	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	535	0	0
T1	567964	6	0	0
T2	22925	0	0	0
T3	35443	0	0	0
T4	371309	0	0	0
T5	142400	2	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	2	0	0
T15	0	1	0	0
T18	12545	1	0	0
T19	25833	1	0	0
T28	0	2	0	0
T43	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	13	0	0
T81	82949	0	0	0
T82	276251	0	0	0
T92	399782	1	0	0
T96	0	1	0	0
T105	0	2	0	0
T112	24320	0	0	0
T113	0	1	0	0
T117	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	0	2	0	0
T122	0	1	0	0
T123	478310	0	0	0
T124	33625	0	0	0
T125	690677	0	0	0
T126	196940	0	0	0
T127	221343	0	0	0
T128	44181	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	245	0	0
T1	567964	3	0	0
T2	22925	0	0	0
T3	35443	0	0	0
T4	371309	0	0	0
T5	142400	1	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	1	0	0
T18	12545	0	0	0
T19	25833	0	0	0
T28	0	1	0	0
T31	0	1	0	0
T34	0	1	0	0
T43	0	1	0	0
T52	0	2	0	0
T71	0	1	0	0
T129	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660481657	284287234	0	0
T1	567964	520564	0	0
T2	22925	17467	0	0
T3	35443	35389	0	0
T4	371309	229630	0	0
T5	142400	447869	0	0
T6	814167	814110	0	0
T7	106044	106037	0	0
T11	373737	2657	0	0
T18	12545	10065	0	0
T19	25833	7393	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	580	0	0
T1	567964	6	0	0
T2	22925	0	0	0
T3	35443	0	0	0
T4	371309	1	0	0
T5	142400	2	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	2	0	0
T15	0	1	0	0
T18	12545	1	0	0
T19	25833	1	0	0
T28	0	2	0	0
T43	0	1	0	0
T50	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	569	0	0
T1	567964	6	0	0
T2	22925	0	0	0
T3	35443	0	0	0
T4	371309	1	0	0
T5	142400	2	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	2	0	0
T15	0	1	0	0
T18	12545	1	0	0
T19	25833	1	0	0
T28	0	2	0	0
T43	0	1	0	0
T50	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	556	0	0
T1	567964	6	0	0
T2	22925	0	0	0
T3	35443	0	0	0
T4	371309	1	0	0
T5	142400	2	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	2	0	0
T15	0	1	0	0
T18	12545	1	0	0
T19	25833	1	0	0
T28	0	2	0	0
T43	0	1	0	0
T50	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	547	0	0
T1	567964	6	0	0
T2	22925	0	0	0
T3	35443	0	0	0
T4	371309	1	0	0
T5	142400	2	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	2	0	0
T15	0	1	0	0
T18	12545	1	0	0
T19	25833	1	0	0
T28	0	2	0	0
T43	0	1	0	0
T50	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	887	0	0
T1	567964	3	0	0
T2	22925	1	0	0
T3	35443	0	0	0
T4	371309	6	0	0
T5	142400	1	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T16	0	1	0	0
T18	12545	0	0	0
T19	25833	0	0	0
T41	0	1	0	0
T68	0	1	0	0
T73	0	1	0	0
T74	0	3	0	0
T75	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	104840	0	0
T1	567964	717	0	0
T2	22925	190	0	0
T3	35443	0	0	0
T4	371309	683	0	0
T5	142400	3	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T16	0	45	0	0
T18	12545	0	0	0
T19	25833	0	0	0
T41	0	180	0	0
T68	0	802	0	0
T73	0	211	0	0
T74	0	374	0	0
T75	0	67	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	831	0	0
T1	567964	2	0	0
T2	22925	1	0	0
T3	35443	0	0	0
T4	371309	5	0	0
T5	142400	1	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T16	0	1	0	0
T18	12545	0	0	0
T19	25833	0	0	0
T41	0	1	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	1	0	0
T77	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	41	0	0
T1	567964	1	0	0
T2	22925	0	0	0
T3	35443	0	0	0
T4	371309	1	0	0
T5	142400	0	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T18	12545	0	0	0
T19	25833	0	0	0
T25	0	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T68	0	1	0	0
T74	0	1	0	0
T124	0	2	0	0
T130	0	1	0	0
T131	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	1039	0	0
T8	15652	165	0	0
T9	0	279	0	0
T10	0	321	0	0
T32	0	141	0	0
T33	0	133	0	0
T34	256681	0	0	0
T35	41521	0	0	0
T36	92822	0	0	0
T37	318180	0	0	0
T38	108716	0	0	0
T39	6788	0	0	0
T40	745715	0	0	0
T41	61751	0	0	0
T42	241458	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	829	0	0
T8	15652	135	0	0
T9	0	219	0	0
T10	0	261	0	0
T32	0	111	0	0
T33	0	103	0	0
T34	256681	0	0	0
T35	41521	0	0	0
T36	92822	0	0	0
T37	318180	0	0	0
T38	108716	0	0	0
T39	6788	0	0	0
T40	745715	0	0	0
T41	61751	0	0	0
T42	241458	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660481012	660412814	0	0
T1	567964	567953	0	0
T2	22925	22853	0	0
T3	35443	35390	0	0
T4	371309	370844	0	0
T5	142400	142334	0	0
T6	814167	814111	0	0
T7	106044	106037	0	0
T11	373737	373732	0	0
T18	12545	12472	0	0
T19	25833	25779	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	660453283	0	0
T1	567964	567953	0	0
T2	22925	22853	0	0
T3	35443	35390	0	0
T4	371309	370844	0	0
T5	142400	142334	0	0
T6	814167	814111	0	0
T7	106044	106037	0	0
T11	373737	373732	0	0
T18	12545	12472	0	0
T19	25833	25779	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T3,T6
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T6

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T6
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T6,T5

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T3,T4
1	0	1	Covered	T1,T6,T4
1	1	0	Covered	T1,T2,T4
1	1	1	Covered	T1,T3,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T4
0	1	Covered	T1,T3,T5
1	0	Covered	T18,T5,T20

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T3,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T18,T5,T20

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Covered	T21
1	1	Covered	T1,T3,T5

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T5
1	Covered	T1,T6,T18

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T1,T5,T47

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T6
1	Covered	T5,T44,T52

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T6,T18
1	Covered	T1,T3,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T6,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T3,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T3,T6

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T18,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T3,T6
Phase1St	198	Covered	T1,T3,T6
Phase2St	215	Covered	T1,T3,T6
Phase3St	233	Covered	T1,T3,T6
TerminalSt	249	Covered	T1,T3,T6
TimeoutSt	159	Covered	T1,T3,T4

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T6,T5
IdleSt->TimeoutSt	159	Covered	T1,T3,T4
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T1,T22,T23
Phase0St->Phase1St	198	Covered	T1,T3,T6
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T24,T25,T27
Phase1St->Phase2St	215	Covered	T1,T3,T6
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T5,T26,T132
Phase2St->Phase3St	233	Covered	T1,T3,T6
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T24,T85,T133
Phase3St->TerminalSt	249	Covered	T1,T3,T6
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T5,T46
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T1,T4,T5
TimeoutSt->Phase0St	172	Covered	T1,T3,T18

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T6,T5
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T18
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T4,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T22,T23,T55
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T3,T6
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T3,T6
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T24,T25,T27
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T3,T6
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T3,T6
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T26,T132
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T3,T6
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T24,T85,T133
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T3,T6
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T3,T6
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T5,T46
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T3,T6
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	660610922	203	0	0
CheckAccumTrig0_A	660610922	855	0	0
CheckAccumTrig1_A	660610922	55	0	0
CheckClr_A	660610922	450	0	0
CheckEn_A	660481657	261846043	0	0
CheckPhase0_A	660610922	949	0	0
CheckPhase1_A	660610922	934	0	0
CheckPhase2_A	660610922	912	0	0
CheckPhase3_A	660610922	891	0	0
CheckTimeout0_A	660610922	903	0	0
CheckTimeoutSt1_A	660610922	102968	0	0
CheckTimeoutSt2_A	660610922	784	0	0
CheckTimeoutStTrig_A	660610922	62	0	0
ErrorStAllEscAsserted_A	660610922	1135	0	0
ErrorStIsTerminal_A	660610922	925	0	0
EscStateOut_A	660481012	660412814	0	0
u_state_regs_A	660610922	660453283	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	203	0	0
T8	15652	32	0	0
T9	0	48	0	0
T10	0	66	0	0
T32	0	43	0	0
T33	0	14	0	0
T34	256681	0	0	0
T35	41521	0	0	0
T36	92822	0	0	0
T37	318180	0	0	0
T38	108716	0	0	0
T39	6788	0	0	0
T40	745715	0	0	0
T41	61751	0	0	0
T42	241458	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	855	0	0
T1	567964	8	0	0
T2	22925	0	0	0
T3	35443	0	0	0
T4	371309	0	0	0
T5	142400	9	0	0
T6	814167	1	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T16	0	2	0	0
T18	12545	0	0	0
T19	25833	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	55	0	0
T5	142400	4	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T18	12545	1	0	0
T19	25833	0	0	0
T20	0	2	0	0
T22	0	1	0	0
T24	0	1	0	0
T25	0	1	0	0
T26	0	1	0	0
T43	5015	0	0	0
T44	15966	0	0	0
T45	3552	0	0	0
T46	7054	0	0	0
T55	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T66	13281	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	450	0	0
T1	567964	2	0	0
T2	22925	0	0	0
T3	35443	0	0	0
T4	371309	0	0	0
T5	142400	12	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T16	0	1	0	0
T18	12545	0	0	0
T19	25833	0	0	0
T20	0	1	0	0
T28	0	2	0	0
T34	0	2	0	0
T35	0	1	0	0
T46	0	1	0	0
T52	0	1	0	0
T68	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660481657	261846043	0	0
T1	567964	167523	0	0
T2	22925	22852	0	0
T3	35443	795	0	0
T4	371309	254610	0	0
T5	142400	102464	0	0
T6	814167	130973	0	0
T7	106044	101640	0	0
T11	373737	373731	0	0
T18	12545	6306	0	0
T19	25833	3203	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	949	0	0
T1	567964	9	0	0
T2	22925	0	0	0
T3	35443	1	0	0
T4	371309	0	0	0
T5	142400	17	0	0
T6	814167	1	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T18	12545	1	0	0
T19	25833	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	934	0	0
T1	567964	9	0	0
T2	22925	0	0	0
T3	35443	1	0	0
T4	371309	0	0	0
T5	142400	17	0	0
T6	814167	1	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T18	12545	1	0	0
T19	25833	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	912	0	0
T1	567964	9	0	0
T2	22925	0	0	0
T3	35443	1	0	0
T4	371309	0	0	0
T5	142400	14	0	0
T6	814167	1	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T18	12545	1	0	0
T19	25833	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	891	0	0
T1	567964	9	0	0
T2	22925	0	0	0
T3	35443	1	0	0
T4	371309	0	0	0
T5	142400	14	0	0
T6	814167	1	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T18	12545	1	0	0
T19	25833	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	903	0	0
T1	567964	13	0	0
T2	22925	0	0	0
T3	35443	1	0	0
T4	371309	12	0	0
T5	142400	15	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T18	12545	1	0	0
T19	25833	0	0	0
T20	0	2	0	0
T34	0	2	0	0
T44	0	1	0	0
T52	0	2	0	0
T66	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	102968	0	0
T1	567964	3173	0	0
T2	22925	0	0	0
T3	35443	18	0	0
T4	371309	1797	0	0
T5	142400	1143	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T18	12545	5	0	0
T19	25833	0	0	0
T20	0	3	0	0
T34	0	88	0	0
T44	0	107	0	0
T52	0	262	0	0
T66	0	469	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	784	0	0
T1	567964	11	0	0
T2	22925	0	0	0
T3	35443	0	0	0
T4	371309	12	0	0
T5	142400	7	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T18	12545	0	0	0
T19	25833	0	0	0
T24	0	1	0	0
T34	0	2	0	0
T44	0	1	0	0
T52	0	2	0	0
T66	0	1	0	0
T69	0	1	0	0
T74	0	4	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	62	0	0
T1	567964	2	0	0
T2	22925	0	0	0
T3	35443	1	0	0
T4	371309	0	0	0
T5	142400	4	0	0
T6	814167	0	0	0
T7	106044	0	0	0
T11	373737	0	0	0
T18	12545	0	0	0
T19	25833	0	0	0
T58	0	1	0	0
T72	0	2	0	0
T77	0	2	0	0
T78	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0
T83	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	1135	0	0
T8	15652	164	0	0
T9	0	340	0	0
T10	0	319	0	0
T32	0	168	0	0
T33	0	144	0	0
T34	256681	0	0	0
T35	41521	0	0	0
T36	92822	0	0	0
T37	318180	0	0	0
T38	108716	0	0	0
T39	6788	0	0	0
T40	745715	0	0	0
T41	61751	0	0	0
T42	241458	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	925	0	0
T8	15652	134	0	0
T9	0	280	0	0
T10	0	259	0	0
T32	0	138	0	0
T33	0	114	0	0
T34	256681	0	0	0
T35	41521	0	0	0
T36	92822	0	0	0
T37	318180	0	0	0
T38	108716	0	0	0
T39	6788	0	0	0
T40	745715	0	0	0
T41	61751	0	0	0
T42	241458	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660481012	660412814	0	0
T1	567964	567953	0	0
T2	22925	22853	0	0
T3	35443	35390	0	0
T4	371309	370844	0	0
T5	142400	142334	0	0
T6	814167	814111	0	0
T7	106044	106037	0	0
T11	373737	373732	0	0
T18	12545	12472	0	0
T19	25833	25779	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	660610922	660453283	0	0
T1	567964	567953	0	0
T2	22925	22853	0	0
T3	35443	35390	0	0
T4	371309	370844	0	0
T5	142400	142334	0	0
T6	814167	814111	0	0
T7	106044	106037	0	0
T11	373737	373732	0	0
T18	12545	12472	0	0
T19	25833	25779	0	0