Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	127244	1			T4	2536		T6	3		T43	41
class_i[0x1]	51488	1			T1	1		T4	2364		T8	3
class_i[0x2]	75513	1			T8	1		T6	193		T43	262
class_i[0x3]	63997	1			T1	5		T4	4179		T6	108

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	78844	1			T1	1		T4	2166		T8	1
alert[0x1]	82654	1			T1	1		T4	2570		T6	123
alert[0x2]	75597	1			T1	3		T4	2223		T8	2
alert[0x3]	81147	1			T1	1		T4	2120		T8	1

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

317942

1

T1

1

T4

9079

T8

1

esc_ping_fail

300

1

T1

5

T8

3

T16

5

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	78756	1			T4	2166		T6	142		T43	4
esc_integrity_fail	alert[0x1]	82585	1			T4	2570		T6	123		T43	268
esc_integrity_fail	alert[0x2]	75523	1			T1	1		T4	2223		T8	1
esc_integrity_fail	alert[0x3]	81078	1			T4	2120		T6	97		T43	11
esc_ping_fail	alert[0x0]	88	1			T1	1		T8	1		T16	1
esc_ping_fail	alert[0x1]	69	1			T1	1		T16	1		T19	2
esc_ping_fail	alert[0x2]	74	1			T1	2		T8	1		T16	1
esc_ping_fail	alert[0x3]	69	1			T1	1		T8	1		T16	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	127210	1			T4	2536		T6	3		T43	41
esc_integrity_fail	class_i[0x1]	51355	1			T1	1		T4	2364		T6	181
esc_integrity_fail	class_i[0x2]	75466	1			T8	1		T6	193		T43	262
esc_integrity_fail	class_i[0x3]	63911	1			T4	4179		T6	108		T43	2
esc_ping_fail	class_i[0x0]	34	1			T297	2		T182	2		T301	2
esc_ping_fail	class_i[0x1]	133	1			T8	3		T16	1		T66	4
esc_ping_fail	class_i[0x2]	47	1			T16	1		T19	8		T297	4
esc_ping_fail	class_i[0x3]	86	1			T1	5		T16	3		T69	9