Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	680599942	0	0	623
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	680599942	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	680599942	680415214	0	0
tb.dut.CheckAccuCntDw	0	0	623	623	0	0
tb.dut.CheckEscCntDw	0	0	623	623	0	0
tb.dut.CheckNAlerts	0	0	623	623	0	0
tb.dut.CheckNClasses	0	0	623	623	0	0
tb.dut.CheckNEscSev	0	0	623	623	0	0
tb.dut.CrashdumpKnownO_A	0	0	680599942	680415214	0	0
tb.dut.EdnKnownO_A	0	0	680599942	680415214	0	0
tb.dut.EscPKnownO_A	0	0	680599942	680415214	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	680599942	90	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	680599942	90	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	680599942	90	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	680599942	90	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	680599942	90	0	0
tb.dut.IrqAKnownO_A	0	0	680599942	680415214	0	0
tb.dut.IrqBKnownO_A	0	0	680599942	680415214	0	0
tb.dut.IrqCKnownO_A	0	0	680599942	680415214	0	0
tb.dut.IrqDKnownO_A	0	0	680599942	680415214	0	0
tb.dut.TlAReadyKnownO_A	0	0	680599942	680415214	0	0
tb.dut.TlDValidKnownO_A	0	0	680599942	680415214	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	709078344	3028740	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	709078344	16809	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	709078344	18168	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	709078344	18165	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	709078344	17175	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	709078344	18075	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	709078344	17821	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	709078344	17252	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	709078344	17127	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	709078344	18116	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	709078344	19187	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	709078344	18359	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	709078344	18541	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	709078344	17110	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	709078344	16836	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	709078344	17157	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	709078344	19349	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	709078344	18627	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	709078344	17210	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	709078344	18411	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	709078344	17008	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	709078344	16978	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	709078344	18143	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	709078344	17235	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	709078344	17124	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	709078344	18329	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	709078344	17174	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	709078344	18281	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	709078344	17278	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	709078344	17982	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	709078344	17770	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	709078344	17088	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	709078344	18357	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	709078344	17140	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	709078344	18194	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	709078344	16904	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	709078344	16749	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	709078344	17989	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	709078344	17278	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	709078344	17206	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	709078344	18201	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	709078344	18334	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	709078344	19427	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	709078344	17303	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	709078344	16984	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	709078344	17199	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	709078344	18187	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	709078344	19308	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	709078344	18507	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	709078344	18254	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	709078344	17543	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	709078344	17352	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	709078344	16662	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	709078344	18189	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	709078344	18092	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	709078344	17047	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	709078344	18243	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	709078344	18311	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	709078344	18032	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	709078344	19241	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	709078344	16867	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	709078344	18172	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	709078344	18513	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	709078344	16491	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	709078344	18281	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	709078344	18255	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	709078344	17155	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	709078344	17049	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	709078344	18006	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	709078344	17026	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	709078344	33891	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	709078344	16744	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	709078344	16978	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	709078344	17422	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	709078344	18231	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	709078344	17545	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	709078344	17338	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	709078344	16909	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	709078344	18342	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	680599942	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	680599942	90	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	680599942	90	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	680599942	1289	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	680599942	215146	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	680599942	371842830	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	680599942	263	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	680599942	796	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	680599942	49	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	680599942	403	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	680307615	274883759	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	680599942	909	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	680599942	890	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	680599942	875	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	680599942	858	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	680599942	2161	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	680599942	267682	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	680599942	2027	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	680599942	83	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	680599942	1454	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	680599942	1184	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	680306184	680236745	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	680599942	680415214	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	680599942	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	680599942	90	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	680599942	90	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	680599942	4521	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	680599942	214209	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	680599942	350416769	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	680599942	235	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	680599942	511	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	680599942	17	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	680599942	227	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	680307615	258691656	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	680599942	601	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	680599942	592	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	680599942	579	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	680599942	566	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	680599942	2056	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	680599942	206329	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	680599942	1956	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	680599942	81	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	680599942	1391	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	680599942	1121	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	680306184	680236745	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	680599942	680415214	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	680599942	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	680599942	90	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	680599942	90	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	680599942	6304	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	680599942	198133	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	680599942	375662992	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	680599942	265	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	680599942	489	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	680599942	26	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	680599942	203	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	680307615	262363493	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	680599942	573	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	680599942	567	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	680599942	561	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	680599942	554	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	680599942	1975	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	680599942	187587	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	680599942	1883	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	680599942	66	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	680599942	1411	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	680599942	1141	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	680306184	680236745	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	680599942	680415214	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	680599942	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	680599942	90	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	680599942	90	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	680599942	3194	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	680599942	198731	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	680599942	386940236	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	680599942	293	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	680599942	505	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	680599942	23	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	680599942	238	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	680307615	296266127	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	680599942	590	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	680599942	577	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	680599942	564	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	680599942	553	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	680599942	1947	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	680599942	218059	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	680599942	1854	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	680599942	68	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	680599942	1481	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	680599942	1211	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	680306184	680236745	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	623	623	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	680599942	680415214	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	709078344	141408500	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	709078344	708380440	0	0
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