Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
93.22	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	4	40	90.91

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	4	40	90.91	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	163	1			T4	4		T7	2		T26	3
index[0x1]	173	1			T4	1		T13	1		T6	2
index[0x2]	187	1			T4	2		T6	2		T45	3
index[0x3]	178	1			T4	1		T20	1		T6	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	245	1			T7	1		T20	1		T6	3
lens_less_than_1000[1]	147	1			T4	4		T13	1		T6	1
lens_less_than_1000[2]	83	1			T4	1		T73	2		T21	1
lens_less_than_1000[3]	70	1			T4	1		T45	1		T26	2
lens_less_than_1000[4]	47	1			T7	1		T26	1		T17	1
lens_less_than_1000[5]	51	1			T4	1		T68	1		T23	1
lens_less_than_1000[6]	25	1			T4	1		T6	1		T45	1
lens_less_than_1000[7]	19	1			T73	1		T65	1		T81	2
lens_less_than_1000[8]	7	1			T30	2		T243	1		T244	1
lens_less_than_1000[9]	3	1			T30	1		T245	1		T246	1
len_2	4	1			T60	2		T247	1		T248	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	4	40	90.91	4

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0]]	[lens_less_than_1000[9]]	0	1	1
[index[0x1] , index[0x2]]	[len_2]	--	--	2
[index[0x3]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	59	1			T7	1		T18	1		T78	1
index[0x0]	lens_less_than_1000[1]	29	1			T4	3		T23	1		T48	1
index[0x0]	lens_less_than_1000[2]	22	1			T4	1		T73	1		T74	1
index[0x0]	lens_less_than_1000[3]	13	1			T26	2		T80	1		T84	1
index[0x0]	lens_less_than_1000[4]	14	1			T7	1		T26	1		T17	1
index[0x0]	lens_less_than_1000[5]	11	1			T23	1		T112	1		T249	1
index[0x0]	lens_less_than_1000[6]	7	1			T21	1		T232	1		T250	1
index[0x0]	lens_less_than_1000[7]	5	1			T73	1		T61	1		T251	1
index[0x0]	lens_less_than_1000[8]	1	1			T30	1		-	-		-	-
index[0x0]	len_2	2	1			T60	1		T247	1		-	-
index[0x1]	lens_less_than_1000[0]	61	1			T6	1		T26	2		T18	1
index[0x1]	lens_less_than_1000[1]	44	1			T13	1		T6	1		T16	1
index[0x1]	lens_less_than_1000[2]	21	1			T21	1		T81	4		T252	1
index[0x1]	lens_less_than_1000[3]	9	1			T48	1		T232	1		T253	1
index[0x1]	lens_less_than_1000[4]	4	1			T75	1		T254	1		T255	1
index[0x1]	lens_less_than_1000[5]	23	1			T4	1		T48	1		T50	3
index[0x1]	lens_less_than_1000[6]	5	1			T225	1		T256	1		T257	1
index[0x1]	lens_less_than_1000[7]	1	1			T181	1		-	-		-	-
index[0x1]	lens_less_than_1000[8]	3	1			T244	1		T258	1		T259	1
index[0x1]	lens_less_than_1000[9]	2	1			T30	1		T245	1		-	-
index[0x2]	lens_less_than_1000[0]	70	1			T6	1		T45	1		T19	1
index[0x2]	lens_less_than_1000[1]	37	1			T4	1		T45	1		T21	1
index[0x2]	lens_less_than_1000[2]	16	1			T73	1		T260	1		T252	1
index[0x2]	lens_less_than_1000[3]	20	1			T45	1		T80	1		T232	1
index[0x2]	lens_less_than_1000[4]	21	1			T78	1		T74	1		T75	1
index[0x2]	lens_less_than_1000[5]	5	1			T99	1		T80	1		T261	1
index[0x2]	lens_less_than_1000[6]	6	1			T4	1		T6	1		T262	1
index[0x2]	lens_less_than_1000[7]	9	1			T65	1		T93	1		T55	1
index[0x2]	lens_less_than_1000[8]	2	1			T30	1		T243	1		-	-
index[0x2]	lens_less_than_1000[9]	1	1			T246	1		-	-		-	-
index[0x3]	lens_less_than_1000[0]	55	1			T20	1		T6	1		T46	1
index[0x3]	lens_less_than_1000[1]	37	1			T45	3		T70	1		T75	1
index[0x3]	lens_less_than_1000[2]	24	1			T72	1		T110	1		T51	1
index[0x3]	lens_less_than_1000[3]	28	1			T4	1		T35	1		T39	1
index[0x3]	lens_less_than_1000[4]	8	1			T263	1		T93	1		T91	1
index[0x3]	lens_less_than_1000[5]	12	1			T68	1		T80	1		T28	1
index[0x3]	lens_less_than_1000[6]	7	1			T45	1		T250	1		T264	1
index[0x3]	lens_less_than_1000[7]	4	1			T81	2		T265	1		T266	1
index[0x3]	lens_less_than_1000[8]	1	1			T267	1		-	-		-	-
index[0x3]	len_2	2	1			T60	1		T248	1		-	-