Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	83	1			T4	2		T14	1		T6	2
class_index[0x1]	81	1			T26	1		T77	1		T68	1
class_index[0x2]	66	1			T6	1		T26	7		T21	1
class_index[0x3]	68	1			T26	2		T70	1		T23	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	122	1			T14	1		T26	11		T68	1
intr_timeout_cnt[1]	58	1			T4	2		T77	1		T80	1
intr_timeout_cnt[2]	30	1			T6	1		T45	1		T26	1
intr_timeout_cnt[3]	18	1			T26	1		T268	2		T61	3
intr_timeout_cnt[4]	13	1			T6	1		T80	1		T53	1
intr_timeout_cnt[5]	15	1			T70	2		T81	2		T52	1
intr_timeout_cnt[6]	16	1			T6	1		T80	1		T83	1
intr_timeout_cnt[7]	12	1			T70	1		T81	1		T84	1
intr_timeout_cnt[8]	10	1			T22	2		T61	1		T269	1
intr_timeout_cnt[9]	4	1			T195	1		T247	1		T270	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	34	1			T14	1		T26	1		T30	2
class_index[0x0]	intr_timeout_cnt[1]	11	1			T4	2		T271	1		T272	1
class_index[0x0]	intr_timeout_cnt[2]	13	1			T6	1		T45	1		T26	1
class_index[0x0]	intr_timeout_cnt[3]	7	1			T26	1		T268	1		T61	1
class_index[0x0]	intr_timeout_cnt[4]	3	1			T6	1		T273	1		T274	1
class_index[0x0]	intr_timeout_cnt[5]	6	1			T113	1		T246	5		-	-
class_index[0x0]	intr_timeout_cnt[6]	5	1			T83	1		T107	1		T275	3
class_index[0x0]	intr_timeout_cnt[7]	3	1			T114	1		T107	1		T267	1
class_index[0x0]	intr_timeout_cnt[8]	1	1			T276	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	37	1			T26	1		T68	1		T75	1
class_index[0x1]	intr_timeout_cnt[1]	20	1			T77	1		T51	1		T92	1
class_index[0x1]	intr_timeout_cnt[2]	5	1			T277	1		T278	1		T279	1
class_index[0x1]	intr_timeout_cnt[3]	5	1			T61	1		T269	1		T280	1
class_index[0x1]	intr_timeout_cnt[4]	2	1			T281	1		T195	1		-	-
class_index[0x1]	intr_timeout_cnt[5]	1	1			T70	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[6]	1	1			T282	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	4	1			T81	1		T273	1		T283	1
class_index[0x1]	intr_timeout_cnt[8]	3	1			T273	1		T262	1		T284	1
class_index[0x1]	intr_timeout_cnt[9]	3	1			T195	1		T247	1		T270	1
class_index[0x2]	intr_timeout_cnt[0]	23	1			T26	7		T30	1		T285	1
class_index[0x2]	intr_timeout_cnt[1]	16	1			T109	1		T84	3		T113	5
class_index[0x2]	intr_timeout_cnt[2]	6	1			T21	1		T272	1		T269	1
class_index[0x2]	intr_timeout_cnt[3]	5	1			T268	1		T61	1		T247	1
class_index[0x2]	intr_timeout_cnt[4]	2	1			T53	1		T276	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	3	1			T70	1		T55	1		T284	1
class_index[0x2]	intr_timeout_cnt[6]	5	1			T6	1		T80	1		T262	1
class_index[0x2]	intr_timeout_cnt[7]	3	1			T84	1		T286	2		-	-
class_index[0x2]	intr_timeout_cnt[8]	2	1			T269	1		T287	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T288	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	28	1			T26	2		T23	1		T28	1
class_index[0x3]	intr_timeout_cnt[1]	11	1			T80	1		T81	1		T117	1
class_index[0x3]	intr_timeout_cnt[2]	6	1			T50	1		T272	1		T268	1
class_index[0x3]	intr_timeout_cnt[3]	1	1			T276	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[4]	6	1			T80	1		T96	1		T269	1
class_index[0x3]	intr_timeout_cnt[5]	5	1			T81	2		T52	1		T262	1
class_index[0x3]	intr_timeout_cnt[6]	5	1			T289	1		T290	1		T246	1
class_index[0x3]	intr_timeout_cnt[7]	2	1			T70	1		T267	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	4	1			T22	2		T61	1		T262	1