Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	371396	1			T1	39		T2	31		T3	35
all_values[1]	371396	1			T1	39		T2	31		T3	35
all_values[2]	371396	1			T1	39		T2	31		T3	35
all_values[3]	371396	1			T1	39		T2	31		T3	35

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

738644

1

T2

52

T3

75

T4

8715

auto[1]

746940

1

T1

156

T2

72

T3

65

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

881876

1

T1

136

T2

64

T3

73

auto[1]

603708

1

T1

20

T2

60

T3

67

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	106430	1			T2	10		T3	10		T4	1174
all_values[0]	auto[0]	auto[1]	77702	1			T2	9		T3	9		T4	988
all_values[0]	auto[1]	auto[0]	108791	1			T1	39		T2	6		T3	8
all_values[0]	auto[1]	auto[1]	78473	1			T2	6		T3	8		T4	1023
all_values[1]	auto[0]	auto[0]	109239	1			T2	4		T3	11		T4	1361
all_values[1]	auto[0]	auto[1]	75275	1			T2	4		T3	10		T4	755
all_values[1]	auto[1]	auto[0]	111191	1			T1	38		T2	12		T3	7
all_values[1]	auto[1]	auto[1]	75691	1			T1	1		T2	11		T3	7
all_values[2]	auto[0]	auto[0]	110697	1			T2	6		T3	7		T4	1453
all_values[2]	auto[0]	auto[1]	74561	1			T2	6		T3	7		T4	752
all_values[2]	auto[1]	auto[0]	111713	1			T1	39		T2	10		T3	11
all_values[2]	auto[1]	auto[1]	74425	1			T2	9		T3	10		T4	750
all_values[3]	auto[0]	auto[0]	111170	1			T2	7		T3	12		T4	1389
all_values[3]	auto[0]	auto[1]	73570	1			T2	6		T3	9		T4	843
all_values[3]	auto[1]	auto[0]	112645	1			T1	20		T2	9		T3	7
all_values[3]	auto[1]	auto[1]	74011	1			T1	19		T2	9		T3	7