Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	371396	1			T1	39		T2	31		T3	35
all_pins[1]	371396	1			T1	39		T2	31		T3	35
all_pins[2]	371396	1			T1	39		T2	31		T3	35
all_pins[3]	371396	1			T1	39		T2	31		T3	35

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1182984	1			T1	136		T2	89		T3	108
values[0x1]	302600	1			T1	20		T2	35		T3	32
transitions[0x0=>0x1]	200916	1			T1	20		T2	17		T3	18
transitions[0x1=>0x0]	201169	1			T1	20		T2	18		T3	18

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	292923	1			T1	39		T2	25		T3	27
all_pins[0]	values[0x1]	78473	1			T2	6		T3	8		T4	1023
all_pins[0]	transitions[0x0=>0x1]	77820	1			T2	5		T3	8		T4	1016
all_pins[0]	transitions[0x1=>0x0]	73611	1			T1	19		T2	9		T3	7
all_pins[1]	values[0x0]	295705	1			T1	38		T2	20		T3	28
all_pins[1]	values[0x1]	75691	1			T1	1		T2	11		T3	7
all_pins[1]	transitions[0x0=>0x1]	41585	1			T1	1		T2	6		T3	3
all_pins[1]	transitions[0x1=>0x0]	44367	1			T2	1		T3	4		T4	633
all_pins[2]	values[0x0]	296971	1			T1	39		T2	22		T3	25
all_pins[2]	values[0x1]	74425	1			T2	9		T3	10		T4	750
all_pins[2]	transitions[0x0=>0x1]	40595	1			T2	2		T3	4		T4	397
all_pins[2]	transitions[0x1=>0x0]	41861	1			T1	1		T2	4		T3	1
all_pins[3]	values[0x0]	297385	1			T1	20		T2	22		T3	28
all_pins[3]	values[0x1]	74011	1			T1	19		T2	9		T3	7
all_pins[3]	transitions[0x0=>0x1]	40916	1			T1	19		T2	4		T3	3
all_pins[3]	transitions[0x1=>0x0]	41330	1			T2	4		T3	6		T4	387