Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	94711	1			T4	685		T7	435		T26	415
accum_cnt_1000	238362	1			T4	2901		T13	124		T7	1364
accum_cnt_100	30557	1			T4	374		T13	71		T7	84
accum_cnt_50	82418	1			T2	38		T3	18		T4	1341
accum_cnt_10	187061	1			T1	14		T2	37		T3	39
accum_cnt_0	411784	1			T1	82		T2	25		T3	51

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	274317	1			T1	24		T2	25		T3	27
class_index[0x1]	274317	1			T1	24		T2	25		T3	27
class_index[0x2]	274317	1			T1	24		T2	25		T3	27
class_index[0x3]	274317	1			T1	24		T2	25		T3	27

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	25088	1			T4	369		T7	421		T26	415
class_index[0x0]	accum_cnt_1000	55074	1			T4	520		T7	492		T24	810
class_index[0x0]	accum_cnt_100	9924	1			T4	105		T7	33		T6	32
class_index[0x0]	accum_cnt_50	16919	1			T4	84		T7	19		T6	41
class_index[0x0]	accum_cnt_10	44599	1			T3	27		T4	313		T12	30
class_index[0x0]	accum_cnt_0	110216	1			T1	24		T2	25		T4	1791
class_index[0x1]	accum_cnt_2000	26483	1			T4	291		T7	14		T27	674
class_index[0x1]	accum_cnt_1000	63997	1			T4	524		T13	15		T7	872
class_index[0x1]	accum_cnt_100	6957	1			T4	64		T13	37		T7	51
class_index[0x1]	accum_cnt_50	22381	1			T2	19		T3	18		T4	1102
class_index[0x1]	accum_cnt_10	41280	1			T2	6		T3	9		T4	59
class_index[0x1]	accum_cnt_0	100348	1			T1	24		T4	1014		T12	2
class_index[0x2]	accum_cnt_2000	21204	1			T27	485		T37	420		T25	516
class_index[0x2]	accum_cnt_1000	60774	1			T4	1115		T13	55		T43	12
class_index[0x2]	accum_cnt_100	6969	1			T4	132		T13	16		T6	39
class_index[0x2]	accum_cnt_50	22169	1			T2	19		T4	107		T13	14
class_index[0x2]	accum_cnt_10	50940	1			T2	6		T3	2		T4	1088
class_index[0x2]	accum_cnt_0	97863	1			T1	24		T3	25		T4	750
class_index[0x3]	accum_cnt_2000	21936	1			T4	25		T27	362		T29	183
class_index[0x3]	accum_cnt_1000	58517	1			T4	742		T13	54		T26	796
class_index[0x3]	accum_cnt_100	6707	1			T4	73		T13	18		T26	58
class_index[0x3]	accum_cnt_50	20949	1			T4	48		T12	2		T13	13
class_index[0x3]	accum_cnt_10	50242	1			T1	14		T2	25		T3	1
class_index[0x3]	accum_cnt_0	103357	1			T1	10		T3	26		T4	2284