Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	18117	1			T6	1		T29	30		T68	14
alert[0x1]	7823	1			T16	1		T19	1		T29	275
alert[0x2]	11418	1			T1	1		T29	203		T65	1423
alert[0x3]	14595	1			T6	76		T296	1		T79	121
alert[0x4]	4714	1			T26	5		T69	1		T79	37
alert[0x5]	5600	1			T4	4		T8	1		T6	971
alert[0x6]	7114	1			T6	1		T26	6		T65	36
alert[0x7]	11203	1			T16	1		T29	33		T297	1
alert[0x8]	4488	1			T26	1		T68	42		T30	3
alert[0x9]	12488	1			T1	1		T6	2		T19	1
alert[0xa]	2872	1			T8	1		T16	1		T19	1
alert[0xb]	3948	1			T23	3		T48	14		T22	10
alert[0xc]	4336	1			T26	27		T19	1		T297	1
alert[0xd]	5633	1			T26	2		T65	19		T69	1
alert[0xe]	9080	1			T26	149		T25	1		T66	1
alert[0xf]	8566	1			T4	2		T8	1		T6	2
alert[0x10]	4456	1			T16	1		T19	1		T29	15
alert[0x11]	3368	1			T4	4		T6	20		T69	1
alert[0x12]	4120	1			T4	22		T6	2		T65	52
alert[0x13]	3710	1			T8	1		T16	1		T29	40
alert[0x14]	4247	1			T19	1		T79	21		T238	1
alert[0x15]	3761	1			T16	1		T19	1		T29	15
alert[0x16]	10307	1			T25	22		T68	283		T297	1
alert[0x17]	8281	1			T8	1		T19	1		T29	7
alert[0x18]	8965	1			T6	1		T29	51		T65	112
alert[0x19]	3426	1			T43	8		T65	31		T66	1
alert[0x1a]	8162	1			T1	2		T26	54		T29	147
alert[0x1b]	3597	1			T1	1		T26	3		T29	248
alert[0x1c]	7340	1			T4	10		T8	1		T30	1
alert[0x1d]	9531	1			T1	1		T26	4		T19	1
alert[0x1e]	7358	1			T1	1		T6	4		T29	175
alert[0x1f]	12508	1			T4	4		T19	1		T29	685
alert[0x20]	10860	1			T29	7		T69	1		T48	204
alert[0x21]	6545	1			T16	1		T65	102		T68	267
alert[0x22]	9729	1			T4	20		T26	7		T85	1
alert[0x23]	5400	1			T23	48		T32	1		T80	33
alert[0x24]	10836	1			T6	85		T26	2		T19	1
alert[0x25]	2316	1			T6	6		T26	1		T16	1
alert[0x26]	6549	1			T16	1		T69	1		T79	162
alert[0x27]	6395	1			T6	17		T26	1		T65	360
alert[0x28]	13919	1			T6	2		T65	145		T238	2
alert[0x29]	5491	1			T8	1		T19	1		T29	25
alert[0x2a]	6271	1			T4	3		T25	1		T21	1
alert[0x2b]	12241	1			T1	2		T29	135		T48	108
alert[0x2c]	7002	1			T1	1		T43	11		T26	389
alert[0x2d]	6815	1			T16	1		T29	155		T65	308
alert[0x2e]	8741	1			T4	5		T21	6		T65	820
alert[0x2f]	5840	1			T6	8		T26	9		T65	69
alert[0x30]	7729	1			T6	56		T29	1828		T66	1
alert[0x31]	8693	1			T6	1		T26	267		T19	1
alert[0x32]	7085	1			T26	4		T29	22		T30	4
alert[0x33]	8554	1			T16	1		T19	1		T29	8
alert[0x34]	3333	1			T1	1		T65	99		T79	17
alert[0x35]	2716	1			T6	6		T29	46		T66	1
alert[0x36]	10535	1			T25	1		T21	18		T65	52
alert[0x37]	7193	1			T68	358		T30	48		T90	6
alert[0x38]	8593	1			T6	4		T16	1		T19	1
alert[0x39]	11578	1			T6	7		T26	18		T65	1391
alert[0x3a]	9034	1			T1	1		T6	377		T26	1
alert[0x3b]	9176	1			T26	10		T29	41		T65	189
alert[0x3c]	3074	1			T6	256		T29	8		T25	1
alert[0x3d]	12943	1			T1	1		T6	11		T26	263
alert[0x3e]	5223	1			T1	1		T6	13		T29	154
alert[0x3f]	14483	1			T29	604		T21	3		T65	10
alert[0x40]	6554	1			T26	14		T16	1		T19	1

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	182002	1			T4	23		T8	2		T43	11
class_i[0x1]	91528	1			T8	1		T43	8		T16	2
class_i[0x2]	112688	1			T4	13		T8	1		T6	81
class_i[0x3]	110360	1			T1	14		T4	38		T8	3

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

495817

1

T4

74

T6

1929

T43

19

alert_ping_fail

761

1

T1

14

T8

7

T16

13

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	18106	1			T6	1		T29	30		T68	14
alert_integrity_fail	alert[0x1]	7813	1			T29	275		T21	3		T65	1691
alert_integrity_fail	alert[0x2]	11409	1			T29	203		T65	1423		T68	3
alert_integrity_fail	alert[0x3]	14585	1			T6	76		T296	1		T79	121
alert_integrity_fail	alert[0x4]	4707	1			T26	5		T79	37		T28	3
alert_integrity_fail	alert[0x5]	5570	1			T4	4		T6	971		T26	712
alert_integrity_fail	alert[0x6]	7105	1			T6	1		T26	6		T65	36
alert_integrity_fail	alert[0x7]	11183	1			T29	33		T30	6		T23	5
alert_integrity_fail	alert[0x8]	4481	1			T26	1		T68	42		T30	3
alert_integrity_fail	alert[0x9]	12475	1			T6	2		T25	3		T65	721
alert_integrity_fail	alert[0xa]	2857	1			T65	34		T23	4		T32	1
alert_integrity_fail	alert[0xb]	3938	1			T23	3		T48	14		T22	10
alert_integrity_fail	alert[0xc]	4325	1			T26	27		T79	20		T48	5
alert_integrity_fail	alert[0xd]	5620	1			T26	2		T65	19		T23	217
alert_integrity_fail	alert[0xe]	9067	1			T26	149		T25	1		T68	26
alert_integrity_fail	alert[0xf]	8553	1			T4	2		T6	2		T29	56
alert_integrity_fail	alert[0x10]	4448	1			T29	15		T30	2		T23	11
alert_integrity_fail	alert[0x11]	3357	1			T4	4		T6	20		T30	11
alert_integrity_fail	alert[0x12]	4107	1			T4	22		T6	2		T65	52
alert_integrity_fail	alert[0x13]	3698	1			T29	40		T65	23		T79	31
alert_integrity_fail	alert[0x14]	4238	1			T79	21		T50	1		T229	68
alert_integrity_fail	alert[0x15]	3745	1			T29	15		T68	179		T79	172
alert_integrity_fail	alert[0x16]	10297	1			T25	22		T68	283		T80	4
alert_integrity_fail	alert[0x17]	8258	1			T29	7		T65	72		T32	3
alert_integrity_fail	alert[0x18]	8955	1			T6	1		T29	51		T65	112
alert_integrity_fail	alert[0x19]	3417	1			T43	8		T65	31		T68	17
alert_integrity_fail	alert[0x1a]	8147	1			T26	54		T29	147		T68	5
alert_integrity_fail	alert[0x1b]	3583	1			T26	3		T29	248		T48	58
alert_integrity_fail	alert[0x1c]	7328	1			T4	10		T30	1		T23	4
alert_integrity_fail	alert[0x1d]	9520	1			T26	4		T22	1		T80	1
alert_integrity_fail	alert[0x1e]	7351	1			T6	4		T29	175		T80	5
alert_integrity_fail	alert[0x1f]	12487	1			T4	4		T29	685		T298	10
alert_integrity_fail	alert[0x20]	10848	1			T29	7		T48	204		T90	30
alert_integrity_fail	alert[0x21]	6536	1			T65	102		T68	267		T79	32
alert_integrity_fail	alert[0x22]	9712	1			T4	20		T26	7		T21	14
alert_integrity_fail	alert[0x23]	5394	1			T23	48		T32	1		T80	33
alert_integrity_fail	alert[0x24]	10827	1			T6	85		T26	2		T29	43
alert_integrity_fail	alert[0x25]	2303	1			T6	6		T26	1		T30	52
alert_integrity_fail	alert[0x26]	6535	1			T79	162		T23	33		T48	74
alert_integrity_fail	alert[0x27]	6388	1			T6	17		T26	1		T65	360
alert_integrity_fail	alert[0x28]	13909	1			T6	2		T65	145		T22	291
alert_integrity_fail	alert[0x29]	5483	1			T29	25		T79	153		T48	102
alert_integrity_fail	alert[0x2a]	6256	1			T4	3		T25	1		T21	1
alert_integrity_fail	alert[0x2b]	12225	1			T29	135		T48	108		T28	38
alert_integrity_fail	alert[0x2c]	6988	1			T43	11		T26	389		T21	2
alert_integrity_fail	alert[0x2d]	6803	1			T29	155		T65	308		T79	16
alert_integrity_fail	alert[0x2e]	8735	1			T4	5		T21	6		T65	820
alert_integrity_fail	alert[0x2f]	5828	1			T6	8		T26	9		T65	69
alert_integrity_fail	alert[0x30]	7714	1			T6	56		T29	1828		T30	3
alert_integrity_fail	alert[0x31]	8677	1			T6	1		T26	267		T68	176
alert_integrity_fail	alert[0x32]	7080	1			T26	4		T29	22		T30	4
alert_integrity_fail	alert[0x33]	8543	1			T29	8		T21	1		T65	2478
alert_integrity_fail	alert[0x34]	3314	1			T65	99		T79	17		T298	5
alert_integrity_fail	alert[0x35]	2708	1			T6	6		T29	46		T23	47
alert_integrity_fail	alert[0x36]	10521	1			T25	1		T21	18		T65	52
alert_integrity_fail	alert[0x37]	7187	1			T68	358		T30	48		T90	6
alert_integrity_fail	alert[0x38]	8580	1			T6	4		T65	737		T79	120
alert_integrity_fail	alert[0x39]	11569	1			T6	7		T26	18		T65	1391
alert_integrity_fail	alert[0x3a]	9029	1			T6	377		T26	1		T29	218
alert_integrity_fail	alert[0x3b]	9165	1			T26	10		T29	41		T65	189
alert_integrity_fail	alert[0x3c]	3061	1			T6	256		T29	8		T25	1
alert_integrity_fail	alert[0x3d]	12937	1			T6	11		T26	263		T29	1117
alert_integrity_fail	alert[0x3e]	5209	1			T6	13		T29	154		T65	1102
alert_integrity_fail	alert[0x3f]	14477	1			T29	604		T21	3		T65	10
alert_integrity_fail	alert[0x40]	6546	1			T26	14		T65	30		T79	20
alert_ping_fail	alert[0x0]	11	1			T297	3		T182	1		T299	1
alert_ping_fail	alert[0x1]	10	1			T16	1		T19	1		T300	2
alert_ping_fail	alert[0x2]	9	1			T1	1		T301	1		T302	1
alert_ping_fail	alert[0x3]	10	1			T303	1		T302	2		T304	1
alert_ping_fail	alert[0x4]	7	1			T69	1		T305	1		T306	1
alert_ping_fail	alert[0x5]	30	1			T8	1		T69	1		T297	1
alert_ping_fail	alert[0x6]	9	1			T228	1		T306	1		T307	1
alert_ping_fail	alert[0x7]	20	1			T16	1		T297	1		T74	2
alert_ping_fail	alert[0x8]	7	1			T294	1		T305	1		T306	1
alert_ping_fail	alert[0x9]	13	1			T1	1		T19	1		T66	1
alert_ping_fail	alert[0xa]	15	1			T8	1		T16	1		T19	1
alert_ping_fail	alert[0xb]	10	1			T223	1		T306	2		T303	1
alert_ping_fail	alert[0xc]	11	1			T19	1		T297	1		T301	1
alert_ping_fail	alert[0xd]	13	1			T69	1		T223	1		T308	1
alert_ping_fail	alert[0xe]	13	1			T66	1		T297	2		T257	1
alert_ping_fail	alert[0xf]	13	1			T8	1		T66	1		T238	1
alert_ping_fail	alert[0x10]	8	1			T16	1		T19	1		T301	1
alert_ping_fail	alert[0x11]	11	1			T69	1		T223	1		T301	1
alert_ping_fail	alert[0x12]	13	1			T69	1		T223	2		T219	1
alert_ping_fail	alert[0x13]	12	1			T8	1		T16	1		T66	1
alert_ping_fail	alert[0x14]	9	1			T19	1		T238	1		T304	1
alert_ping_fail	alert[0x15]	16	1			T16	1		T19	1		T66	1
alert_ping_fail	alert[0x16]	10	1			T297	1		T308	1		T257	1
alert_ping_fail	alert[0x17]	23	1			T8	1		T19	1		T238	1
alert_ping_fail	alert[0x18]	10	1			T66	1		T306	1		T303	1
alert_ping_fail	alert[0x19]	9	1			T66	1		T305	2		T309	2
alert_ping_fail	alert[0x1a]	15	1			T1	2		T297	1		T305	1
alert_ping_fail	alert[0x1b]	14	1			T1	1		T69	1		T219	1
alert_ping_fail	alert[0x1c]	12	1			T8	1		T301	1		T300	1
alert_ping_fail	alert[0x1d]	11	1			T1	1		T19	1		T300	2
alert_ping_fail	alert[0x1e]	7	1			T1	1		T300	1		T310	1
alert_ping_fail	alert[0x1f]	21	1			T19	1		T297	1		T311	1
alert_ping_fail	alert[0x20]	12	1			T69	1		T301	1		T300	2
alert_ping_fail	alert[0x21]	9	1			T16	1		T299	1		T312	2
alert_ping_fail	alert[0x22]	17	1			T85	1		T301	2		T305	1
alert_ping_fail	alert[0x23]	6	1			T219	1		T313	1		T310	2
alert_ping_fail	alert[0x24]	9	1			T19	1		T307	1		T299	1
alert_ping_fail	alert[0x25]	13	1			T16	1		T19	1		T69	1
alert_ping_fail	alert[0x26]	14	1			T16	1		T69	1		T306	1
alert_ping_fail	alert[0x27]	7	1			T69	1		T238	1		T223	2
alert_ping_fail	alert[0x28]	10	1			T238	2		T311	1		T182	1
alert_ping_fail	alert[0x29]	8	1			T8	1		T19	1		T69	1
alert_ping_fail	alert[0x2a]	15	1			T66	1		T297	1		T182	1
alert_ping_fail	alert[0x2b]	16	1			T1	2		T300	1		T309	1
alert_ping_fail	alert[0x2c]	14	1			T1	1		T238	1		T182	1
alert_ping_fail	alert[0x2d]	12	1			T16	1		T69	2		T308	1
alert_ping_fail	alert[0x2e]	6	1			T69	1		T310	1		T314	1
alert_ping_fail	alert[0x2f]	12	1			T297	1		T300	1		T310	2
alert_ping_fail	alert[0x30]	15	1			T66	1		T74	2		T223	1
alert_ping_fail	alert[0x31]	16	1			T19	1		T69	3		T257	1
alert_ping_fail	alert[0x32]	5	1			T307	1		T315	1		T316	1
alert_ping_fail	alert[0x33]	11	1			T16	1		T19	1		T297	1
alert_ping_fail	alert[0x34]	19	1			T1	1		T308	1		T257	1
alert_ping_fail	alert[0x35]	8	1			T66	1		T69	1		T297	1
alert_ping_fail	alert[0x36]	14	1			T297	1		T305	1		T313	1
alert_ping_fail	alert[0x37]	6	1			T219	1		T313	1		T310	1
alert_ping_fail	alert[0x38]	13	1			T16	1		T19	1		T69	1
alert_ping_fail	alert[0x39]	9	1			T223	1		T306	1		T303	1
alert_ping_fail	alert[0x3a]	5	1			T1	1		T69	1		T238	1
alert_ping_fail	alert[0x3b]	11	1			T297	1		T300	1		T257	1
alert_ping_fail	alert[0x3c]	13	1			T238	1		T300	1		T310	1
alert_ping_fail	alert[0x3d]	6	1			T1	1		T238	1		T305	2
alert_ping_fail	alert[0x3e]	14	1			T1	1		T297	1		T308	1
alert_ping_fail	alert[0x3f]	6	1			T309	1		T307	1		T299	1
alert_ping_fail	alert[0x40]	8	1			T16	1		T19	1		T306	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	181863	1			T4	23		T43	11		T26	1695
alert_integrity_fail	class_i[0x1]	91363	1			T43	8		T29	8		T21	8
alert_integrity_fail	class_i[0x2]	112523	1			T4	13		T6	81		T26	254
alert_integrity_fail	class_i[0x3]	110068	1			T4	38		T6	1848		T29	6346
alert_ping_fail	class_i[0x0]	139	1			T8	2		T16	7		T66	1
alert_ping_fail	class_i[0x1]	165	1			T8	1		T16	2		T19	17
alert_ping_fail	class_i[0x2]	165	1			T8	1		T16	2		T66	7
alert_ping_fail	class_i[0x3]	292	1			T1	14		T8	3		T16	2