Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.23 99.99 98.65 97.09 100.00 100.00 99.38 99.48


Total test records in report: 828
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html
T141 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1462100683 Jul 27 05:17:00 PM PDT 24 Jul 27 05:20:16 PM PDT 24 1775828131 ps
T776 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1507350102 Jul 27 05:16:50 PM PDT 24 Jul 27 05:16:59 PM PDT 24 59307281 ps
T777 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.250885414 Jul 27 05:17:00 PM PDT 24 Jul 27 05:20:51 PM PDT 24 3416295076 ps
T778 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.6250158 Jul 27 05:17:11 PM PDT 24 Jul 27 05:17:16 PM PDT 24 64520712 ps
T166 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.682582984 Jul 27 05:17:15 PM PDT 24 Jul 27 05:17:20 PM PDT 24 67003544 ps
T134 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.4237631654 Jul 27 05:17:23 PM PDT 24 Jul 27 05:34:17 PM PDT 24 50981136723 ps
T779 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.413769365 Jul 27 05:17:21 PM PDT 24 Jul 27 05:17:26 PM PDT 24 33917534 ps
T173 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1054101906 Jul 27 05:17:22 PM PDT 24 Jul 27 05:17:27 PM PDT 24 110745577 ps
T780 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3693702258 Jul 27 05:16:50 PM PDT 24 Jul 27 05:16:56 PM PDT 24 121329007 ps
T781 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.4013694320 Jul 27 05:16:59 PM PDT 24 Jul 27 05:17:17 PM PDT 24 983016932 ps
T782 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1285628113 Jul 27 05:16:50 PM PDT 24 Jul 27 05:21:13 PM PDT 24 6730868948 ps
T783 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2947102841 Jul 27 05:17:10 PM PDT 24 Jul 27 05:17:11 PM PDT 24 7198704 ps
T784 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.256799748 Jul 27 05:17:11 PM PDT 24 Jul 27 05:17:24 PM PDT 24 142407916 ps
T148 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2437711682 Jul 27 05:17:14 PM PDT 24 Jul 27 05:36:41 PM PDT 24 15487263806 ps
T146 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3840191499 Jul 27 05:16:59 PM PDT 24 Jul 27 05:22:10 PM PDT 24 9682348568 ps
T785 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.103998983 Jul 27 05:16:57 PM PDT 24 Jul 27 05:16:59 PM PDT 24 20457485 ps
T149 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2093232121 Jul 27 05:17:12 PM PDT 24 Jul 27 05:20:30 PM PDT 24 2616016949 ps
T139 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2320939509 Jul 27 05:16:51 PM PDT 24 Jul 27 05:19:02 PM PDT 24 7370636131 ps
T786 /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2606723537 Jul 27 05:17:12 PM PDT 24 Jul 27 05:17:22 PM PDT 24 473642153 ps
T787 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1810204406 Jul 27 05:16:58 PM PDT 24 Jul 27 05:17:01 PM PDT 24 35817675 ps
T788 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1647801694 Jul 27 05:17:23 PM PDT 24 Jul 27 05:17:26 PM PDT 24 60989443 ps
T789 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2259460521 Jul 27 05:17:12 PM PDT 24 Jul 27 05:17:22 PM PDT 24 128003295 ps
T790 /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3561025571 Jul 27 05:17:14 PM PDT 24 Jul 27 05:17:16 PM PDT 24 16522219 ps
T791 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3864686723 Jul 27 05:17:24 PM PDT 24 Jul 27 05:17:33 PM PDT 24 206027436 ps
T142 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2375090508 Jul 27 05:17:00 PM PDT 24 Jul 27 05:35:39 PM PDT 24 16616078175 ps
T151 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2781946079 Jul 27 05:17:10 PM PDT 24 Jul 27 05:22:12 PM PDT 24 4049520112 ps
T177 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2858562562 Jul 27 05:17:11 PM PDT 24 Jul 27 05:17:50 PM PDT 24 4168626302 ps
T792 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.444640645 Jul 27 05:17:23 PM PDT 24 Jul 27 05:17:25 PM PDT 24 21633540 ps
T153 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3068009411 Jul 27 05:17:27 PM PDT 24 Jul 27 05:35:06 PM PDT 24 98681758155 ps
T793 /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3153329590 Jul 27 05:17:00 PM PDT 24 Jul 27 05:17:11 PM PDT 24 274223547 ps
T794 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1600993309 Jul 27 05:16:58 PM PDT 24 Jul 27 05:16:59 PM PDT 24 8831982 ps
T795 /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.197963366 Jul 27 05:17:23 PM PDT 24 Jul 27 05:17:25 PM PDT 24 18414409 ps
T796 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3214521978 Jul 27 05:17:13 PM PDT 24 Jul 27 05:17:26 PM PDT 24 100743417 ps
T797 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.254050882 Jul 27 05:17:21 PM PDT 24 Jul 27 05:17:23 PM PDT 24 9521827 ps
T169 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.249286093 Jul 27 05:17:22 PM PDT 24 Jul 27 05:17:26 PM PDT 24 39792518 ps
T798 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1702827190 Jul 27 05:17:22 PM PDT 24 Jul 27 05:17:24 PM PDT 24 12004991 ps
T799 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1089681158 Jul 27 05:16:50 PM PDT 24 Jul 27 05:24:35 PM PDT 24 6584758074 ps
T800 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3378124345 Jul 27 05:16:52 PM PDT 24 Jul 27 05:20:01 PM PDT 24 2883657080 ps
T801 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2282653121 Jul 27 05:17:21 PM PDT 24 Jul 27 05:17:33 PM PDT 24 267737386 ps
T143 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.606045612 Jul 27 05:16:59 PM PDT 24 Jul 27 05:19:10 PM PDT 24 24706993993 ps
T802 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2355611666 Jul 27 05:17:22 PM PDT 24 Jul 27 05:17:39 PM PDT 24 381646590 ps
T803 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1502054691 Jul 27 05:17:23 PM PDT 24 Jul 27 05:17:25 PM PDT 24 27382079 ps
T804 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.364784821 Jul 27 05:17:10 PM PDT 24 Jul 27 05:17:16 PM PDT 24 126875925 ps
T164 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.457151133 Jul 27 05:17:22 PM PDT 24 Jul 27 05:17:25 PM PDT 24 170312324 ps
T805 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3251744116 Jul 27 05:17:04 PM PDT 24 Jul 27 05:18:15 PM PDT 24 1916480702 ps
T135 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3712863707 Jul 27 05:16:58 PM PDT 24 Jul 27 05:27:37 PM PDT 24 4775690301 ps
T806 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.777306009 Jul 27 05:17:22 PM PDT 24 Jul 27 05:17:24 PM PDT 24 8503159 ps
T807 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1199506251 Jul 27 05:17:14 PM PDT 24 Jul 27 05:17:31 PM PDT 24 271493374 ps
T808 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2599350174 Jul 27 05:16:58 PM PDT 24 Jul 27 05:17:03 PM PDT 24 124880170 ps
T809 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1017110316 Jul 27 05:17:22 PM PDT 24 Jul 27 05:18:04 PM PDT 24 4869000799 ps
T810 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2097510797 Jul 27 05:16:57 PM PDT 24 Jul 27 05:16:59 PM PDT 24 15485728 ps
T147 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.196166578 Jul 27 05:16:51 PM PDT 24 Jul 27 05:22:56 PM PDT 24 20750439068 ps
T811 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.830515679 Jul 27 05:16:48 PM PDT 24 Jul 27 05:16:50 PM PDT 24 8438270 ps
T155 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2193134213 Jul 27 05:17:12 PM PDT 24 Jul 27 05:19:59 PM PDT 24 8553046602 ps
T152 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.923754674 Jul 27 05:16:57 PM PDT 24 Jul 27 05:27:18 PM PDT 24 4250395536 ps
T812 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1338622914 Jul 27 05:17:22 PM PDT 24 Jul 27 05:17:47 PM PDT 24 6699162887 ps
T165 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.77565770 Jul 27 05:17:01 PM PDT 24 Jul 27 05:17:04 PM PDT 24 126002251 ps
T813 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1105575367 Jul 27 05:16:58 PM PDT 24 Jul 27 05:17:18 PM PDT 24 1082018577 ps
T814 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3168068324 Jul 27 05:17:10 PM PDT 24 Jul 27 05:17:26 PM PDT 24 385642169 ps
T136 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.4184422901 Jul 27 05:17:04 PM PDT 24 Jul 27 05:20:14 PM PDT 24 1683940721 ps
T815 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1298749490 Jul 27 05:17:24 PM PDT 24 Jul 27 05:17:26 PM PDT 24 10256747 ps
T816 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3013043100 Jul 27 05:17:14 PM PDT 24 Jul 27 05:17:32 PM PDT 24 248822161 ps
T817 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1434547564 Jul 27 05:17:02 PM PDT 24 Jul 27 05:17:14 PM PDT 24 434804592 ps
T818 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2794384679 Jul 27 05:16:56 PM PDT 24 Jul 27 05:17:01 PM PDT 24 559410308 ps
T819 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2212380865 Jul 27 05:17:11 PM PDT 24 Jul 27 05:17:13 PM PDT 24 58240229 ps
T820 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3084568793 Jul 27 05:17:10 PM PDT 24 Jul 27 05:17:11 PM PDT 24 26531727 ps
T168 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1798940856 Jul 27 05:16:57 PM PDT 24 Jul 27 05:17:21 PM PDT 24 187648569 ps
T150 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.842228956 Jul 27 05:17:23 PM PDT 24 Jul 27 05:21:47 PM PDT 24 3846382790 ps
T821 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.4192071803 Jul 27 05:16:58 PM PDT 24 Jul 27 05:25:22 PM PDT 24 38887168776 ps
T822 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.894868299 Jul 27 05:17:14 PM PDT 24 Jul 27 05:17:38 PM PDT 24 182263082 ps
T823 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.633096274 Jul 27 05:16:59 PM PDT 24 Jul 27 05:24:04 PM PDT 24 22811153749 ps
T824 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1763052515 Jul 27 05:17:23 PM PDT 24 Jul 27 05:17:24 PM PDT 24 8421649 ps
T825 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.893874729 Jul 27 05:16:51 PM PDT 24 Jul 27 05:17:01 PM PDT 24 101374654 ps
T154 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.397620836 Jul 27 05:17:20 PM PDT 24 Jul 27 05:19:38 PM PDT 24 8426020413 ps
T156 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1293179576 Jul 27 05:17:04 PM PDT 24 Jul 27 05:39:19 PM PDT 24 32176496073 ps
T826 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1925134173 Jul 27 05:17:12 PM PDT 24 Jul 27 05:17:18 PM PDT 24 34564277 ps
T827 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3113622229 Jul 27 05:16:59 PM PDT 24 Jul 27 05:17:03 PM PDT 24 81385747 ps
T828 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.939322924 Jul 27 05:17:23 PM PDT 24 Jul 27 05:17:25 PM PDT 24 16025458 ps

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.983100959
Short name T4
Test name
Test status
Simulation time 334924544889 ps
CPU time 5519.56 seconds
Started Jul 27 05:19:56 PM PDT 24
Finished Jul 27 06:51:56 PM PDT 24
Peak memory 354628 kb
Host smart-77b71460-7a66-48a4-983d-e02a22009955
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983100959 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.983100959
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.632685809
Short name T6
Test name
Test status
Simulation time 49577323275 ps
CPU time 819.23 seconds
Started Jul 27 05:20:08 PM PDT 24
Finished Jul 27 05:33:47 PM PDT 24
Peak memory 273580 kb
Host smart-0b919f62-8335-43f9-baad-59f15719e88f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632685809 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.632685809
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.2937763399
Short name T11
Test name
Test status
Simulation time 1801856955 ps
CPU time 73.83 seconds
Started Jul 27 05:18:17 PM PDT 24
Finished Jul 27 05:19:31 PM PDT 24
Peak memory 270448 kb
Host smart-af25579a-c927-4ef6-a594-436f531e8693
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2937763399 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.2937763399
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.4105500737
Short name T5
Test name
Test status
Simulation time 803004077 ps
CPU time 20.51 seconds
Started Jul 27 05:18:31 PM PDT 24
Finished Jul 27 05:18:51 PM PDT 24
Peak memory 248696 kb
Host smart-afb66f04-5b85-47f3-9619-9ca896f8d5b1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4105500737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.4105500737
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.481494603
Short name T157
Test name
Test status
Simulation time 1824320775 ps
CPU time 74.66 seconds
Started Jul 27 05:16:59 PM PDT 24
Finished Jul 27 05:18:14 PM PDT 24
Peak memory 240292 kb
Host smart-da204187-a6c1-4bf8-815c-afb387282986
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=481494603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.481494603
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3992030153
Short name T93
Test name
Test status
Simulation time 185451322390 ps
CPU time 2865.17 seconds
Started Jul 27 05:21:14 PM PDT 24
Finished Jul 27 06:09:00 PM PDT 24
Peak memory 297932 kb
Host smart-66a2241d-0f2a-4aed-955b-6e807deb1eed
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992030153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3992030153
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.98176836
Short name T26
Test name
Test status
Simulation time 46396086823 ps
CPU time 4345.29 seconds
Started Jul 27 05:18:39 PM PDT 24
Finished Jul 27 06:31:05 PM PDT 24
Peak memory 339044 kb
Host smart-5d0dbb64-5cee-4de5-bcea-2eadc4951a60
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98176836 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.98176836
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.300121921
Short name T81
Test name
Test status
Simulation time 6795293114 ps
CPU time 206.72 seconds
Started Jul 27 05:20:59 PM PDT 24
Finished Jul 27 05:24:26 PM PDT 24
Peak memory 256980 kb
Host smart-34c60da1-7b69-4b77-b144-152f82032826
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300121921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.300121921
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3260886191
Short name T123
Test name
Test status
Simulation time 52357022686 ps
CPU time 795.08 seconds
Started Jul 27 05:17:23 PM PDT 24
Finished Jul 27 05:30:38 PM PDT 24
Peak memory 271348 kb
Host smart-c90e6aa9-4e4f-4d32-9843-f34604c4bc49
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260886191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3260886191
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.2788249278
Short name T74
Test name
Test status
Simulation time 63967171131 ps
CPU time 1955.46 seconds
Started Jul 27 05:18:30 PM PDT 24
Finished Jul 27 05:51:06 PM PDT 24
Peak memory 285312 kb
Host smart-766397f8-3705-4358-a834-d9c38b95a998
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788249278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.2788249278
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.1546843874
Short name T58
Test name
Test status
Simulation time 340296628280 ps
CPU time 8615.84 seconds
Started Jul 27 05:21:13 PM PDT 24
Finished Jul 27 07:44:50 PM PDT 24
Peak memory 353432 kb
Host smart-839df323-3c7a-49bc-b48a-1b6df26b55cc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546843874 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.1546843874
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.4265318888
Short name T62
Test name
Test status
Simulation time 15667614494 ps
CPU time 1472.18 seconds
Started Jul 27 05:21:19 PM PDT 24
Finished Jul 27 05:45:51 PM PDT 24
Peak memory 289100 kb
Host smart-69a289b5-4e21-4719-a55d-dad66b8e63c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265318888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.4265318888
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.1059077061
Short name T119
Test name
Test status
Simulation time 9789349794 ps
CPU time 325.66 seconds
Started Jul 27 05:16:59 PM PDT 24
Finished Jul 27 05:22:25 PM PDT 24
Peak memory 265400 kb
Host smart-5128c435-52a3-4421-b424-79e295c64f5a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1059077061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.1059077061
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.196166578
Short name T147
Test name
Test status
Simulation time 20750439068 ps
CPU time 365.13 seconds
Started Jul 27 05:16:51 PM PDT 24
Finished Jul 27 05:22:56 PM PDT 24
Peak memory 265404 kb
Host smart-832f4819-d473-4bb8-9bae-f759dacc4a98
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=196166578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_error
s.196166578
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.1567793011
Short name T19
Test name
Test status
Simulation time 20043652560 ps
CPU time 472.28 seconds
Started Jul 27 05:20:34 PM PDT 24
Finished Jul 27 05:28:27 PM PDT 24
Peak memory 255516 kb
Host smart-9b6545d8-ca1b-46cf-8b61-5191cab94e50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567793011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1567793011
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3155758180
Short name T120
Test name
Test status
Simulation time 12698773587 ps
CPU time 531.43 seconds
Started Jul 27 05:16:57 PM PDT 24
Finished Jul 27 05:25:49 PM PDT 24
Peak memory 272624 kb
Host smart-86c5fbd9-9bd1-406e-8966-d0e1ac44fb8a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155758180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3155758180
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.4002248865
Short name T90
Test name
Test status
Simulation time 104904548837 ps
CPU time 3061.95 seconds
Started Jul 27 05:20:46 PM PDT 24
Finished Jul 27 06:11:49 PM PDT 24
Peak memory 289612 kb
Host smart-fa1bfdee-1698-4e89-bd18-7a420a7f7d17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002248865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.4002248865
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2918982922
Short name T125
Test name
Test status
Simulation time 12694517506 ps
CPU time 1012.36 seconds
Started Jul 27 05:16:50 PM PDT 24
Finished Jul 27 05:33:43 PM PDT 24
Peak memory 265340 kb
Host smart-5de7bafa-fc04-4137-8851-efe989982f3d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918982922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.2918982922
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2934033761
Short name T311
Test name
Test status
Simulation time 107019445693 ps
CPU time 3179.83 seconds
Started Jul 27 05:19:31 PM PDT 24
Finished Jul 27 06:12:32 PM PDT 24
Peak memory 289116 kb
Host smart-fe802611-b8c2-4bd6-a1b6-e28236817511
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934033761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2934033761
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.3462889968
Short name T160
Test name
Test status
Simulation time 6719394 ps
CPU time 1.51 seconds
Started Jul 27 05:17:24 PM PDT 24
Finished Jul 27 05:17:26 PM PDT 24
Peak memory 237484 kb
Host smart-1132736c-c498-489a-bb53-d3c6ccdcb8bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3462889968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.3462889968
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1462100683
Short name T141
Test name
Test status
Simulation time 1775828131 ps
CPU time 195.88 seconds
Started Jul 27 05:17:00 PM PDT 24
Finished Jul 27 05:20:16 PM PDT 24
Peak memory 265256 kb
Host smart-35225a9c-85b0-4b8d-961f-ddfe1f1c1143
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1462100683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1462100683
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.4188756707
Short name T323
Test name
Test status
Simulation time 148836313179 ps
CPU time 2114.89 seconds
Started Jul 27 05:18:17 PM PDT 24
Finished Jul 27 05:53:32 PM PDT 24
Peak memory 273192 kb
Host smart-b2a798c0-bc75-4850-a2ed-d7a34789c2b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188756707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.4188756707
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3553518246
Short name T69
Test name
Test status
Simulation time 14065452100 ps
CPU time 593.91 seconds
Started Jul 27 05:20:07 PM PDT 24
Finished Jul 27 05:30:01 PM PDT 24
Peak memory 248884 kb
Host smart-dbf9cd83-3dcc-4bfd-82d7-0b4c5dd1fa86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553518246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3553518246
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.73804232
Short name T132
Test name
Test status
Simulation time 18021924035 ps
CPU time 170.99 seconds
Started Jul 27 05:17:22 PM PDT 24
Finished Jul 27 05:20:14 PM PDT 24
Peak memory 265420 kb
Host smart-3f56d788-122d-430b-b3dd-9de92f059c04
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=73804232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_error
s.73804232
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.4166019685
Short name T320
Test name
Test status
Simulation time 91106458497 ps
CPU time 3040.02 seconds
Started Jul 27 05:21:08 PM PDT 24
Finished Jul 27 06:11:49 PM PDT 24
Peak memory 289588 kb
Host smart-73b430ea-d9a9-4bca-a165-0cda27ff9b20
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166019685 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.4166019685
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.2775466442
Short name T79
Test name
Test status
Simulation time 24314885472 ps
CPU time 1590.96 seconds
Started Jul 27 05:18:16 PM PDT 24
Finished Jul 27 05:44:48 PM PDT 24
Peak memory 273332 kb
Host smart-93d6f46d-45c1-4226-b5fc-5483dbed3cd1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775466442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.2775466442
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.2437711682
Short name T148
Test name
Test status
Simulation time 15487263806 ps
CPU time 1166.86 seconds
Started Jul 27 05:17:14 PM PDT 24
Finished Jul 27 05:36:41 PM PDT 24
Peak memory 273552 kb
Host smart-903f43af-e2b1-4982-95b3-df7d9ea14230
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437711682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.2437711682
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.2730892734
Short name T299
Test name
Test status
Simulation time 65498972903 ps
CPU time 607.64 seconds
Started Jul 27 05:18:47 PM PDT 24
Finished Jul 27 05:28:55 PM PDT 24
Peak memory 255576 kb
Host smart-59fba4a0-82dd-41aa-b489-3df671feae88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730892734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.2730892734
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1275251054
Short name T122
Test name
Test status
Simulation time 5550799663 ps
CPU time 94.11 seconds
Started Jul 27 05:17:14 PM PDT 24
Finished Jul 27 05:18:48 PM PDT 24
Peak memory 257424 kb
Host smart-bacd41b7-9548-4155-80b3-dc994c6055b4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1275251054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.1275251054
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.2630831271
Short name T294
Test name
Test status
Simulation time 19588968055 ps
CPU time 790.22 seconds
Started Jul 27 05:18:48 PM PDT 24
Finished Jul 27 05:31:58 PM PDT 24
Peak memory 272792 kb
Host smart-c85fc514-5884-4221-9882-acb9dfc85c71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630831271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2630831271
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.674721899
Short name T30
Test name
Test status
Simulation time 20896808140 ps
CPU time 1822.45 seconds
Started Jul 27 05:19:45 PM PDT 24
Finished Jul 27 05:50:08 PM PDT 24
Peak memory 289132 kb
Host smart-b3474900-b51d-403c-adfb-ef19b46579f8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674721899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_han
dler_stress_all.674721899
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2493168296
Short name T269
Test name
Test status
Simulation time 137697502233 ps
CPU time 3667.61 seconds
Started Jul 27 05:20:56 PM PDT 24
Finished Jul 27 06:22:04 PM PDT 24
Peak memory 301292 kb
Host smart-69af240c-76e7-4ffa-8d54-8fb1b3fdcd07
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493168296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2493168296
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.3286106319
Short name T310
Test name
Test status
Simulation time 51984850836 ps
CPU time 547.86 seconds
Started Jul 27 05:18:18 PM PDT 24
Finished Jul 27 05:27:26 PM PDT 24
Peak memory 248836 kb
Host smart-f165f9ea-f185-428b-bd9d-c404aee47046
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286106319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.3286106319
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.694754649
Short name T343
Test name
Test status
Simulation time 6662174 ps
CPU time 1.38 seconds
Started Jul 27 05:17:23 PM PDT 24
Finished Jul 27 05:17:25 PM PDT 24
Peak memory 237476 kb
Host smart-b4642a11-199f-4579-b293-a89a834b8341
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=694754649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.694754649
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3546626170
Short name T247
Test name
Test status
Simulation time 30471929636 ps
CPU time 433.97 seconds
Started Jul 27 05:18:43 PM PDT 24
Finished Jul 27 05:25:57 PM PDT 24
Peak memory 256984 kb
Host smart-99e93be9-866f-4790-a3ce-8b0a8fd8a8bb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546626170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3546626170
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2521225735
Short name T317
Test name
Test status
Simulation time 187082398734 ps
CPU time 2664.92 seconds
Started Jul 27 05:20:35 PM PDT 24
Finished Jul 27 06:05:00 PM PDT 24
Peak memory 286008 kb
Host smart-edbdc5ff-ddf9-4983-b704-b7dc866c287a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521225735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2521225735
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3840191499
Short name T146
Test name
Test status
Simulation time 9682348568 ps
CPU time 311.61 seconds
Started Jul 27 05:16:59 PM PDT 24
Finished Jul 27 05:22:10 PM PDT 24
Peak memory 265360 kb
Host smart-5a293099-0d11-42a3-89d3-398a10d562e7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840191499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3840191499
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2193679232
Short name T306
Test name
Test status
Simulation time 157217411660 ps
CPU time 572.64 seconds
Started Jul 27 05:20:48 PM PDT 24
Finished Jul 27 05:30:21 PM PDT 24
Peak memory 247664 kb
Host smart-e17be619-5336-4fca-a87a-e3e2dc57b251
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193679232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2193679232
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.1081062906
Short name T131
Test name
Test status
Simulation time 2147384550 ps
CPU time 158.83 seconds
Started Jul 27 05:16:57 PM PDT 24
Finished Jul 27 05:19:36 PM PDT 24
Peak memory 265220 kb
Host smart-13577b53-d4fe-4028-adc1-5a88c337990a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1081062906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.1081062906
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1970310885
Short name T276
Test name
Test status
Simulation time 24369324076 ps
CPU time 681.47 seconds
Started Jul 27 05:18:48 PM PDT 24
Finished Jul 27 05:30:09 PM PDT 24
Peak memory 257092 kb
Host smart-e6a5df16-2db2-4d84-b87c-af665d4fb31f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970310885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1970310885
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2932616607
Short name T246
Test name
Test status
Simulation time 64970575070 ps
CPU time 1391.74 seconds
Started Jul 27 05:18:59 PM PDT 24
Finished Jul 27 05:42:11 PM PDT 24
Peak memory 288404 kb
Host smart-415ac610-2a7f-448c-9416-5ac9e95550da
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932616607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2932616607
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1399778568
Short name T21
Test name
Test status
Simulation time 15831055856 ps
CPU time 1377.37 seconds
Started Jul 27 05:18:15 PM PDT 24
Finished Jul 27 05:41:12 PM PDT 24
Peak memory 289840 kb
Host smart-44eb9744-7f99-45f9-9ab5-35f46f2642de
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399778568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1399778568
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1187650037
Short name T70
Test name
Test status
Simulation time 652969504 ps
CPU time 46.58 seconds
Started Jul 27 05:20:33 PM PDT 24
Finished Jul 27 05:21:20 PM PDT 24
Peak memory 248564 kb
Host smart-f8c44a87-f037-4113-b180-07e5f6827cc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11876
50037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1187650037
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.336671012
Short name T163
Test name
Test status
Simulation time 79883851 ps
CPU time 3.13 seconds
Started Jul 27 05:16:48 PM PDT 24
Finished Jul 27 05:16:51 PM PDT 24
Peak memory 236596 kb
Host smart-52dc33f8-842f-4663-8fcf-6650e86e52bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=336671012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.336671012
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1481625977
Short name T625
Test name
Test status
Simulation time 46093733501 ps
CPU time 469.23 seconds
Started Jul 27 05:19:19 PM PDT 24
Finished Jul 27 05:27:09 PM PDT 24
Peak memory 248784 kb
Host smart-f0c2b58f-bc99-4027-8fa0-df9ea8b962f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481625977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1481625977
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1266804745
Short name T228
Test name
Test status
Simulation time 66131506444 ps
CPU time 1961.72 seconds
Started Jul 27 05:20:50 PM PDT 24
Finished Jul 27 05:53:32 PM PDT 24
Peak memory 284676 kb
Host smart-961bda1a-9e38-47ec-8f61-273b696976b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266804745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1266804745
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.1806883473
Short name T61
Test name
Test status
Simulation time 109209384478 ps
CPU time 9174.8 seconds
Started Jul 27 05:18:31 PM PDT 24
Finished Jul 27 07:51:26 PM PDT 24
Peak memory 394736 kb
Host smart-5c93b8bb-9e81-4606-9f45-06445b93ea11
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806883473 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.1806883473
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1237244304
Short name T118
Test name
Test status
Simulation time 9506769533 ps
CPU time 345.02 seconds
Started Jul 27 05:17:11 PM PDT 24
Finished Jul 27 05:22:56 PM PDT 24
Peak memory 265448 kb
Host smart-1feb9ad1-d900-4a92-bd3a-35ca17f839e3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237244304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1237244304
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1481604074
Short name T121
Test name
Test status
Simulation time 10932561939 ps
CPU time 188.24 seconds
Started Jul 27 05:17:01 PM PDT 24
Finished Jul 27 05:20:10 PM PDT 24
Peak memory 265376 kb
Host smart-502a8f27-52a3-4d9a-85f8-8e9b1c468896
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1481604074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1481604074
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1491670778
Short name T8
Test name
Test status
Simulation time 4740376532 ps
CPU time 108.85 seconds
Started Jul 27 05:18:29 PM PDT 24
Finished Jul 27 05:20:17 PM PDT 24
Peak memory 249116 kb
Host smart-16aa248e-fed3-43c6-9e9c-84b30a936e1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491670778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1491670778
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.3910157366
Short name T214
Test name
Test status
Simulation time 45736114 ps
CPU time 2.3 seconds
Started Jul 27 05:18:18 PM PDT 24
Finished Jul 27 05:18:20 PM PDT 24
Peak memory 249068 kb
Host smart-27191ced-77cc-4c9f-9d43-481172c9284c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3910157366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.3910157366
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.2314409378
Short name T209
Test name
Test status
Simulation time 231243181 ps
CPU time 3.25 seconds
Started Jul 27 05:18:19 PM PDT 24
Finished Jul 27 05:18:22 PM PDT 24
Peak memory 248964 kb
Host smart-160c6140-13f2-4617-8b52-e7296feae075
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2314409378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2314409378
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.301577806
Short name T201
Test name
Test status
Simulation time 159444329 ps
CPU time 3.87 seconds
Started Jul 27 05:18:47 PM PDT 24
Finished Jul 27 05:18:51 PM PDT 24
Peak memory 249156 kb
Host smart-fde1bdbe-80eb-4d3e-bf62-03375c26424e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=301577806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.301577806
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2898819161
Short name T202
Test name
Test status
Simulation time 68056782 ps
CPU time 3.88 seconds
Started Jul 27 05:18:37 PM PDT 24
Finished Jul 27 05:18:41 PM PDT 24
Peak memory 249032 kb
Host smart-9141198a-e0fb-4d13-bca5-b4e1582f8294
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2898819161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2898819161
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.777049951
Short name T239
Test name
Test status
Simulation time 73092414839 ps
CPU time 2488.15 seconds
Started Jul 27 05:19:07 PM PDT 24
Finished Jul 27 06:00:36 PM PDT 24
Peak memory 289796 kb
Host smart-f5932247-9c09-49de-ac80-7b6e9723770b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777049951 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.777049951
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.640904030
Short name T288
Test name
Test status
Simulation time 159231671345 ps
CPU time 3947.82 seconds
Started Jul 27 05:19:32 PM PDT 24
Finished Jul 27 06:25:21 PM PDT 24
Peak memory 333688 kb
Host smart-f431137b-bf00-493d-ace5-04f6f44071b6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640904030 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.640904030
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.2271149271
Short name T107
Test name
Test status
Simulation time 176017854952 ps
CPU time 2742.22 seconds
Started Jul 27 05:20:26 PM PDT 24
Finished Jul 27 06:06:08 PM PDT 24
Peak memory 288868 kb
Host smart-2ecf8cc2-3fdb-4c06-abaf-578e6e6834db
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271149271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.2271149271
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2085083770
Short name T292
Test name
Test status
Simulation time 17745831358 ps
CPU time 1464.51 seconds
Started Jul 27 05:21:00 PM PDT 24
Finished Jul 27 05:45:25 PM PDT 24
Peak memory 288064 kb
Host smart-278bbe49-f381-4e1b-9f29-5f6638a441fb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085083770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2085083770
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.3287409505
Short name T258
Test name
Test status
Simulation time 39108173457 ps
CPU time 2423.33 seconds
Started Jul 27 05:18:31 PM PDT 24
Finished Jul 27 05:58:55 PM PDT 24
Peak memory 287288 kb
Host smart-e17f44f4-76b3-4109-95a7-a195d4b76ed7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287409505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3287409505
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.2781946079
Short name T151
Test name
Test status
Simulation time 4049520112 ps
CPU time 301.83 seconds
Started Jul 27 05:17:10 PM PDT 24
Finished Jul 27 05:22:12 PM PDT 24
Peak memory 265416 kb
Host smart-d1d23e1c-1638-4aaa-9bca-045185854f6e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2781946079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.2781946079
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.1179508420
Short name T138
Test name
Test status
Simulation time 25706813800 ps
CPU time 1013.61 seconds
Started Jul 27 05:17:13 PM PDT 24
Finished Jul 27 05:34:07 PM PDT 24
Peak memory 265476 kb
Host smart-f80781cb-9799-47e6-88fb-00a841ed847e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179508420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1179508420
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.576282172
Short name T752
Test name
Test status
Simulation time 8107275 ps
CPU time 1.33 seconds
Started Jul 27 05:16:50 PM PDT 24
Finished Jul 27 05:16:52 PM PDT 24
Peak memory 236524 kb
Host smart-ea7c0f9b-2efa-4b88-b79b-f147b6262340
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=576282172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.576282172
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.2088991494
Short name T128
Test name
Test status
Simulation time 12477209011 ps
CPU time 290.09 seconds
Started Jul 27 05:17:00 PM PDT 24
Finished Jul 27 05:21:50 PM PDT 24
Peak memory 265644 kb
Host smart-a78a42ae-82fa-4868-ae02-c921e89afdaf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088991494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.2088991494
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2422089003
Short name T262
Test name
Test status
Simulation time 130970485989 ps
CPU time 2145.25 seconds
Started Jul 27 05:18:16 PM PDT 24
Finished Jul 27 05:54:01 PM PDT 24
Peak memory 289388 kb
Host smart-ccc87e32-e9c7-4832-a8ee-e90f393384fd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422089003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2422089003
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.2742182386
Short name T282
Test name
Test status
Simulation time 40222021278 ps
CPU time 3842.7 seconds
Started Jul 27 05:18:17 PM PDT 24
Finished Jul 27 06:22:20 PM PDT 24
Peak memory 337564 kb
Host smart-b1eed934-2123-41f2-960c-d55488cf7270
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742182386 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.2742182386
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3293896415
Short name T305
Test name
Test status
Simulation time 14876666036 ps
CPU time 332.84 seconds
Started Jul 27 05:18:30 PM PDT 24
Finished Jul 27 05:24:03 PM PDT 24
Peak memory 248912 kb
Host smart-8f3ec662-ecda-4c3d-b46b-f5bb23313614
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293896415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3293896415
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3675172942
Short name T337
Test name
Test status
Simulation time 86566826865 ps
CPU time 2462.75 seconds
Started Jul 27 05:18:46 PM PDT 24
Finished Jul 27 05:59:49 PM PDT 24
Peak memory 273248 kb
Host smart-9a3aca67-77db-4f55-b512-3430816b12bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675172942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3675172942
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3153802397
Short name T84
Test name
Test status
Simulation time 48801511870 ps
CPU time 2835.72 seconds
Started Jul 27 05:18:37 PM PDT 24
Finished Jul 27 06:05:54 PM PDT 24
Peak memory 300156 kb
Host smart-818dbcac-d146-4ca7-aa39-a6ac871a7f8f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153802397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3153802397
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.1584005784
Short name T327
Test name
Test status
Simulation time 52912793437 ps
CPU time 1542.03 seconds
Started Jul 27 05:18:46 PM PDT 24
Finished Jul 27 05:44:28 PM PDT 24
Peak memory 273480 kb
Host smart-cb609c91-7a62-4fca-b913-ce4d5d460889
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584005784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1584005784
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.2006102163
Short name T195
Test name
Test status
Simulation time 84794460347 ps
CPU time 5288.63 seconds
Started Jul 27 05:18:49 PM PDT 24
Finished Jul 27 06:46:58 PM PDT 24
Peak memory 316880 kb
Host smart-688638cf-2816-4185-a411-5b625f1cff37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2006102163 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.2006102163
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1644071755
Short name T307
Test name
Test status
Simulation time 58503510453 ps
CPU time 580.02 seconds
Started Jul 27 05:18:46 PM PDT 24
Finished Jul 27 05:28:26 PM PDT 24
Peak memory 247904 kb
Host smart-0fae304b-3982-48ba-8dbc-caf5f9235c52
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644071755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1644071755
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.1378026598
Short name T677
Test name
Test status
Simulation time 40922232984 ps
CPU time 2304.26 seconds
Started Jul 27 05:19:19 PM PDT 24
Finished Jul 27 05:57:44 PM PDT 24
Peak memory 289064 kb
Host smart-88ff85ed-b28d-4a14-adb5-dde12302e107
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378026598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1378026598
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.163343423
Short name T60
Test name
Test status
Simulation time 1604942148 ps
CPU time 31.93 seconds
Started Jul 27 05:19:21 PM PDT 24
Finished Jul 27 05:19:53 PM PDT 24
Peak memory 256212 kb
Host smart-ac90301f-486c-40c0-bb38-07a3081abb7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16334
3423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.163343423
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.4132834542
Short name T75
Test name
Test status
Simulation time 78124914395 ps
CPU time 1236.56 seconds
Started Jul 27 05:19:34 PM PDT 24
Finished Jul 27 05:40:11 PM PDT 24
Peak memory 281452 kb
Host smart-773e2afe-5cbf-485f-a9d0-256d4c9ed351
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132834542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.4132834542
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.3589462750
Short name T80
Test name
Test status
Simulation time 13345390328 ps
CPU time 1169.15 seconds
Started Jul 27 05:19:30 PM PDT 24
Finished Jul 27 05:39:00 PM PDT 24
Peak memory 289312 kb
Host smart-98af3078-a617-4d50-9cc9-25311f6ae0c6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589462750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.3589462750
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2283149128
Short name T181
Test name
Test status
Simulation time 9560366402 ps
CPU time 879.36 seconds
Started Jul 27 05:18:17 PM PDT 24
Finished Jul 27 05:32:57 PM PDT 24
Peak memory 273160 kb
Host smart-c6514b09-325e-4392-a938-c6e05832924b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283149128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2283149128
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.3608180521
Short name T267
Test name
Test status
Simulation time 7202136335 ps
CPU time 457.92 seconds
Started Jul 27 05:18:26 PM PDT 24
Finished Jul 27 05:26:04 PM PDT 24
Peak memory 256992 kb
Host smart-4a0fcafd-f592-416f-9e0e-d0b65ea6e7c8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608180521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.3608180521
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.580521940
Short name T97
Test name
Test status
Simulation time 51290131599 ps
CPU time 770.03 seconds
Started Jul 27 05:18:29 PM PDT 24
Finished Jul 27 05:31:20 PM PDT 24
Peak memory 272084 kb
Host smart-f7f51d33-772e-480d-a255-bcba11a01367
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580521940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.580521940
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1837958788
Short name T126
Test name
Test status
Simulation time 4220133501 ps
CPU time 673.6 seconds
Started Jul 27 05:17:15 PM PDT 24
Finished Jul 27 05:28:29 PM PDT 24
Peak memory 273536 kb
Host smart-aa2a65ca-0889-4aa6-931d-b1c71a66f679
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837958788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.1837958788
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.682582984
Short name T166
Test name
Test status
Simulation time 67003544 ps
CPU time 4.68 seconds
Started Jul 27 05:17:15 PM PDT 24
Finished Jul 27 05:17:20 PM PDT 24
Peak memory 237732 kb
Host smart-2fed1efc-6f4e-4590-904c-111280430c3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=682582984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.682582984
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.1054101906
Short name T173
Test name
Test status
Simulation time 110745577 ps
CPU time 3.98 seconds
Started Jul 27 05:17:22 PM PDT 24
Finished Jul 27 05:17:27 PM PDT 24
Peak memory 237808 kb
Host smart-8c08780d-ee21-4715-a6be-fa5cd6520b66
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1054101906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.1054101906
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.249286093
Short name T169
Test name
Test status
Simulation time 39792518 ps
CPU time 3.45 seconds
Started Jul 27 05:17:22 PM PDT 24
Finished Jul 27 05:17:26 PM PDT 24
Peak memory 237840 kb
Host smart-b526a46c-3c18-4f2f-9f8b-7ee5290e1d6c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=249286093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.249286093
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.687597069
Short name T159
Test name
Test status
Simulation time 4521535283 ps
CPU time 77.96 seconds
Started Jul 27 05:17:00 PM PDT 24
Finished Jul 27 05:18:18 PM PDT 24
Peak memory 240476 kb
Host smart-baa436b5-3975-49ac-a844-46669af540f9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=687597069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.687597069
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.77565770
Short name T165
Test name
Test status
Simulation time 126002251 ps
CPU time 3.07 seconds
Started Jul 27 05:17:01 PM PDT 24
Finished Jul 27 05:17:04 PM PDT 24
Peak memory 237484 kb
Host smart-a06db10a-fcc8-4ae2-90d6-849db9eb3064
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=77565770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.77565770
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2643626059
Short name T167
Test name
Test status
Simulation time 753677905 ps
CPU time 45.08 seconds
Started Jul 27 05:17:00 PM PDT 24
Finished Jul 27 05:17:45 PM PDT 24
Peak memory 237496 kb
Host smart-04b6f97a-f475-4bf8-9831-0cd942eee55f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2643626059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2643626059
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.2427802061
Short name T158
Test name
Test status
Simulation time 317614599 ps
CPU time 47.18 seconds
Started Jul 27 05:16:50 PM PDT 24
Finished Jul 27 05:17:37 PM PDT 24
Peak memory 237452 kb
Host smart-279e7c87-1e4f-4d6b-9f6f-837c18457f3f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2427802061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.2427802061
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.3616780230
Short name T171
Test name
Test status
Simulation time 78158300 ps
CPU time 2.22 seconds
Started Jul 27 05:17:12 PM PDT 24
Finished Jul 27 05:17:14 PM PDT 24
Peak memory 237488 kb
Host smart-3a476533-3361-49f7-9e60-7ffb9850cc93
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3616780230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.3616780230
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.1774917601
Short name T127
Test name
Test status
Simulation time 5720999085 ps
CPU time 357.8 seconds
Started Jul 27 05:17:11 PM PDT 24
Finished Jul 27 05:23:09 PM PDT 24
Peak memory 273492 kb
Host smart-808c9f99-4f4d-4dd7-9b4d-a779d29e071c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1774917601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.1774917601
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.4001754401
Short name T179
Test name
Test status
Simulation time 845200652 ps
CPU time 38.61 seconds
Started Jul 27 05:17:10 PM PDT 24
Finished Jul 27 05:17:48 PM PDT 24
Peak memory 237648 kb
Host smart-a6e71100-f521-4c8b-bdc1-49afe0c32da1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4001754401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.4001754401
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.118694871
Short name T130
Test name
Test status
Simulation time 55027560993 ps
CPU time 1060.05 seconds
Started Jul 27 05:17:21 PM PDT 24
Finished Jul 27 05:35:01 PM PDT 24
Peak memory 265320 kb
Host smart-e10c756f-a715-48ac-9379-7dc4599130a4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118694871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.118694871
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.842228956
Short name T150
Test name
Test status
Simulation time 3846382790 ps
CPU time 263.75 seconds
Started Jul 27 05:17:23 PM PDT 24
Finished Jul 27 05:21:47 PM PDT 24
Peak memory 271304 kb
Host smart-bc3fc22f-32e3-4f2a-b6a7-0a1253a5c830
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=842228956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_erro
rs.842228956
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.1798940856
Short name T168
Test name
Test status
Simulation time 187648569 ps
CPU time 23.83 seconds
Started Jul 27 05:16:57 PM PDT 24
Finished Jul 27 05:17:21 PM PDT 24
Peak memory 240416 kb
Host smart-a3e0f2ef-1eda-4f84-b7fb-c3f8e8cff2e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1798940856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.1798940856
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2547955706
Short name T170
Test name
Test status
Simulation time 3037957594 ps
CPU time 36.87 seconds
Started Jul 27 05:17:10 PM PDT 24
Finished Jul 27 05:17:47 PM PDT 24
Peak memory 240424 kb
Host smart-8482161d-d4d6-4539-b8fa-bf38bd749d3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2547955706 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2547955706
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.457151133
Short name T164
Test name
Test status
Simulation time 170312324 ps
CPU time 3.68 seconds
Started Jul 27 05:17:22 PM PDT 24
Finished Jul 27 05:17:25 PM PDT 24
Peak memory 237448 kb
Host smart-23dd1133-3525-43f3-9380-efa135a3f0fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=457151133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.457151133
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1130739579
Short name T174
Test name
Test status
Simulation time 58830210 ps
CPU time 2.79 seconds
Started Jul 27 05:16:56 PM PDT 24
Finished Jul 27 05:16:59 PM PDT 24
Peak memory 236572 kb
Host smart-e46fcc6b-894e-4bd5-be52-e640bd5d1635
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1130739579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1130739579
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.2858562562
Short name T177
Test name
Test status
Simulation time 4168626302 ps
CPU time 38.24 seconds
Started Jul 27 05:17:11 PM PDT 24
Finished Jul 27 05:17:50 PM PDT 24
Peak memory 240428 kb
Host smart-002d8c56-3bb2-4b1b-8661-cefef3400cec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2858562562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.2858562562
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.1372495525
Short name T22
Test name
Test status
Simulation time 50673505927 ps
CPU time 553.75 seconds
Started Jul 27 05:19:17 PM PDT 24
Finished Jul 27 05:28:31 PM PDT 24
Peak memory 270144 kb
Host smart-6b8af840-20b1-4b26-b589-824518498881
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372495525 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.1372495525
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1285628113
Short name T782
Test name
Test status
Simulation time 6730868948 ps
CPU time 262.18 seconds
Started Jul 27 05:16:50 PM PDT 24
Finished Jul 27 05:21:13 PM PDT 24
Peak memory 242064 kb
Host smart-ecb53b87-0be1-40e6-b1cc-71dcecde9249
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1285628113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1285628113
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.3378124345
Short name T800
Test name
Test status
Simulation time 2883657080 ps
CPU time 188.77 seconds
Started Jul 27 05:16:52 PM PDT 24
Finished Jul 27 05:20:01 PM PDT 24
Peak memory 236648 kb
Host smart-9b7c96fa-681a-4cd4-901d-400a0a6da687
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3378124345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3378124345
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2392885733
Short name T732
Test name
Test status
Simulation time 472406326 ps
CPU time 8.71 seconds
Started Jul 27 05:16:50 PM PDT 24
Finished Jul 27 05:16:59 PM PDT 24
Peak memory 248956 kb
Host smart-14fa3354-6685-458c-aaca-9ef30a856f01
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2392885733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2392885733
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.3693702258
Short name T780
Test name
Test status
Simulation time 121329007 ps
CPU time 5.15 seconds
Started Jul 27 05:16:50 PM PDT 24
Finished Jul 27 05:16:56 PM PDT 24
Peak memory 256828 kb
Host smart-d6dce4ee-b7ec-475a-aade-24c489e34af5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693702258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.3693702258
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.3766209068
Short name T175
Test name
Test status
Simulation time 97061373 ps
CPU time 4.75 seconds
Started Jul 27 05:16:52 PM PDT 24
Finished Jul 27 05:16:57 PM PDT 24
Peak memory 237408 kb
Host smart-ae9b8827-33b1-447f-93a5-2703a35275a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3766209068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.3766209068
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.830515679
Short name T811
Test name
Test status
Simulation time 8438270 ps
CPU time 1.42 seconds
Started Jul 27 05:16:48 PM PDT 24
Finished Jul 27 05:16:50 PM PDT 24
Peak memory 237436 kb
Host smart-fec604a2-256c-4fff-ab43-33700eb5ddf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=830515679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.830515679
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2056626809
Short name T751
Test name
Test status
Simulation time 218587109 ps
CPU time 13.79 seconds
Started Jul 27 05:16:50 PM PDT 24
Finished Jul 27 05:17:04 PM PDT 24
Peak memory 245688 kb
Host smart-3f220de5-76d0-45a3-9015-d39f8763a3a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2056626809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2056626809
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.1089681158
Short name T799
Test name
Test status
Simulation time 6584758074 ps
CPU time 465.03 seconds
Started Jul 27 05:16:50 PM PDT 24
Finished Jul 27 05:24:35 PM PDT 24
Peak memory 269928 kb
Host smart-9843c16d-1973-4087-bddc-d9317602d9c2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089681158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.1089681158
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3933139577
Short name T728
Test name
Test status
Simulation time 259337078 ps
CPU time 10.35 seconds
Started Jul 27 05:16:50 PM PDT 24
Finished Jul 27 05:17:00 PM PDT 24
Peak memory 249808 kb
Host smart-84bd7d3f-6dcb-4c35-a4ea-744009cce3a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3933139577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3933139577
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3251744116
Short name T805
Test name
Test status
Simulation time 1916480702 ps
CPU time 70.55 seconds
Started Jul 27 05:17:04 PM PDT 24
Finished Jul 27 05:18:15 PM PDT 24
Peak memory 237472 kb
Host smart-7ebcb051-9f97-4005-abae-96d1e73c573c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3251744116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3251744116
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1318580833
Short name T731
Test name
Test status
Simulation time 4330668651 ps
CPU time 265.58 seconds
Started Jul 27 05:16:58 PM PDT 24
Finished Jul 27 05:21:24 PM PDT 24
Peak memory 240388 kb
Host smart-869c784e-8115-4bcb-aee7-f99a5a97b0ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1318580833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1318580833
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.893874729
Short name T825
Test name
Test status
Simulation time 101374654 ps
CPU time 8.95 seconds
Started Jul 27 05:16:51 PM PDT 24
Finished Jul 27 05:17:01 PM PDT 24
Peak memory 249144 kb
Host smart-b61238e6-4477-4819-890f-93d5e19c971c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=893874729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.893874729
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1156438797
Short name T196
Test name
Test status
Simulation time 684738147 ps
CPU time 9.53 seconds
Started Jul 27 05:16:59 PM PDT 24
Finished Jul 27 05:17:09 PM PDT 24
Peak memory 251664 kb
Host smart-4e4fe728-8fec-40fd-b2e6-3f1221648c9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156438797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1156438797
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1810204406
Short name T787
Test name
Test status
Simulation time 35817675 ps
CPU time 3.36 seconds
Started Jul 27 05:16:58 PM PDT 24
Finished Jul 27 05:17:01 PM PDT 24
Peak memory 237476 kb
Host smart-90f32bc4-7c74-4535-abeb-d036e396649f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1810204406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1810204406
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1105575367
Short name T813
Test name
Test status
Simulation time 1082018577 ps
CPU time 20.48 seconds
Started Jul 27 05:16:58 PM PDT 24
Finished Jul 27 05:17:18 PM PDT 24
Peak memory 245692 kb
Host smart-30f1bb9d-7d89-4150-ba35-e243b2b0edaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1105575367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1105575367
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2320939509
Short name T139
Test name
Test status
Simulation time 7370636131 ps
CPU time 130.44 seconds
Started Jul 27 05:16:51 PM PDT 24
Finished Jul 27 05:19:02 PM PDT 24
Peak memory 265440 kb
Host smart-d592e807-7fe2-40f0-909c-0321da095d05
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2320939509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2320939509
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.1507350102
Short name T776
Test name
Test status
Simulation time 59307281 ps
CPU time 8.38 seconds
Started Jul 27 05:16:50 PM PDT 24
Finished Jul 27 05:16:59 PM PDT 24
Peak memory 254176 kb
Host smart-f0a77e7c-68fe-48bc-b700-da311c602a94
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1507350102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.1507350102
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2436026133
Short name T725
Test name
Test status
Simulation time 129475102 ps
CPU time 8.4 seconds
Started Jul 27 05:17:11 PM PDT 24
Finished Jul 27 05:17:20 PM PDT 24
Peak memory 239992 kb
Host smart-99eab2e4-91ef-41a9-878e-3d6fda472005
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436026133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2436026133
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1925134173
Short name T826
Test name
Test status
Simulation time 34564277 ps
CPU time 5.83 seconds
Started Jul 27 05:17:12 PM PDT 24
Finished Jul 27 05:17:18 PM PDT 24
Peak memory 240384 kb
Host smart-d85de9b3-d72d-48cc-88d8-4fe831cedf63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1925134173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1925134173
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2821631375
Short name T750
Test name
Test status
Simulation time 15134832 ps
CPU time 1.31 seconds
Started Jul 27 05:17:11 PM PDT 24
Finished Jul 27 05:17:13 PM PDT 24
Peak memory 237324 kb
Host smart-0758e83c-bd56-41af-9bdc-9943ceddabad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2821631375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.2821631375
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.894868299
Short name T822
Test name
Test status
Simulation time 182263082 ps
CPU time 23.88 seconds
Started Jul 27 05:17:14 PM PDT 24
Finished Jul 27 05:17:38 PM PDT 24
Peak memory 248528 kb
Host smart-50d64d18-e283-4b3b-8bab-2007e0d5abf5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=894868299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_out
standing.894868299
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2093232121
Short name T149
Test name
Test status
Simulation time 2616016949 ps
CPU time 197.78 seconds
Started Jul 27 05:17:12 PM PDT 24
Finished Jul 27 05:20:30 PM PDT 24
Peak memory 265384 kb
Host smart-5651cd8f-9fb0-4a9d-aed3-328b1dc5ee38
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2093232121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.2093232121
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3865235490
Short name T140
Test name
Test status
Simulation time 18021555017 ps
CPU time 1121.43 seconds
Started Jul 27 05:17:15 PM PDT 24
Finished Jul 27 05:35:57 PM PDT 24
Peak memory 265328 kb
Host smart-9f85b473-5033-4d5c-9254-3a56d6951747
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865235490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3865235490
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.3168068324
Short name T814
Test name
Test status
Simulation time 385642169 ps
CPU time 16.07 seconds
Started Jul 27 05:17:10 PM PDT 24
Finished Jul 27 05:17:26 PM PDT 24
Peak memory 254728 kb
Host smart-3089d165-43a5-4952-82fe-2d694fbca43c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3168068324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.3168068324
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.364784821
Short name T804
Test name
Test status
Simulation time 126875925 ps
CPU time 5.48 seconds
Started Jul 27 05:17:10 PM PDT 24
Finished Jul 27 05:17:16 PM PDT 24
Peak memory 256672 kb
Host smart-bcdf4ce1-330f-4cec-89fb-3d344e9889ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364784821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 11.alert_handler_csr_mem_rw_with_rand_reset.364784821
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1778374698
Short name T744
Test name
Test status
Simulation time 244454780 ps
CPU time 9.35 seconds
Started Jul 27 05:17:13 PM PDT 24
Finished Jul 27 05:17:22 PM PDT 24
Peak memory 240308 kb
Host smart-5d21eebe-eb96-4474-b616-a36cebdf5983
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1778374698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1778374698
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3995127245
Short name T708
Test name
Test status
Simulation time 9150812 ps
CPU time 1.48 seconds
Started Jul 27 05:17:11 PM PDT 24
Finished Jul 27 05:17:12 PM PDT 24
Peak memory 237488 kb
Host smart-5cdb176a-12a4-4c64-a853-be7d35cc6ed7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3995127245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3995127245
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.3058905476
Short name T191
Test name
Test status
Simulation time 969567227 ps
CPU time 18.24 seconds
Started Jul 27 05:17:14 PM PDT 24
Finished Jul 27 05:17:32 PM PDT 24
Peak memory 245872 kb
Host smart-b26e4d85-9566-45ff-844f-f640d49ea03f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3058905476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.3058905476
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.95861387
Short name T713
Test name
Test status
Simulation time 1020902273 ps
CPU time 11.27 seconds
Started Jul 27 05:17:10 PM PDT 24
Finished Jul 27 05:17:22 PM PDT 24
Peak memory 256740 kb
Host smart-4cb6193d-9ddf-4c15-aca3-7d2bdff48b07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=95861387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.95861387
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3570745045
Short name T761
Test name
Test status
Simulation time 51545253 ps
CPU time 3.41 seconds
Started Jul 27 05:17:13 PM PDT 24
Finished Jul 27 05:17:16 PM PDT 24
Peak memory 237704 kb
Host smart-ef3bfe85-cb93-4b4e-9402-d2848a311e47
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3570745045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3570745045
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3651333474
Short name T715
Test name
Test status
Simulation time 2477223697 ps
CPU time 13.53 seconds
Started Jul 27 05:17:12 PM PDT 24
Finished Jul 27 05:17:26 PM PDT 24
Peak memory 251984 kb
Host smart-c4628127-c6ac-46b9-9fb8-2c0b8cd6eaea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651333474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3651333474
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.6250158
Short name T778
Test name
Test status
Simulation time 64520712 ps
CPU time 5.18 seconds
Started Jul 27 05:17:11 PM PDT 24
Finished Jul 27 05:17:16 PM PDT 24
Peak memory 237404 kb
Host smart-9259ccf0-eb0d-4be2-b26a-363e74d3dd20
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=6250158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.6250158
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3084568793
Short name T820
Test name
Test status
Simulation time 26531727 ps
CPU time 1.45 seconds
Started Jul 27 05:17:10 PM PDT 24
Finished Jul 27 05:17:11 PM PDT 24
Peak memory 237484 kb
Host smart-2ff5d8fc-5f3a-4f5f-b5e4-ba6f0a19da1b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3084568793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3084568793
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.3659966186
Short name T735
Test name
Test status
Simulation time 2760435658 ps
CPU time 45.24 seconds
Started Jul 27 05:17:10 PM PDT 24
Finished Jul 27 05:17:55 PM PDT 24
Peak memory 248704 kb
Host smart-150c88c6-64af-414d-80fe-b32d4bc32dc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3659966186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.3659966186
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.3624222869
Short name T768
Test name
Test status
Simulation time 81914116 ps
CPU time 10.31 seconds
Started Jul 27 05:17:16 PM PDT 24
Finished Jul 27 05:17:26 PM PDT 24
Peak memory 248276 kb
Host smart-e21e4066-7f72-4807-8801-e8c9235d6652
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3624222869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.3624222869
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.2212380865
Short name T819
Test name
Test status
Simulation time 58240229 ps
CPU time 2.19 seconds
Started Jul 27 05:17:11 PM PDT 24
Finished Jul 27 05:17:13 PM PDT 24
Peak memory 236552 kb
Host smart-117853aa-87a9-4f46-8b4a-dabeae61a860
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2212380865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2212380865
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3376807762
Short name T764
Test name
Test status
Simulation time 32945938 ps
CPU time 5.73 seconds
Started Jul 27 05:17:12 PM PDT 24
Finished Jul 27 05:17:18 PM PDT 24
Peak memory 256560 kb
Host smart-67544dd7-9277-403b-af02-8bf0d94f1e4e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376807762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.3376807762
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1153463316
Short name T727
Test name
Test status
Simulation time 39670057 ps
CPU time 3.63 seconds
Started Jul 27 05:17:12 PM PDT 24
Finished Jul 27 05:17:16 PM PDT 24
Peak memory 237432 kb
Host smart-3056278b-607e-4c5b-a226-01aa902fb439
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1153463316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.1153463316
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3561025571
Short name T790
Test name
Test status
Simulation time 16522219 ps
CPU time 1.46 seconds
Started Jul 27 05:17:14 PM PDT 24
Finished Jul 27 05:17:16 PM PDT 24
Peak memory 237452 kb
Host smart-2e6a1924-6425-4a5c-a7c5-a57148772ea8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3561025571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3561025571
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.2249503921
Short name T755
Test name
Test status
Simulation time 243803812 ps
CPU time 17.19 seconds
Started Jul 27 05:17:13 PM PDT 24
Finished Jul 27 05:17:31 PM PDT 24
Peak memory 244712 kb
Host smart-06ce96bc-223d-4ef0-81d7-4878e7c090da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2249503921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.2249503921
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3214521978
Short name T796
Test name
Test status
Simulation time 100743417 ps
CPU time 12.17 seconds
Started Jul 27 05:17:13 PM PDT 24
Finished Jul 27 05:17:26 PM PDT 24
Peak memory 248656 kb
Host smart-4c2638f2-1ca4-40db-bd3f-17fd482ec430
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3214521978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3214521978
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2606723537
Short name T786
Test name
Test status
Simulation time 473642153 ps
CPU time 9.63 seconds
Started Jul 27 05:17:12 PM PDT 24
Finished Jul 27 05:17:22 PM PDT 24
Peak memory 256644 kb
Host smart-9e7a3a3c-717a-479d-a309-86b31b1903a6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606723537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2606723537
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3470359756
Short name T194
Test name
Test status
Simulation time 369758009 ps
CPU time 9.04 seconds
Started Jul 27 05:17:12 PM PDT 24
Finished Jul 27 05:17:21 PM PDT 24
Peak memory 237328 kb
Host smart-21291931-02d5-4704-a5a8-3fb9a23c050d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3470359756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3470359756
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2106425558
Short name T707
Test name
Test status
Simulation time 9671714 ps
CPU time 1.58 seconds
Started Jul 27 05:17:12 PM PDT 24
Finished Jul 27 05:17:14 PM PDT 24
Peak memory 236568 kb
Host smart-4b2417b3-c687-453c-9040-001c84bd807f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2106425558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2106425558
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3013043100
Short name T816
Test name
Test status
Simulation time 248822161 ps
CPU time 17.2 seconds
Started Jul 27 05:17:14 PM PDT 24
Finished Jul 27 05:17:32 PM PDT 24
Peak memory 244744 kb
Host smart-2440b66c-9491-4e78-a7cb-638b60cc3c2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3013043100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.3013043100
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.2201723743
Short name T124
Test name
Test status
Simulation time 6180486371 ps
CPU time 144.64 seconds
Started Jul 27 05:17:11 PM PDT 24
Finished Jul 27 05:19:36 PM PDT 24
Peak memory 267056 kb
Host smart-d0dc05f1-8b8a-40ea-bc9d-6d2510def134
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2201723743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.2201723743
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3817900093
Short name T714
Test name
Test status
Simulation time 755601735 ps
CPU time 8.11 seconds
Started Jul 27 05:17:13 PM PDT 24
Finished Jul 27 05:17:21 PM PDT 24
Peak memory 253732 kb
Host smart-f2f88b6d-3a5a-4fbc-a2ca-8b33bc27302c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3817900093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3817900093
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.256799748
Short name T784
Test name
Test status
Simulation time 142407916 ps
CPU time 12.56 seconds
Started Jul 27 05:17:11 PM PDT 24
Finished Jul 27 05:17:24 PM PDT 24
Peak memory 250796 kb
Host smart-99f8c8a2-58e7-43e0-9b7d-d17da6b1a56f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256799748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 15.alert_handler_csr_mem_rw_with_rand_reset.256799748
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.241297006
Short name T188
Test name
Test status
Simulation time 323325366 ps
CPU time 4.12 seconds
Started Jul 27 05:17:15 PM PDT 24
Finished Jul 27 05:17:19 PM PDT 24
Peak memory 237488 kb
Host smart-fbe78cc8-0be1-4401-9485-e7dbb9af5da9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=241297006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.241297006
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.3171811102
Short name T235
Test name
Test status
Simulation time 12397208 ps
CPU time 1.34 seconds
Started Jul 27 05:17:14 PM PDT 24
Finished Jul 27 05:17:16 PM PDT 24
Peak memory 236508 kb
Host smart-dcc3eee1-48af-412b-846e-cd01e359ee5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3171811102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.3171811102
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3142434878
Short name T756
Test name
Test status
Simulation time 93514973 ps
CPU time 10.38 seconds
Started Jul 27 05:17:14 PM PDT 24
Finished Jul 27 05:17:25 PM PDT 24
Peak memory 244740 kb
Host smart-3406a1bb-01f7-47d7-89ae-5ec4be8e5298
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3142434878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.3142434878
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2193134213
Short name T155
Test name
Test status
Simulation time 8553046602 ps
CPU time 167.34 seconds
Started Jul 27 05:17:12 PM PDT 24
Finished Jul 27 05:19:59 PM PDT 24
Peak memory 265468 kb
Host smart-c31044a5-23cb-4cec-a51f-dfb46fd58205
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2193134213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.2193134213
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.1244678937
Short name T144
Test name
Test status
Simulation time 5837905321 ps
CPU time 425.16 seconds
Started Jul 27 05:17:09 PM PDT 24
Finished Jul 27 05:24:15 PM PDT 24
Peak memory 265412 kb
Host smart-adcf024d-fbd3-425d-b848-abd1df6be0b4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244678937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.1244678937
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1199506251
Short name T807
Test name
Test status
Simulation time 271493374 ps
CPU time 16.67 seconds
Started Jul 27 05:17:14 PM PDT 24
Finished Jul 27 05:17:31 PM PDT 24
Peak memory 249796 kb
Host smart-4290e7c5-bd19-4eb3-b485-841c314cd2a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1199506251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1199506251
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.394656620
Short name T771
Test name
Test status
Simulation time 57020595 ps
CPU time 4.64 seconds
Started Jul 27 05:17:21 PM PDT 24
Finished Jul 27 05:17:25 PM PDT 24
Peak memory 240844 kb
Host smart-024ed0e4-83c2-4695-894e-f240ee0d4541
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394656620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.394656620
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.4129961624
Short name T176
Test name
Test status
Simulation time 68840690 ps
CPU time 5.8 seconds
Started Jul 27 05:17:24 PM PDT 24
Finished Jul 27 05:17:30 PM PDT 24
Peak memory 237444 kb
Host smart-9cb9da11-de01-4c52-8e0d-c0817633bb30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4129961624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.4129961624
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.334502815
Short name T340
Test name
Test status
Simulation time 31702829 ps
CPU time 1.25 seconds
Started Jul 27 05:17:23 PM PDT 24
Finished Jul 27 05:17:24 PM PDT 24
Peak memory 236604 kb
Host smart-0bbed666-2642-4a21-b961-608cd7611c96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=334502815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.334502815
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1338622914
Short name T812
Test name
Test status
Simulation time 6699162887 ps
CPU time 23.82 seconds
Started Jul 27 05:17:22 PM PDT 24
Finished Jul 27 05:17:47 PM PDT 24
Peak memory 248692 kb
Host smart-143d5672-9da9-40c9-8a39-e0218794af65
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1338622914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1338622914
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.964278107
Short name T133
Test name
Test status
Simulation time 10401730593 ps
CPU time 208.53 seconds
Started Jul 27 05:17:23 PM PDT 24
Finished Jul 27 05:20:51 PM PDT 24
Peak memory 265428 kb
Host smart-d6a7d077-cdc7-485a-ae7e-4cf1c01a0dfb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=964278107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_erro
rs.964278107
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3034371681
Short name T242
Test name
Test status
Simulation time 176376692 ps
CPU time 11.51 seconds
Started Jul 27 05:17:23 PM PDT 24
Finished Jul 27 05:17:35 PM PDT 24
Peak memory 248596 kb
Host smart-52628330-1e64-4d2b-a485-9ead8e55236b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3034371681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3034371681
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3864686723
Short name T791
Test name
Test status
Simulation time 206027436 ps
CPU time 8.78 seconds
Started Jul 27 05:17:24 PM PDT 24
Finished Jul 27 05:17:33 PM PDT 24
Peak memory 253380 kb
Host smart-0a20a2c0-dfa5-4d55-8600-ccb5ead57242
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864686723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.3864686723
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3696890702
Short name T730
Test name
Test status
Simulation time 72382342 ps
CPU time 3.14 seconds
Started Jul 27 05:17:24 PM PDT 24
Finished Jul 27 05:17:27 PM PDT 24
Peak memory 236592 kb
Host smart-99fbf02e-faac-417d-9357-c5db922ead2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3696890702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3696890702
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.2484333583
Short name T717
Test name
Test status
Simulation time 23088774 ps
CPU time 2.07 seconds
Started Jul 27 05:17:23 PM PDT 24
Finished Jul 27 05:17:25 PM PDT 24
Peak memory 237496 kb
Host smart-ee274c2b-9cf9-4b36-9389-d9d25d5a8197
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2484333583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.2484333583
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.1017110316
Short name T809
Test name
Test status
Simulation time 4869000799 ps
CPU time 41.41 seconds
Started Jul 27 05:17:22 PM PDT 24
Finished Jul 27 05:18:04 PM PDT 24
Peak memory 248696 kb
Host smart-a662a5dc-938e-4543-aaa5-9fb326b88c68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1017110316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.1017110316
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.397620836
Short name T154
Test name
Test status
Simulation time 8426020413 ps
CPU time 137.74 seconds
Started Jul 27 05:17:20 PM PDT 24
Finished Jul 27 05:19:38 PM PDT 24
Peak memory 265436 kb
Host smart-9af5af45-76ab-40ad-a4c5-51785f6cbf9a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=397620836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_erro
rs.397620836
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.2634189930
Short name T767
Test name
Test status
Simulation time 288833125 ps
CPU time 11.06 seconds
Started Jul 27 05:17:25 PM PDT 24
Finished Jul 27 05:17:37 PM PDT 24
Peak memory 254940 kb
Host smart-f179fb1e-6ced-4fbc-9958-cecfcb4c9a3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2634189930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.2634189930
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.1153494051
Short name T709
Test name
Test status
Simulation time 146895050 ps
CPU time 6.74 seconds
Started Jul 27 05:17:23 PM PDT 24
Finished Jul 27 05:17:30 PM PDT 24
Peak memory 239740 kb
Host smart-ad5c06ab-2db1-4c97-a302-cb1699b1ba2d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153494051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.1153494051
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.618506746
Short name T739
Test name
Test status
Simulation time 216545711 ps
CPU time 5.12 seconds
Started Jul 27 05:17:20 PM PDT 24
Finished Jul 27 05:17:26 PM PDT 24
Peak memory 240316 kb
Host smart-36b40356-e5c1-4249-b0d2-2ce3b26bddf2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=618506746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.618506746
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2355611666
Short name T802
Test name
Test status
Simulation time 381646590 ps
CPU time 17.03 seconds
Started Jul 27 05:17:22 PM PDT 24
Finished Jul 27 05:17:39 PM PDT 24
Peak memory 245664 kb
Host smart-4f7eaf7a-b774-464f-b086-3b18707a3a8d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2355611666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.2355611666
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.4237631654
Short name T134
Test name
Test status
Simulation time 50981136723 ps
CPU time 1013.97 seconds
Started Jul 27 05:17:23 PM PDT 24
Finished Jul 27 05:34:17 PM PDT 24
Peak memory 265408 kb
Host smart-f1320172-b8c4-4147-b98d-0061a4bb5b1f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237631654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.4237631654
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.2729492975
Short name T748
Test name
Test status
Simulation time 526310224 ps
CPU time 10.66 seconds
Started Jul 27 05:17:23 PM PDT 24
Finished Jul 27 05:17:34 PM PDT 24
Peak memory 247732 kb
Host smart-84e41024-ecd4-4f46-8dcc-2713c4b94b63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2729492975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.2729492975
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2282653121
Short name T801
Test name
Test status
Simulation time 267737386 ps
CPU time 11.55 seconds
Started Jul 27 05:17:21 PM PDT 24
Finished Jul 27 05:17:33 PM PDT 24
Peak memory 252916 kb
Host smart-6c2a2767-a9cb-4160-9a61-5d20ccb4f4cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282653121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2282653121
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.413769365
Short name T779
Test name
Test status
Simulation time 33917534 ps
CPU time 4.87 seconds
Started Jul 27 05:17:21 PM PDT 24
Finished Jul 27 05:17:26 PM PDT 24
Peak memory 240320 kb
Host smart-53a6ba21-0328-4155-a38f-2beea15d4cf5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=413769365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.413769365
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2289812888
Short name T724
Test name
Test status
Simulation time 16865267 ps
CPU time 1.3 seconds
Started Jul 27 05:17:21 PM PDT 24
Finished Jul 27 05:17:23 PM PDT 24
Peak memory 236544 kb
Host smart-c0750491-53b2-40df-911a-0a43f7a5184c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2289812888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2289812888
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.3328757181
Short name T192
Test name
Test status
Simulation time 775368101 ps
CPU time 44.9 seconds
Started Jul 27 05:17:26 PM PDT 24
Finished Jul 27 05:18:11 PM PDT 24
Peak memory 245584 kb
Host smart-f1355107-02d7-410a-8c4c-c1341f042ce9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3328757181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.3328757181
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3068009411
Short name T153
Test name
Test status
Simulation time 98681758155 ps
CPU time 1058.83 seconds
Started Jul 27 05:17:27 PM PDT 24
Finished Jul 27 05:35:06 PM PDT 24
Peak memory 273500 kb
Host smart-2c044945-c7ef-4c8a-9cbc-d478bf004bd1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068009411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.3068009411
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3618708484
Short name T705
Test name
Test status
Simulation time 393075062 ps
CPU time 7.12 seconds
Started Jul 27 05:17:23 PM PDT 24
Finished Jul 27 05:17:30 PM PDT 24
Peak memory 251360 kb
Host smart-c068ffe9-4c03-4730-ad8e-e1f91e76bc3f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3618708484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3618708484
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.1647801694
Short name T788
Test name
Test status
Simulation time 60989443 ps
CPU time 2.79 seconds
Started Jul 27 05:17:23 PM PDT 24
Finished Jul 27 05:17:26 PM PDT 24
Peak memory 238512 kb
Host smart-0221924e-d3b2-4696-bda3-b872f1055336
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1647801694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.1647801694
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.4244471467
Short name T720
Test name
Test status
Simulation time 5796536521 ps
CPU time 328.06 seconds
Started Jul 27 05:16:58 PM PDT 24
Finished Jul 27 05:22:26 PM PDT 24
Peak memory 240692 kb
Host smart-b54548b0-9ea9-4da1-b41b-3075b0f572b8
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4244471467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.4244471467
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.633096274
Short name T823
Test name
Test status
Simulation time 22811153749 ps
CPU time 424.52 seconds
Started Jul 27 05:16:59 PM PDT 24
Finished Jul 27 05:24:04 PM PDT 24
Peak memory 240448 kb
Host smart-fbcda945-996c-4d07-a239-e702f72a5a4c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=633096274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.633096274
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3113622229
Short name T827
Test name
Test status
Simulation time 81385747 ps
CPU time 3.85 seconds
Started Jul 27 05:16:59 PM PDT 24
Finished Jul 27 05:17:03 PM PDT 24
Peak memory 248600 kb
Host smart-82c34925-b762-47c4-9fe8-99e60ec87d74
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3113622229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3113622229
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.4118026808
Short name T770
Test name
Test status
Simulation time 560219443 ps
CPU time 10.5 seconds
Started Jul 27 05:16:57 PM PDT 24
Finished Jul 27 05:17:08 PM PDT 24
Peak memory 240440 kb
Host smart-583fb931-68a7-4493-941e-99633b7c2be0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118026808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.4118026808
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2599350174
Short name T808
Test name
Test status
Simulation time 124880170 ps
CPU time 5.12 seconds
Started Jul 27 05:16:58 PM PDT 24
Finished Jul 27 05:17:03 PM PDT 24
Peak memory 240336 kb
Host smart-b607ef02-2fa1-4283-8081-c11073df44b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2599350174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2599350174
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.2097510797
Short name T810
Test name
Test status
Simulation time 15485728 ps
CPU time 1.49 seconds
Started Jul 27 05:16:57 PM PDT 24
Finished Jul 27 05:16:59 PM PDT 24
Peak memory 237392 kb
Host smart-c9132923-42d0-4d0a-901d-ed2c248fa773
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2097510797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.2097510797
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.2877596529
Short name T760
Test name
Test status
Simulation time 645965300 ps
CPU time 44.7 seconds
Started Jul 27 05:16:57 PM PDT 24
Finished Jul 27 05:17:42 PM PDT 24
Peak memory 245696 kb
Host smart-57b07ea4-40b3-493b-bef3-10338b9090d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2877596529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.2877596529
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3712863707
Short name T135
Test name
Test status
Simulation time 4775690301 ps
CPU time 637.83 seconds
Started Jul 27 05:16:58 PM PDT 24
Finished Jul 27 05:27:37 PM PDT 24
Peak memory 273432 kb
Host smart-20f25dfc-fc21-4839-a4c8-2849755b542e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3712863707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.3712863707
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2928154576
Short name T757
Test name
Test status
Simulation time 289688349 ps
CPU time 16.38 seconds
Started Jul 27 05:16:58 PM PDT 24
Finished Jul 27 05:17:14 PM PDT 24
Peak memory 248700 kb
Host smart-0d6083b3-3142-4d3a-8584-638f352d7849
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2928154576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2928154576
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.1763052515
Short name T824
Test name
Test status
Simulation time 8421649 ps
CPU time 1.48 seconds
Started Jul 27 05:17:23 PM PDT 24
Finished Jul 27 05:17:24 PM PDT 24
Peak memory 237496 kb
Host smart-89352537-275a-49d2-b259-e2c75d351157
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1763052515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.1763052515
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.444640645
Short name T792
Test name
Test status
Simulation time 21633540 ps
CPU time 1.36 seconds
Started Jul 27 05:17:23 PM PDT 24
Finished Jul 27 05:17:25 PM PDT 24
Peak memory 236592 kb
Host smart-c96f6c79-9e77-4e22-9fcb-5c3c6ddc026a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=444640645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.444640645
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.4105293321
Short name T344
Test name
Test status
Simulation time 6165276 ps
CPU time 1.46 seconds
Started Jul 27 05:17:25 PM PDT 24
Finished Jul 27 05:17:27 PM PDT 24
Peak memory 237372 kb
Host smart-e843319c-2546-4b58-a3ef-96ae35d056c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4105293321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.4105293321
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1702827190
Short name T798
Test name
Test status
Simulation time 12004991 ps
CPU time 1.49 seconds
Started Jul 27 05:17:22 PM PDT 24
Finished Jul 27 05:17:24 PM PDT 24
Peak memory 236612 kb
Host smart-4122b3b9-f7f0-4836-bdbc-1f09c3042afe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1702827190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1702827190
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.1327452126
Short name T746
Test name
Test status
Simulation time 6314390 ps
CPU time 1.46 seconds
Started Jul 27 05:17:23 PM PDT 24
Finished Jul 27 05:17:25 PM PDT 24
Peak memory 235440 kb
Host smart-d11291eb-8e7d-46d0-810d-0fd4a6e2195a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1327452126 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.1327452126
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.939322924
Short name T828
Test name
Test status
Simulation time 16025458 ps
CPU time 1.37 seconds
Started Jul 27 05:17:23 PM PDT 24
Finished Jul 27 05:17:25 PM PDT 24
Peak memory 237376 kb
Host smart-ed82d386-0762-43ec-a415-caa5fa013d5f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=939322924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.939322924
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.4222583036
Short name T341
Test name
Test status
Simulation time 8839410 ps
CPU time 1.52 seconds
Started Jul 27 05:17:22 PM PDT 24
Finished Jul 27 05:17:23 PM PDT 24
Peak memory 236628 kb
Host smart-5e57ec0e-748f-498d-a98e-60a13d59d508
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4222583036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.4222583036
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3610866418
Short name T718
Test name
Test status
Simulation time 7397700 ps
CPU time 1.4 seconds
Started Jul 27 05:17:27 PM PDT 24
Finished Jul 27 05:17:28 PM PDT 24
Peak memory 236512 kb
Host smart-381aefd9-1d79-4289-b9f9-93597138272c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3610866418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3610866418
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.777306009
Short name T806
Test name
Test status
Simulation time 8503159 ps
CPU time 1.53 seconds
Started Jul 27 05:17:22 PM PDT 24
Finished Jul 27 05:17:24 PM PDT 24
Peak memory 237416 kb
Host smart-83159bdc-54cb-4aeb-8089-1a293d30eebe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=777306009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.777306009
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.254050882
Short name T797
Test name
Test status
Simulation time 9521827 ps
CPU time 1.58 seconds
Started Jul 27 05:17:21 PM PDT 24
Finished Jul 27 05:17:23 PM PDT 24
Peak memory 236544 kb
Host smart-9b8321ff-9f70-4d17-a2a9-c00cac28fc92
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=254050882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.254050882
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1538800964
Short name T723
Test name
Test status
Simulation time 4710838812 ps
CPU time 163.08 seconds
Started Jul 27 05:16:59 PM PDT 24
Finished Jul 27 05:19:42 PM PDT 24
Peak memory 241136 kb
Host smart-11256b0f-acc3-492a-8e43-2d0cbd9f7197
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1538800964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1538800964
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3830587016
Short name T711
Test name
Test status
Simulation time 4976324824 ps
CPU time 264.96 seconds
Started Jul 27 05:16:57 PM PDT 24
Finished Jul 27 05:21:22 PM PDT 24
Peak memory 240528 kb
Host smart-0d88dc32-0c09-4bf8-808f-4719a4290ce3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3830587016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3830587016
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3696150354
Short name T162
Test name
Test status
Simulation time 108217267 ps
CPU time 8.46 seconds
Started Jul 27 05:16:57 PM PDT 24
Finished Jul 27 05:17:06 PM PDT 24
Peak memory 240388 kb
Host smart-382df8fe-4096-4d9d-8c0d-a0c561aae1c3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3696150354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3696150354
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1447909702
Short name T747
Test name
Test status
Simulation time 721546926 ps
CPU time 12.62 seconds
Started Jul 27 05:17:03 PM PDT 24
Finished Jul 27 05:17:16 PM PDT 24
Peak memory 252516 kb
Host smart-ae54e272-d6d8-4dec-bcd4-d662248c018a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447909702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1447909702
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1988256825
Short name T759
Test name
Test status
Simulation time 190754048 ps
CPU time 5.01 seconds
Started Jul 27 05:16:59 PM PDT 24
Finished Jul 27 05:17:04 PM PDT 24
Peak memory 240272 kb
Host smart-13a37311-e698-46dd-9913-0705df716db3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1988256825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1988256825
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2614715141
Short name T734
Test name
Test status
Simulation time 9642467 ps
CPU time 1.22 seconds
Started Jul 27 05:16:58 PM PDT 24
Finished Jul 27 05:17:00 PM PDT 24
Peak memory 236556 kb
Host smart-eeb28c47-ed63-48ee-b624-18adc3f3af56
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2614715141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2614715141
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.956805256
Short name T738
Test name
Test status
Simulation time 689559459 ps
CPU time 20.2 seconds
Started Jul 27 05:16:58 PM PDT 24
Finished Jul 27 05:17:18 PM PDT 24
Peak memory 240332 kb
Host smart-621c7465-b2fe-4558-ae05-bb831549eb41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=956805256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outs
tanding.956805256
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.923754674
Short name T152
Test name
Test status
Simulation time 4250395536 ps
CPU time 620.45 seconds
Started Jul 27 05:16:57 PM PDT 24
Finished Jul 27 05:27:18 PM PDT 24
Peak memory 273504 kb
Host smart-8bbc2191-3ab1-41df-b111-d37d53034b55
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923754674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.923754674
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1434547564
Short name T817
Test name
Test status
Simulation time 434804592 ps
CPU time 11.99 seconds
Started Jul 27 05:17:02 PM PDT 24
Finished Jul 27 05:17:14 PM PDT 24
Peak memory 248700 kb
Host smart-17593c18-9de3-4da8-963a-d80659863674
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1434547564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1434547564
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.487462564
Short name T733
Test name
Test status
Simulation time 18081636 ps
CPU time 1.27 seconds
Started Jul 27 05:17:27 PM PDT 24
Finished Jul 27 05:17:28 PM PDT 24
Peak memory 236388 kb
Host smart-8f5a1408-cfd2-4e43-8b23-159cf4ce0b35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=487462564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.487462564
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.197963366
Short name T795
Test name
Test status
Simulation time 18414409 ps
CPU time 1.33 seconds
Started Jul 27 05:17:23 PM PDT 24
Finished Jul 27 05:17:25 PM PDT 24
Peak memory 236484 kb
Host smart-1b111e4d-6d35-4bba-892c-d0f9d6b94b42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=197963366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.197963366
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1298749490
Short name T815
Test name
Test status
Simulation time 10256747 ps
CPU time 1.52 seconds
Started Jul 27 05:17:24 PM PDT 24
Finished Jul 27 05:17:26 PM PDT 24
Peak memory 236612 kb
Host smart-240d5762-133b-400f-9101-5893d19ac751
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1298749490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1298749490
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.1672830858
Short name T716
Test name
Test status
Simulation time 11807284 ps
CPU time 1.69 seconds
Started Jul 27 05:17:23 PM PDT 24
Finished Jul 27 05:17:25 PM PDT 24
Peak memory 236548 kb
Host smart-4f70c888-24a1-4a51-81bf-58800d41cdcf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1672830858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.1672830858
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3217017715
Short name T762
Test name
Test status
Simulation time 8392170 ps
CPU time 1.56 seconds
Started Jul 27 05:17:24 PM PDT 24
Finished Jul 27 05:17:26 PM PDT 24
Peak memory 237484 kb
Host smart-1091e21e-a1e0-41d4-8841-305b7a764042
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3217017715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3217017715
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.855889627
Short name T345
Test name
Test status
Simulation time 11600890 ps
CPU time 1.61 seconds
Started Jul 27 05:17:22 PM PDT 24
Finished Jul 27 05:17:24 PM PDT 24
Peak memory 237508 kb
Host smart-7a5b2be0-a7ff-4c6b-bb64-ba983d2ca3f6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=855889627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.855889627
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.2105187722
Short name T161
Test name
Test status
Simulation time 6640731 ps
CPU time 1.46 seconds
Started Jul 27 05:17:23 PM PDT 24
Finished Jul 27 05:17:24 PM PDT 24
Peak memory 237424 kb
Host smart-62805852-5086-449e-8aad-2be5ef139bdf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2105187722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.2105187722
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.4251019187
Short name T721
Test name
Test status
Simulation time 25522545 ps
CPU time 1.53 seconds
Started Jul 27 05:17:23 PM PDT 24
Finished Jul 27 05:17:25 PM PDT 24
Peak memory 237392 kb
Host smart-4c5922ce-6562-4149-a474-5b66c54f9f84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4251019187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.4251019187
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.447204903
Short name T740
Test name
Test status
Simulation time 9966471 ps
CPU time 1.41 seconds
Started Jul 27 05:17:24 PM PDT 24
Finished Jul 27 05:17:26 PM PDT 24
Peak memory 237480 kb
Host smart-b78996ec-b1c5-42ea-bbaf-041f3affafff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=447204903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.447204903
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.250885414
Short name T777
Test name
Test status
Simulation time 3416295076 ps
CPU time 231.19 seconds
Started Jul 27 05:17:00 PM PDT 24
Finished Jul 27 05:20:51 PM PDT 24
Peak memory 240460 kb
Host smart-dd88c05e-ccd9-43f2-a5bb-4e29fc2f714b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=250885414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.250885414
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.4192071803
Short name T821
Test name
Test status
Simulation time 38887168776 ps
CPU time 503.01 seconds
Started Jul 27 05:16:58 PM PDT 24
Finished Jul 27 05:25:22 PM PDT 24
Peak memory 237592 kb
Host smart-7afbcf73-44bf-4155-88de-d4312fdcf9ee
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4192071803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.4192071803
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3082652766
Short name T741
Test name
Test status
Simulation time 515801013 ps
CPU time 10.18 seconds
Started Jul 27 05:16:59 PM PDT 24
Finished Jul 27 05:17:09 PM PDT 24
Peak memory 248952 kb
Host smart-c9c00e40-3280-4f1b-8d6f-b17687a1c2da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3082652766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3082652766
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.458725877
Short name T737
Test name
Test status
Simulation time 104980510 ps
CPU time 9.16 seconds
Started Jul 27 05:16:58 PM PDT 24
Finished Jul 27 05:17:07 PM PDT 24
Peak memory 239816 kb
Host smart-dcafedc6-964f-462b-8b34-01f18661884b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458725877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.alert_handler_csr_mem_rw_with_rand_reset.458725877
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.804376361
Short name T190
Test name
Test status
Simulation time 496265144 ps
CPU time 10.19 seconds
Started Jul 27 05:16:58 PM PDT 24
Finished Jul 27 05:17:08 PM PDT 24
Peak memory 237476 kb
Host smart-1a809b09-9e81-4fdf-9c92-44d4dc30af5a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=804376361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.804376361
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.103998983
Short name T785
Test name
Test status
Simulation time 20457485 ps
CPU time 1.41 seconds
Started Jul 27 05:16:57 PM PDT 24
Finished Jul 27 05:16:59 PM PDT 24
Peak memory 235536 kb
Host smart-71d157d3-4e87-498a-b5e8-8c4a213f65d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=103998983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.103998983
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.57190359
Short name T719
Test name
Test status
Simulation time 571998960 ps
CPU time 22.52 seconds
Started Jul 27 05:17:04 PM PDT 24
Finished Jul 27 05:17:27 PM PDT 24
Peak memory 248616 kb
Host smart-cf9b4211-64fa-4e7e-ae0a-7063d6402a01
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=57190359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outst
anding.57190359
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.606045612
Short name T143
Test name
Test status
Simulation time 24706993993 ps
CPU time 131.35 seconds
Started Jul 27 05:16:59 PM PDT 24
Finished Jul 27 05:19:10 PM PDT 24
Peak memory 265388 kb
Host smart-e512d13e-9112-4ae3-b8c1-aca69ec666cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=606045612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_error
s.606045612
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1293179576
Short name T156
Test name
Test status
Simulation time 32176496073 ps
CPU time 1334.42 seconds
Started Jul 27 05:17:04 PM PDT 24
Finished Jul 27 05:39:19 PM PDT 24
Peak memory 265488 kb
Host smart-aac174a4-6b57-4ab5-8c3c-2c19974a3bc4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293179576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1293179576
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3352703743
Short name T749
Test name
Test status
Simulation time 812472180 ps
CPU time 14.24 seconds
Started Jul 27 05:17:03 PM PDT 24
Finished Jul 27 05:17:18 PM PDT 24
Peak memory 248648 kb
Host smart-65584a30-94df-4031-b327-717c01ad86ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3352703743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.3352703743
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2632681446
Short name T172
Test name
Test status
Simulation time 156498340 ps
CPU time 19.43 seconds
Started Jul 27 05:16:57 PM PDT 24
Finished Jul 27 05:17:16 PM PDT 24
Peak memory 240392 kb
Host smart-ad8dc6d2-dcca-42de-bef7-03ece8e4c20a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2632681446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2632681446
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.421852191
Short name T745
Test name
Test status
Simulation time 7325310 ps
CPU time 1.51 seconds
Started Jul 27 05:17:25 PM PDT 24
Finished Jul 27 05:17:27 PM PDT 24
Peak memory 236444 kb
Host smart-78b5b796-f37a-4260-8c7d-12d134143ed5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=421852191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.421852191
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1502054691
Short name T803
Test name
Test status
Simulation time 27382079 ps
CPU time 2.02 seconds
Started Jul 27 05:17:23 PM PDT 24
Finished Jul 27 05:17:25 PM PDT 24
Peak memory 235388 kb
Host smart-3c02f1d6-3693-492d-9b65-7108460c3430
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1502054691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1502054691
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1858595190
Short name T766
Test name
Test status
Simulation time 11428191 ps
CPU time 1.62 seconds
Started Jul 27 05:17:24 PM PDT 24
Finished Jul 27 05:17:26 PM PDT 24
Peak memory 236544 kb
Host smart-8a8abd99-06bd-4d59-8921-3699a7b51b78
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1858595190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1858595190
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3282521663
Short name T774
Test name
Test status
Simulation time 7637969 ps
CPU time 1.57 seconds
Started Jul 27 05:17:23 PM PDT 24
Finished Jul 27 05:17:25 PM PDT 24
Peak memory 237468 kb
Host smart-5c125b7f-646b-440c-b566-df7407b342cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3282521663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3282521663
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3192886176
Short name T742
Test name
Test status
Simulation time 22726691 ps
CPU time 1.34 seconds
Started Jul 27 05:17:25 PM PDT 24
Finished Jul 27 05:17:27 PM PDT 24
Peak memory 237376 kb
Host smart-fabc53d5-25ae-4514-b75c-f8f5e27a35ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3192886176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3192886176
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.4026170248
Short name T712
Test name
Test status
Simulation time 10357301 ps
CPU time 1.5 seconds
Started Jul 27 05:17:23 PM PDT 24
Finished Jul 27 05:17:25 PM PDT 24
Peak memory 237488 kb
Host smart-bae54636-839a-4771-8d51-20d0c1783aa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4026170248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.4026170248
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.4068729543
Short name T342
Test name
Test status
Simulation time 6964440 ps
CPU time 1.41 seconds
Started Jul 27 05:17:21 PM PDT 24
Finished Jul 27 05:17:23 PM PDT 24
Peak memory 236588 kb
Host smart-cdf3cf31-e61e-4548-b56f-cca3ec666de3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4068729543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.4068729543
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.1205093808
Short name T339
Test name
Test status
Simulation time 6586812 ps
CPU time 1.5 seconds
Started Jul 27 05:17:24 PM PDT 24
Finished Jul 27 05:17:25 PM PDT 24
Peak memory 237484 kb
Host smart-438dee5d-dff5-45e0-a186-88b93356a55c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1205093808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.1205093808
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.4264508939
Short name T710
Test name
Test status
Simulation time 12242755 ps
CPU time 1.66 seconds
Started Jul 27 05:17:26 PM PDT 24
Finished Jul 27 05:17:27 PM PDT 24
Peak memory 237508 kb
Host smart-2b944874-d5c2-440f-9d4b-435c494ddfc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4264508939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.4264508939
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2482653708
Short name T763
Test name
Test status
Simulation time 9889298 ps
CPU time 1.58 seconds
Started Jul 27 05:17:23 PM PDT 24
Finished Jul 27 05:17:25 PM PDT 24
Peak memory 237480 kb
Host smart-046388d8-d03b-4b9c-98a9-82e652476454
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2482653708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2482653708
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1540715168
Short name T178
Test name
Test status
Simulation time 293339212 ps
CPU time 12.24 seconds
Started Jul 27 05:17:00 PM PDT 24
Finished Jul 27 05:17:13 PM PDT 24
Peak memory 243648 kb
Host smart-567fa7c4-81cd-4f59-8d8a-f5b80f4055d9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540715168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.1540715168
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2794384679
Short name T818
Test name
Test status
Simulation time 559410308 ps
CPU time 4.96 seconds
Started Jul 27 05:16:56 PM PDT 24
Finished Jul 27 05:17:01 PM PDT 24
Peak memory 237460 kb
Host smart-faa60ee4-2e87-4d64-9c73-7ccc5e60f2ce
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2794384679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2794384679
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.1600993309
Short name T794
Test name
Test status
Simulation time 8831982 ps
CPU time 1.27 seconds
Started Jul 27 05:16:58 PM PDT 24
Finished Jul 27 05:16:59 PM PDT 24
Peak memory 236596 kb
Host smart-547481af-cf9f-4add-bdb9-2fac83eddc40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1600993309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.1600993309
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.4013694320
Short name T781
Test name
Test status
Simulation time 983016932 ps
CPU time 18.02 seconds
Started Jul 27 05:16:59 PM PDT 24
Finished Jul 27 05:17:17 PM PDT 24
Peak memory 244764 kb
Host smart-56ca4805-73b8-4e7e-86f6-cfed4a86620f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4013694320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.4013694320
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3810265121
Short name T145
Test name
Test status
Simulation time 1657513190 ps
CPU time 229.81 seconds
Started Jul 27 05:16:57 PM PDT 24
Finished Jul 27 05:20:47 PM PDT 24
Peak memory 265248 kb
Host smart-cfaaedfd-1957-44a7-8160-4586be3cf99d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3810265121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3810265121
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2344962898
Short name T753
Test name
Test status
Simulation time 312412347 ps
CPU time 6.46 seconds
Started Jul 27 05:16:58 PM PDT 24
Finished Jul 27 05:17:04 PM PDT 24
Peak memory 248736 kb
Host smart-4fe311f6-0877-495e-984c-7876a97b8413
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2344962898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2344962898
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1537875211
Short name T241
Test name
Test status
Simulation time 802178159 ps
CPU time 12.13 seconds
Started Jul 27 05:17:00 PM PDT 24
Finished Jul 27 05:17:12 PM PDT 24
Peak memory 250640 kb
Host smart-07e14e2b-48a0-4f31-82d6-44926fd61a97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537875211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1537875211
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2554226823
Short name T754
Test name
Test status
Simulation time 52179268 ps
CPU time 4.67 seconds
Started Jul 27 05:17:04 PM PDT 24
Finished Jul 27 05:17:08 PM PDT 24
Peak memory 237464 kb
Host smart-88df02de-baac-49e7-a865-abefef83e924
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2554226823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2554226823
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.562760694
Short name T769
Test name
Test status
Simulation time 12803563 ps
CPU time 1.34 seconds
Started Jul 27 05:16:58 PM PDT 24
Finished Jul 27 05:17:00 PM PDT 24
Peak memory 236576 kb
Host smart-5961bddf-7131-46bf-bbf4-bc6b4d7866f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=562760694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.562760694
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.953634005
Short name T189
Test name
Test status
Simulation time 2553599637 ps
CPU time 41.01 seconds
Started Jul 27 05:17:02 PM PDT 24
Finished Jul 27 05:17:43 PM PDT 24
Peak memory 245120 kb
Host smart-f084a792-6795-4af8-bd35-2e1fae8d012a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=953634005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_outs
tanding.953634005
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3591280131
Short name T726
Test name
Test status
Simulation time 578318809 ps
CPU time 14.47 seconds
Started Jul 27 05:17:02 PM PDT 24
Finished Jul 27 05:17:16 PM PDT 24
Peak memory 248676 kb
Host smart-375b8afd-f3c2-4b24-8192-b7bb350357c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3591280131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3591280131
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2930088953
Short name T758
Test name
Test status
Simulation time 294739899 ps
CPU time 9.99 seconds
Started Jul 27 05:16:59 PM PDT 24
Finished Jul 27 05:17:09 PM PDT 24
Peak memory 239752 kb
Host smart-76125836-903c-4e77-9c8a-ba01d5c4aab8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930088953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.2930088953
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.2894242998
Short name T193
Test name
Test status
Simulation time 329976582 ps
CPU time 4.93 seconds
Started Jul 27 05:17:00 PM PDT 24
Finished Jul 27 05:17:05 PM PDT 24
Peak memory 236460 kb
Host smart-b989adfb-2ec6-4aba-854f-f9172ae0f6f4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2894242998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.2894242998
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.4074159580
Short name T706
Test name
Test status
Simulation time 19517346 ps
CPU time 1.33 seconds
Started Jul 27 05:17:01 PM PDT 24
Finished Jul 27 05:17:02 PM PDT 24
Peak memory 236604 kb
Host smart-5dce6edc-2156-4001-844d-826385f76fca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4074159580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.4074159580
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3172781901
Short name T775
Test name
Test status
Simulation time 1104440947 ps
CPU time 22.66 seconds
Started Jul 27 05:17:00 PM PDT 24
Finished Jul 27 05:17:23 PM PDT 24
Peak memory 244760 kb
Host smart-39d2bae3-ba64-4e8e-bd97-12dc2142ce7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3172781901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3172781901
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.4184422901
Short name T136
Test name
Test status
Simulation time 1683940721 ps
CPU time 189.39 seconds
Started Jul 27 05:17:04 PM PDT 24
Finished Jul 27 05:20:14 PM PDT 24
Peak memory 265300 kb
Host smart-bc52ba82-ce61-40a1-9450-c9e2c037c3e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4184422901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.4184422901
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2183293232
Short name T137
Test name
Test status
Simulation time 8962558875 ps
CPU time 644.37 seconds
Started Jul 27 05:17:00 PM PDT 24
Finished Jul 27 05:27:45 PM PDT 24
Peak memory 265444 kb
Host smart-7c860846-4edc-41f3-9f5f-cd99463d7560
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183293232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.2183293232
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.4209081820
Short name T765
Test name
Test status
Simulation time 206322084 ps
CPU time 7.26 seconds
Started Jul 27 05:17:02 PM PDT 24
Finished Jul 27 05:17:09 PM PDT 24
Peak memory 248164 kb
Host smart-e655f75b-c713-4592-af1f-9f1d434834c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4209081820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.4209081820
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.101561608
Short name T197
Test name
Test status
Simulation time 505008145 ps
CPU time 9.63 seconds
Started Jul 27 05:17:04 PM PDT 24
Finished Jul 27 05:17:14 PM PDT 24
Peak memory 255620 kb
Host smart-8aa0f7d0-9eab-4347-b7d4-1838dc0d53aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101561608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.alert_handler_csr_mem_rw_with_rand_reset.101561608
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1782523459
Short name T722
Test name
Test status
Simulation time 93564925 ps
CPU time 8.33 seconds
Started Jul 27 05:17:04 PM PDT 24
Finished Jul 27 05:17:12 PM PDT 24
Peak memory 237352 kb
Host smart-d6233b9a-9f3e-4407-827b-44f2b85c8060
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1782523459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1782523459
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.1719657516
Short name T772
Test name
Test status
Simulation time 11323967 ps
CPU time 1.39 seconds
Started Jul 27 05:17:04 PM PDT 24
Finished Jul 27 05:17:06 PM PDT 24
Peak memory 236604 kb
Host smart-06cc420f-54e7-4774-8565-5341086480c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1719657516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.1719657516
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1854693581
Short name T729
Test name
Test status
Simulation time 97509084 ps
CPU time 12 seconds
Started Jul 27 05:17:03 PM PDT 24
Finished Jul 27 05:17:15 PM PDT 24
Peak memory 244776 kb
Host smart-117d2a61-9a1c-49eb-b328-f30a47d1be3f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1854693581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1854693581
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2375090508
Short name T142
Test name
Test status
Simulation time 16616078175 ps
CPU time 1118.3 seconds
Started Jul 27 05:17:00 PM PDT 24
Finished Jul 27 05:35:39 PM PDT 24
Peak memory 265424 kb
Host smart-763a5682-9f0a-4143-add7-fa63aa56db75
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375090508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2375090508
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3153329590
Short name T793
Test name
Test status
Simulation time 274223547 ps
CPU time 10.73 seconds
Started Jul 27 05:17:00 PM PDT 24
Finished Jul 27 05:17:11 PM PDT 24
Peak memory 253812 kb
Host smart-e9c21982-31e6-4813-8469-9eb1bd83ee8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3153329590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3153329590
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2259460521
Short name T789
Test name
Test status
Simulation time 128003295 ps
CPU time 10.36 seconds
Started Jul 27 05:17:12 PM PDT 24
Finished Jul 27 05:17:22 PM PDT 24
Peak memory 243528 kb
Host smart-083b12a1-7a3f-41ed-b098-ac5531ae33a0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259460521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2259460521
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.3303935114
Short name T736
Test name
Test status
Simulation time 257193123 ps
CPU time 9.83 seconds
Started Jul 27 05:17:09 PM PDT 24
Finished Jul 27 05:17:18 PM PDT 24
Peak memory 240404 kb
Host smart-b929f702-70fc-4c71-ad02-d54096902298
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3303935114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.3303935114
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2947102841
Short name T783
Test name
Test status
Simulation time 7198704 ps
CPU time 1.43 seconds
Started Jul 27 05:17:10 PM PDT 24
Finished Jul 27 05:17:11 PM PDT 24
Peak memory 235496 kb
Host smart-32b39846-2899-4f77-b9d9-538034d3ed38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2947102841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2947102841
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3243896073
Short name T743
Test name
Test status
Simulation time 615942248 ps
CPU time 13.2 seconds
Started Jul 27 05:17:13 PM PDT 24
Finished Jul 27 05:17:26 PM PDT 24
Peak memory 240352 kb
Host smart-84f816d3-8192-41eb-aba4-b98483a75213
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3243896073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.3243896073
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.660425465
Short name T129
Test name
Test status
Simulation time 12867704888 ps
CPU time 100.65 seconds
Started Jul 27 05:17:09 PM PDT 24
Finished Jul 27 05:18:50 PM PDT 24
Peak memory 265576 kb
Host smart-d7692c05-cb77-42ac-bbd9-0094db70c1f7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=660425465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.660425465
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.373564323
Short name T773
Test name
Test status
Simulation time 265463163 ps
CPU time 10.19 seconds
Started Jul 27 05:17:11 PM PDT 24
Finished Jul 27 05:17:21 PM PDT 24
Peak memory 248828 kb
Host smart-210ef72d-334c-452e-b418-da2fca527fc4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=373564323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.373564323
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3649414516
Short name T25
Test name
Test status
Simulation time 37165862218 ps
CPU time 2290.13 seconds
Started Jul 27 05:18:18 PM PDT 24
Finished Jul 27 05:56:29 PM PDT 24
Peak memory 289656 kb
Host smart-47e7428b-282c-420e-94c3-993871202479
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649414516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3649414516
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.3414002724
Short name T499
Test name
Test status
Simulation time 599621393 ps
CPU time 16.43 seconds
Started Jul 27 05:18:17 PM PDT 24
Finished Jul 27 05:18:34 PM PDT 24
Peak memory 248736 kb
Host smart-a2557c0f-e0d7-409f-8b95-1ed80dae7380
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3414002724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3414002724
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.4174447495
Short name T680
Test name
Test status
Simulation time 732917065 ps
CPU time 61.87 seconds
Started Jul 27 05:18:03 PM PDT 24
Finished Jul 27 05:19:05 PM PDT 24
Peak memory 256920 kb
Host smart-34a6b578-1995-441f-b754-79b2aef9a536
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41744
47495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.4174447495
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.49743427
Short name T639
Test name
Test status
Simulation time 2950654835 ps
CPU time 49.67 seconds
Started Jul 27 05:18:05 PM PDT 24
Finished Jul 27 05:18:55 PM PDT 24
Peak memory 256680 kb
Host smart-166493e1-1fa7-42b1-8a79-2b90323f5eb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49743
427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.49743427
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.4122418907
Short name T636
Test name
Test status
Simulation time 9319158965 ps
CPU time 698.49 seconds
Started Jul 27 05:18:16 PM PDT 24
Finished Jul 27 05:29:54 PM PDT 24
Peak memory 271540 kb
Host smart-264e18ed-694c-430b-99e9-b4a67dc551f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122418907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.4122418907
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3349077337
Short name T496
Test name
Test status
Simulation time 134574167240 ps
CPU time 2093.25 seconds
Started Jul 27 05:18:18 PM PDT 24
Finished Jul 27 05:53:12 PM PDT 24
Peak memory 285896 kb
Host smart-fe514f5e-04ae-43a2-89c8-af3d07ff71e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349077337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3349077337
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.394303207
Short name T616
Test name
Test status
Simulation time 14633020514 ps
CPU time 334.93 seconds
Started Jul 27 05:18:19 PM PDT 24
Finished Jul 27 05:23:55 PM PDT 24
Peak memory 248848 kb
Host smart-a197a808-728b-4b21-80cb-bad4483397cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394303207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.394303207
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.2607832436
Short name T600
Test name
Test status
Simulation time 1410053812 ps
CPU time 30.76 seconds
Started Jul 27 05:18:04 PM PDT 24
Finished Jul 27 05:18:35 PM PDT 24
Peak memory 255988 kb
Host smart-f777e6c0-9896-4772-b5a8-35d713c63de7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26078
32436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.2607832436
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3436972533
Short name T449
Test name
Test status
Simulation time 5470124110 ps
CPU time 56.2 seconds
Started Jul 27 05:18:03 PM PDT 24
Finished Jul 27 05:18:59 PM PDT 24
Peak memory 256956 kb
Host smart-7ae8a980-ad78-416a-8bb5-6d83c0b5974c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34369
72533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3436972533
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.206090613
Short name T110
Test name
Test status
Simulation time 107833665 ps
CPU time 4.17 seconds
Started Jul 27 05:18:14 PM PDT 24
Finished Jul 27 05:18:18 PM PDT 24
Peak memory 240068 kb
Host smart-689353d5-a419-4b78-9dfb-f6137893930b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20609
0613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.206090613
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.2683293443
Short name T562
Test name
Test status
Simulation time 330938240 ps
CPU time 30.89 seconds
Started Jul 27 05:18:04 PM PDT 24
Finished Jul 27 05:18:35 PM PDT 24
Peak memory 256376 kb
Host smart-dc650eae-acf7-4b89-adf5-5d907fb76a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26832
93443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.2683293443
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.356515051
Short name T701
Test name
Test status
Simulation time 12065060380 ps
CPU time 1046.69 seconds
Started Jul 27 05:18:14 PM PDT 24
Finished Jul 27 05:35:41 PM PDT 24
Peak memory 289476 kb
Host smart-fc33fc84-7dde-4c5b-bcef-84dcb925352c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356515051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.356515051
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.2752699717
Short name T479
Test name
Test status
Simulation time 341283361 ps
CPU time 18.07 seconds
Started Jul 27 05:18:16 PM PDT 24
Finished Jul 27 05:18:35 PM PDT 24
Peak memory 248676 kb
Host smart-5c89ff59-0173-4ef3-80d3-e8de67f10c26
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2752699717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.2752699717
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.2044265115
Short name T684
Test name
Test status
Simulation time 8301548091 ps
CPU time 245.24 seconds
Started Jul 27 05:18:16 PM PDT 24
Finished Jul 27 05:22:22 PM PDT 24
Peak memory 256908 kb
Host smart-475d8a84-a9db-4f41-82fd-11d7dee8a185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20442
65115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.2044265115
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.623477796
Short name T359
Test name
Test status
Simulation time 508303967 ps
CPU time 16.45 seconds
Started Jul 27 05:18:17 PM PDT 24
Finished Jul 27 05:18:33 PM PDT 24
Peak memory 256604 kb
Host smart-5d3cb36b-df03-4e35-9374-4a6cbbc1fcad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62347
7796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.623477796
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.1176598172
Short name T266
Test name
Test status
Simulation time 46022689209 ps
CPU time 1261.88 seconds
Started Jul 27 05:18:16 PM PDT 24
Finished Jul 27 05:39:18 PM PDT 24
Peak memory 265204 kb
Host smart-65e428c4-8daf-4b1a-a70e-4b815881681b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176598172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1176598172
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.430688422
Short name T502
Test name
Test status
Simulation time 14689157327 ps
CPU time 297.08 seconds
Started Jul 27 05:18:15 PM PDT 24
Finished Jul 27 05:23:12 PM PDT 24
Peak memory 256928 kb
Host smart-57b0a56d-3f1a-4a3f-9115-f4f1998623a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430688422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.430688422
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.2427817257
Short name T694
Test name
Test status
Simulation time 1369233883 ps
CPU time 38.41 seconds
Started Jul 27 05:18:20 PM PDT 24
Finished Jul 27 05:18:59 PM PDT 24
Peak memory 256296 kb
Host smart-fbbffd2b-f834-4fb6-91c1-ffb4428a465f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24278
17257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2427817257
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.438903617
Short name T116
Test name
Test status
Simulation time 595226858 ps
CPU time 27.33 seconds
Started Jul 27 05:18:17 PM PDT 24
Finished Jul 27 05:18:44 PM PDT 24
Peak memory 247996 kb
Host smart-bbcd12bd-5d2d-4a6b-9a1e-9fc1a677cffb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43890
3617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.438903617
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.2191035836
Short name T10
Test name
Test status
Simulation time 703821976 ps
CPU time 20.66 seconds
Started Jul 27 05:18:15 PM PDT 24
Finished Jul 27 05:18:36 PM PDT 24
Peak memory 270824 kb
Host smart-81776232-f860-4fa2-a8ab-4999f0a7f03c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2191035836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.2191035836
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.4274427409
Short name T354
Test name
Test status
Simulation time 484358151 ps
CPU time 12.49 seconds
Started Jul 27 05:18:17 PM PDT 24
Finished Jul 27 05:18:29 PM PDT 24
Peak memory 248260 kb
Host smart-fb68d27c-4097-4604-bde1-c0003c37317e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42744
27409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.4274427409
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3717880834
Short name T415
Test name
Test status
Simulation time 15230192903 ps
CPU time 72.52 seconds
Started Jul 27 05:18:13 PM PDT 24
Finished Jul 27 05:19:25 PM PDT 24
Peak memory 248700 kb
Host smart-16a7c169-867a-4aa6-8225-c939478a8258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37178
80834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3717880834
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.1575153870
Short name T592
Test name
Test status
Simulation time 1477279978 ps
CPU time 123.02 seconds
Started Jul 27 05:18:18 PM PDT 24
Finished Jul 27 05:20:22 PM PDT 24
Peak memory 251048 kb
Host smart-81a5dd09-7aab-4a8c-a2b0-6661fbf48cab
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575153870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.1575153870
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.244626356
Short name T198
Test name
Test status
Simulation time 51462923 ps
CPU time 4.19 seconds
Started Jul 27 05:18:32 PM PDT 24
Finished Jul 27 05:18:37 PM PDT 24
Peak memory 248992 kb
Host smart-3e569a87-f1ec-4d79-b16e-d29fd583f14a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=244626356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.244626356
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.174615307
Short name T550
Test name
Test status
Simulation time 40510451825 ps
CPU time 2562.66 seconds
Started Jul 27 05:18:29 PM PDT 24
Finished Jul 27 06:01:12 PM PDT 24
Peak memory 289656 kb
Host smart-d10466db-4b5e-4b6f-a2fc-19d75c55e8ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174615307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.174615307
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1075559492
Short name T657
Test name
Test status
Simulation time 949285724 ps
CPU time 13.16 seconds
Started Jul 27 05:18:30 PM PDT 24
Finished Jul 27 05:18:44 PM PDT 24
Peak memory 248740 kb
Host smart-eebdba2e-f714-433d-adf8-c8eee5fbd4db
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1075559492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1075559492
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.3388118544
Short name T516
Test name
Test status
Simulation time 4287089516 ps
CPU time 248.21 seconds
Started Jul 27 05:18:28 PM PDT 24
Finished Jul 27 05:22:36 PM PDT 24
Peak memory 252032 kb
Host smart-10be6925-8c06-434e-8115-983d8cc94fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33881
18544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3388118544
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.826122761
Short name T599
Test name
Test status
Simulation time 568566041 ps
CPU time 33.82 seconds
Started Jul 27 05:18:32 PM PDT 24
Finished Jul 27 05:19:06 PM PDT 24
Peak memory 256400 kb
Host smart-7f1049e7-d979-4c35-b4f7-9ef525e0a9ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82612
2761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.826122761
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.2569187514
Short name T221
Test name
Test status
Simulation time 609877780 ps
CPU time 33.08 seconds
Started Jul 27 05:18:29 PM PDT 24
Finished Jul 27 05:19:02 PM PDT 24
Peak memory 248720 kb
Host smart-5cd6160d-6f25-4ac7-a096-b13dc53c76a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25691
87514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.2569187514
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.1218347279
Short name T364
Test name
Test status
Simulation time 255007648 ps
CPU time 14.79 seconds
Started Jul 27 05:18:37 PM PDT 24
Finished Jul 27 05:18:52 PM PDT 24
Peak memory 254384 kb
Host smart-37ab187a-727e-4007-be89-7d9ff052a659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12183
47279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.1218347279
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2527466085
Short name T458
Test name
Test status
Simulation time 173562711 ps
CPU time 12.19 seconds
Started Jul 27 05:18:35 PM PDT 24
Finished Jul 27 05:18:48 PM PDT 24
Peak memory 254800 kb
Host smart-40f4e47a-446b-41f4-a5ef-cf835f64140d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25274
66085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2527466085
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.1094719255
Short name T475
Test name
Test status
Simulation time 1592602388 ps
CPU time 19.06 seconds
Started Jul 27 05:18:29 PM PDT 24
Finished Jul 27 05:18:48 PM PDT 24
Peak memory 256908 kb
Host smart-971bb283-db20-4d98-beed-af47d9bbde70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10947
19255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.1094719255
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.2960306554
Short name T603
Test name
Test status
Simulation time 6621450239 ps
CPU time 175.8 seconds
Started Jul 27 05:18:30 PM PDT 24
Finished Jul 27 05:21:26 PM PDT 24
Peak memory 256588 kb
Host smart-85bd5ca7-a7e7-4622-8fac-c52d6c997ef0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960306554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.2960306554
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.1360890377
Short name T23
Test name
Test status
Simulation time 23712095665 ps
CPU time 1609.18 seconds
Started Jul 27 05:18:37 PM PDT 24
Finished Jul 27 05:45:27 PM PDT 24
Peak memory 280568 kb
Host smart-67e7dc1e-44c4-443b-9723-7096a725a72a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360890377 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.1360890377
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3475051856
Short name T208
Test name
Test status
Simulation time 109553409 ps
CPU time 2.79 seconds
Started Jul 27 05:18:28 PM PDT 24
Finished Jul 27 05:18:31 PM PDT 24
Peak memory 248924 kb
Host smart-5fc8691a-bbbf-4a2d-b87f-6c31fd177f58
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3475051856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3475051856
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2348794978
Short name T111
Test name
Test status
Simulation time 33315220583 ps
CPU time 1837.99 seconds
Started Jul 27 05:18:35 PM PDT 24
Finished Jul 27 05:49:14 PM PDT 24
Peak memory 273284 kb
Host smart-41b761ce-27d3-4dd3-a8df-0a7635aa2ef2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348794978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2348794978
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.323680509
Short name T651
Test name
Test status
Simulation time 773512291 ps
CPU time 9.97 seconds
Started Jul 27 05:18:30 PM PDT 24
Finished Jul 27 05:18:40 PM PDT 24
Peak memory 248788 kb
Host smart-916b946f-f4e5-4a6c-913d-518c237228d1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=323680509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.323680509
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.119295143
Short name T387
Test name
Test status
Simulation time 287037955 ps
CPU time 9.36 seconds
Started Jul 27 05:18:28 PM PDT 24
Finished Jul 27 05:18:38 PM PDT 24
Peak memory 256108 kb
Host smart-ffea9fe0-ef75-47d5-9e67-0c62d09dafd0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11929
5143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.119295143
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.1121799373
Short name T549
Test name
Test status
Simulation time 774691215 ps
CPU time 35.71 seconds
Started Jul 27 05:18:35 PM PDT 24
Finished Jul 27 05:19:12 PM PDT 24
Peak memory 248420 kb
Host smart-915906a3-680b-4fbf-b15a-0814778121a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11217
99373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.1121799373
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1172432772
Short name T18
Test name
Test status
Simulation time 11149495975 ps
CPU time 1117.8 seconds
Started Jul 27 05:18:37 PM PDT 24
Finished Jul 27 05:37:15 PM PDT 24
Peak memory 284400 kb
Host smart-f383e436-735f-4cea-b2f6-37320622f478
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172432772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1172432772
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2431722171
Short name T17
Test name
Test status
Simulation time 427823431110 ps
CPU time 1799.38 seconds
Started Jul 27 05:18:31 PM PDT 24
Finished Jul 27 05:48:31 PM PDT 24
Peak memory 289264 kb
Host smart-f156dda0-3f64-44a9-8875-0a8aaa2a5c4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431722171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2431722171
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.3851091217
Short name T655
Test name
Test status
Simulation time 23873851133 ps
CPU time 247.89 seconds
Started Jul 27 05:18:35 PM PDT 24
Finished Jul 27 05:22:43 PM PDT 24
Peak memory 248724 kb
Host smart-f5b71d47-ed9b-44cb-9cd8-21ed68c30d0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851091217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.3851091217
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.6939410
Short name T577
Test name
Test status
Simulation time 396337148 ps
CPU time 25.3 seconds
Started Jul 27 05:18:27 PM PDT 24
Finished Jul 27 05:18:52 PM PDT 24
Peak memory 256368 kb
Host smart-ab1220b8-6a33-4ee7-bb4d-deb8765890be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69394
10 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.6939410
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3463016117
Short name T540
Test name
Test status
Simulation time 1376931936 ps
CPU time 39.47 seconds
Started Jul 27 05:18:35 PM PDT 24
Finished Jul 27 05:19:15 PM PDT 24
Peak memory 247832 kb
Host smart-50b68689-e47b-47e7-bc02-13158a6bb0cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34630
16117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3463016117
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3686418696
Short name T654
Test name
Test status
Simulation time 156439920 ps
CPU time 10.73 seconds
Started Jul 27 05:18:32 PM PDT 24
Finished Jul 27 05:18:43 PM PDT 24
Peak memory 248092 kb
Host smart-bb40c662-f21b-4d8b-87d1-59c3a08fe790
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36864
18696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3686418696
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.3520613202
Short name T559
Test name
Test status
Simulation time 310296032 ps
CPU time 12.97 seconds
Started Jul 27 05:18:35 PM PDT 24
Finished Jul 27 05:18:49 PM PDT 24
Peak memory 254832 kb
Host smart-30bca581-c25f-4d88-8a96-4de5ac3745bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35206
13202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3520613202
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.3131391580
Short name T95
Test name
Test status
Simulation time 119794803824 ps
CPU time 1009.84 seconds
Started Jul 27 05:18:27 PM PDT 24
Finished Jul 27 05:35:17 PM PDT 24
Peak memory 284560 kb
Host smart-aea862f8-2f60-4759-b024-72c4fc43857b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3131391580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.3131391580
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2621830081
Short name T205
Test name
Test status
Simulation time 159318775 ps
CPU time 3.94 seconds
Started Jul 27 05:18:47 PM PDT 24
Finished Jul 27 05:18:51 PM PDT 24
Peak memory 249112 kb
Host smart-6397a5c6-3e6d-4c06-a328-71fa46fe1af3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2621830081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2621830081
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.1484808817
Short name T451
Test name
Test status
Simulation time 88808099205 ps
CPU time 1263.04 seconds
Started Jul 27 05:18:32 PM PDT 24
Finished Jul 27 05:39:35 PM PDT 24
Peak memory 272780 kb
Host smart-c4aea17f-8086-4dd8-957d-b54230bb9a44
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484808817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1484808817
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2046570417
Short name T383
Test name
Test status
Simulation time 154513129 ps
CPU time 9.35 seconds
Started Jul 27 05:18:28 PM PDT 24
Finished Jul 27 05:18:38 PM PDT 24
Peak memory 248764 kb
Host smart-42359e7a-ab32-428d-9a67-f68532dc6e41
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2046570417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2046570417
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.1558603139
Short name T351
Test name
Test status
Simulation time 665304218 ps
CPU time 43.56 seconds
Started Jul 27 05:18:31 PM PDT 24
Finished Jul 27 05:19:15 PM PDT 24
Peak memory 256864 kb
Host smart-5a1d631c-a6fd-41ad-b09d-5784b63e5b20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15586
03139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.1558603139
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.1883933117
Short name T76
Test name
Test status
Simulation time 94287308 ps
CPU time 7.43 seconds
Started Jul 27 05:18:37 PM PDT 24
Finished Jul 27 05:18:44 PM PDT 24
Peak memory 254652 kb
Host smart-e381b513-ca58-44d5-b236-9907229b8430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18839
33117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1883933117
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.1591685677
Short name T331
Test name
Test status
Simulation time 46471175620 ps
CPU time 937.12 seconds
Started Jul 27 05:18:32 PM PDT 24
Finished Jul 27 05:34:09 PM PDT 24
Peak memory 282440 kb
Host smart-e3685317-94ac-4137-a55e-08dce185c198
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591685677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1591685677
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.779389478
Short name T561
Test name
Test status
Simulation time 28196059074 ps
CPU time 949.37 seconds
Started Jul 27 05:18:33 PM PDT 24
Finished Jul 27 05:34:23 PM PDT 24
Peak memory 273300 kb
Host smart-c90c746c-8609-4f4e-a22d-a75d85715e4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779389478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.779389478
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.594319832
Short name T579
Test name
Test status
Simulation time 14813239588 ps
CPU time 600.76 seconds
Started Jul 27 05:18:31 PM PDT 24
Finished Jul 27 05:28:32 PM PDT 24
Peak memory 248664 kb
Host smart-a8941bb2-1a73-446e-8ab9-af249a36e056
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594319832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.594319832
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3374877660
Short name T404
Test name
Test status
Simulation time 116054813 ps
CPU time 5.4 seconds
Started Jul 27 05:18:38 PM PDT 24
Finished Jul 27 05:18:43 PM PDT 24
Peak memory 255024 kb
Host smart-3ffcba8d-8d20-4b67-ae9b-7eb6e1478ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33748
77660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3374877660
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.2352217632
Short name T665
Test name
Test status
Simulation time 996372087 ps
CPU time 60.92 seconds
Started Jul 27 05:18:30 PM PDT 24
Finished Jul 27 05:19:31 PM PDT 24
Peak memory 248820 kb
Host smart-c0b093d8-730b-44d5-b500-b65120854d8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23522
17632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2352217632
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1621208398
Short name T531
Test name
Test status
Simulation time 244033554 ps
CPU time 25.68 seconds
Started Jul 27 05:18:29 PM PDT 24
Finished Jul 27 05:18:55 PM PDT 24
Peak memory 256524 kb
Host smart-71cd1939-d2cf-4f3c-b6ec-ed5f669c84f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16212
08398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1621208398
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.1773455549
Short name T369
Test name
Test status
Simulation time 914540965 ps
CPU time 38.04 seconds
Started Jul 27 05:18:26 PM PDT 24
Finished Jul 27 05:19:04 PM PDT 24
Peak memory 256972 kb
Host smart-e50c3973-47d4-403f-94d4-9b464efca1ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17734
55549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.1773455549
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.3361962090
Short name T51
Test name
Test status
Simulation time 430165937 ps
CPU time 15.42 seconds
Started Jul 27 05:18:45 PM PDT 24
Finished Jul 27 05:19:01 PM PDT 24
Peak memory 248760 kb
Host smart-5e8e0c14-835b-43ad-a841-5573cd4b95aa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361962090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.3361962090
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2916869030
Short name T669
Test name
Test status
Simulation time 35279360554 ps
CPU time 1546.37 seconds
Started Jul 27 05:18:38 PM PDT 24
Finished Jul 27 05:44:24 PM PDT 24
Peak memory 289172 kb
Host smart-6127239d-6281-44e2-9d26-257a2b97972a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916869030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2916869030
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.451724664
Short name T405
Test name
Test status
Simulation time 528128017 ps
CPU time 26.93 seconds
Started Jul 27 05:18:40 PM PDT 24
Finished Jul 27 05:19:07 PM PDT 24
Peak memory 248812 kb
Host smart-567c1da7-128f-4d3b-aac9-5050402412c8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=451724664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.451724664
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3067215755
Short name T468
Test name
Test status
Simulation time 2133067999 ps
CPU time 61.33 seconds
Started Jul 27 05:18:46 PM PDT 24
Finished Jul 27 05:19:47 PM PDT 24
Peak memory 256024 kb
Host smart-4ea227ae-7ec6-4d70-8e1f-d2706610d755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30672
15755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3067215755
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.4076783630
Short name T649
Test name
Test status
Simulation time 468272590 ps
CPU time 25.62 seconds
Started Jul 27 05:18:47 PM PDT 24
Finished Jul 27 05:19:12 PM PDT 24
Peak memory 255324 kb
Host smart-cfbfffe6-5360-4257-be29-23f6a491d88d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40767
83630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.4076783630
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2820694551
Short name T467
Test name
Test status
Simulation time 31946234990 ps
CPU time 1750.92 seconds
Started Jul 27 05:18:43 PM PDT 24
Finished Jul 27 05:47:54 PM PDT 24
Peak memory 273132 kb
Host smart-f9b0e237-3848-4e4a-b48e-9cc3b1490fd1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820694551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2820694551
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1000869765
Short name T529
Test name
Test status
Simulation time 6520584874 ps
CPU time 136.72 seconds
Started Jul 27 05:18:46 PM PDT 24
Finished Jul 27 05:21:03 PM PDT 24
Peak memory 247644 kb
Host smart-000eafd1-599d-4d4e-a742-457a7c8798fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000869765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1000869765
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.811139915
Short name T230
Test name
Test status
Simulation time 127499303 ps
CPU time 9.32 seconds
Started Jul 27 05:18:41 PM PDT 24
Finished Jul 27 05:18:50 PM PDT 24
Peak memory 248744 kb
Host smart-07beba7c-ebda-45cd-b25c-c5a5aadee38e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81113
9915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.811139915
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.1292979423
Short name T493
Test name
Test status
Simulation time 751415879 ps
CPU time 32.17 seconds
Started Jul 27 05:18:35 PM PDT 24
Finished Jul 27 05:19:07 PM PDT 24
Peak memory 257032 kb
Host smart-4b15ca08-eec0-4428-912c-3f8c5aacb991
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12929
79423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1292979423
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.140715533
Short name T432
Test name
Test status
Simulation time 82043990 ps
CPU time 10.89 seconds
Started Jul 27 05:18:42 PM PDT 24
Finished Jul 27 05:18:53 PM PDT 24
Peak memory 248664 kb
Host smart-91491c07-8f10-4d4f-bd9d-f15ad35018f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14071
5533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.140715533
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3587718510
Short name T220
Test name
Test status
Simulation time 231308260 ps
CPU time 7.12 seconds
Started Jul 27 05:18:46 PM PDT 24
Finished Jul 27 05:18:54 PM PDT 24
Peak memory 248584 kb
Host smart-777b18e9-777d-480c-8626-a17686b48deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35877
18510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3587718510
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.1257271375
Short name T456
Test name
Test status
Simulation time 60631478256 ps
CPU time 3082.8 seconds
Started Jul 27 05:18:46 PM PDT 24
Finished Jul 27 06:10:09 PM PDT 24
Peak memory 322008 kb
Host smart-b6ce374d-424f-4099-9e10-132f5a50e109
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257271375 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.1257271375
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.2743217938
Short name T108
Test name
Test status
Simulation time 91496213384 ps
CPU time 2646.24 seconds
Started Jul 27 05:18:45 PM PDT 24
Finished Jul 27 06:02:52 PM PDT 24
Peak memory 289188 kb
Host smart-114e3701-5be3-4b6e-a962-e97cd0a148c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743217938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.2743217938
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1219565475
Short name T420
Test name
Test status
Simulation time 887094669 ps
CPU time 40.1 seconds
Started Jul 27 05:18:43 PM PDT 24
Finished Jul 27 05:19:23 PM PDT 24
Peak memory 248716 kb
Host smart-d2976398-82f9-4b1d-aae4-de7aa746e140
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1219565475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1219565475
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.80785111
Short name T249
Test name
Test status
Simulation time 21795030243 ps
CPU time 297.01 seconds
Started Jul 27 05:18:44 PM PDT 24
Finished Jul 27 05:23:42 PM PDT 24
Peak memory 256600 kb
Host smart-dc25fd4c-c037-44fb-b20d-6e05f30cb547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80785
111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.80785111
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.2336737664
Short name T597
Test name
Test status
Simulation time 1149346399 ps
CPU time 18.95 seconds
Started Jul 27 05:18:39 PM PDT 24
Finished Jul 27 05:18:58 PM PDT 24
Peak memory 248324 kb
Host smart-5a6a43b1-9dfa-4ba2-9d42-5c5d4747f4d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23367
37664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2336737664
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.556001885
Short name T333
Test name
Test status
Simulation time 55233081743 ps
CPU time 1319.21 seconds
Started Jul 27 05:18:36 PM PDT 24
Finished Jul 27 05:40:36 PM PDT 24
Peak memory 288364 kb
Host smart-773f103d-e49d-4b0b-9967-bf9e1914d728
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556001885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.556001885
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1203950743
Short name T539
Test name
Test status
Simulation time 26829654516 ps
CPU time 1115.68 seconds
Started Jul 27 05:18:37 PM PDT 24
Finished Jul 27 05:37:13 PM PDT 24
Peak memory 288976 kb
Host smart-dfb5f134-a73c-4920-aedc-186875dec06e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203950743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1203950743
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.1712700340
Short name T702
Test name
Test status
Simulation time 185040415 ps
CPU time 19.6 seconds
Started Jul 27 05:18:37 PM PDT 24
Finished Jul 27 05:18:56 PM PDT 24
Peak memory 248780 kb
Host smart-841fae75-bb23-49b2-b349-288ce494f221
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17127
00340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.1712700340
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2678745532
Short name T567
Test name
Test status
Simulation time 287214613 ps
CPU time 16.53 seconds
Started Jul 27 05:18:43 PM PDT 24
Finished Jul 27 05:18:59 PM PDT 24
Peak memory 256988 kb
Host smart-cf070a70-f22d-45bc-ab70-72c7de71a98f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26787
45532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2678745532
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.251781189
Short name T670
Test name
Test status
Simulation time 621819548 ps
CPU time 35.82 seconds
Started Jul 27 05:18:44 PM PDT 24
Finished Jul 27 05:19:20 PM PDT 24
Peak memory 256940 kb
Host smart-8e09fe48-5334-4fbc-bec7-3aaa0084fc01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25178
1189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.251781189
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3314229619
Short name T555
Test name
Test status
Simulation time 678884027 ps
CPU time 51.76 seconds
Started Jul 27 05:18:39 PM PDT 24
Finished Jul 27 05:19:31 PM PDT 24
Peak memory 256960 kb
Host smart-8dfc6dd5-9bb6-47a7-91e2-581407cc0838
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33142
29619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3314229619
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3966083629
Short name T216
Test name
Test status
Simulation time 47464801 ps
CPU time 4.58 seconds
Started Jul 27 05:18:50 PM PDT 24
Finished Jul 27 05:18:55 PM PDT 24
Peak memory 248996 kb
Host smart-ed9fc774-369b-43e3-92f4-d0536b677837
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3966083629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3966083629
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.2794925909
Short name T32
Test name
Test status
Simulation time 16699487541 ps
CPU time 1110.64 seconds
Started Jul 27 05:18:44 PM PDT 24
Finished Jul 27 05:37:15 PM PDT 24
Peak memory 281176 kb
Host smart-9ac6eb5d-70a8-46da-b11a-ccc1e5a35771
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794925909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2794925909
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.6467813
Short name T462
Test name
Test status
Simulation time 391803809 ps
CPU time 18.61 seconds
Started Jul 27 05:18:47 PM PDT 24
Finished Jul 27 05:19:06 PM PDT 24
Peak memory 248648 kb
Host smart-2270fdd8-6a3d-4e56-bafe-43a671d9dbcc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=6467813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.6467813
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1957626404
Short name T393
Test name
Test status
Simulation time 5688138219 ps
CPU time 298.98 seconds
Started Jul 27 05:18:43 PM PDT 24
Finished Jul 27 05:23:42 PM PDT 24
Peak memory 256188 kb
Host smart-14bc5a45-c69e-4131-982a-f03d2211ccee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19576
26404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1957626404
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.3397775279
Short name T278
Test name
Test status
Simulation time 2367136126 ps
CPU time 69.86 seconds
Started Jul 27 05:18:44 PM PDT 24
Finished Jul 27 05:19:54 PM PDT 24
Peak memory 248896 kb
Host smart-aca0abd6-f1d0-4513-8b58-331df81eda54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33977
75279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.3397775279
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2533840606
Short name T418
Test name
Test status
Simulation time 34622704194 ps
CPU time 913.15 seconds
Started Jul 27 05:18:37 PM PDT 24
Finished Jul 27 05:33:51 PM PDT 24
Peak memory 273356 kb
Host smart-a5c06973-1aa8-42c5-af1c-d11e37b978d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533840606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2533840606
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.1012578826
Short name T219
Test name
Test status
Simulation time 24359693644 ps
CPU time 241.27 seconds
Started Jul 27 05:18:32 PM PDT 24
Finished Jul 27 05:22:33 PM PDT 24
Peak memory 255444 kb
Host smart-30900122-4640-4787-ba81-452b353e2ca8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012578826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1012578826
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.716313961
Short name T668
Test name
Test status
Simulation time 570712481 ps
CPU time 22.61 seconds
Started Jul 27 05:18:38 PM PDT 24
Finished Jul 27 05:19:01 PM PDT 24
Peak memory 248732 kb
Host smart-87b13573-d079-4378-b9bf-60c22915befd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71631
3961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.716313961
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1386231926
Short name T106
Test name
Test status
Simulation time 1066933993 ps
CPU time 70.73 seconds
Started Jul 27 05:18:44 PM PDT 24
Finished Jul 27 05:19:54 PM PDT 24
Peak memory 256852 kb
Host smart-d0446b00-0c60-48b9-857b-92839cbd268e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13862
31926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1386231926
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2501986262
Short name T647
Test name
Test status
Simulation time 1358637499 ps
CPU time 86.3 seconds
Started Jul 27 05:18:47 PM PDT 24
Finished Jul 27 05:20:13 PM PDT 24
Peak memory 249764 kb
Host smart-efc5321f-9378-4387-9de9-a98f08e662e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25019
86262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2501986262
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.4075904107
Short name T521
Test name
Test status
Simulation time 2208262833 ps
CPU time 32.92 seconds
Started Jul 27 05:18:47 PM PDT 24
Finished Jul 27 05:19:20 PM PDT 24
Peak memory 256576 kb
Host smart-edc8e0f4-f76d-4b9a-afe6-5f731c0212f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40759
04107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.4075904107
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.4238004133
Short name T88
Test name
Test status
Simulation time 218713632389 ps
CPU time 2795.2 seconds
Started Jul 27 05:18:46 PM PDT 24
Finished Jul 27 06:05:21 PM PDT 24
Peak memory 289084 kb
Host smart-67557517-d4ce-4fff-accf-200486c3342b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238004133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.4238004133
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3808667498
Short name T215
Test name
Test status
Simulation time 107267609 ps
CPU time 3.11 seconds
Started Jul 27 05:18:49 PM PDT 24
Finished Jul 27 05:18:53 PM PDT 24
Peak memory 249112 kb
Host smart-d251a556-e37d-4e4f-b84c-6805ac2fe16f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3808667498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3808667498
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.667825228
Short name T31
Test name
Test status
Simulation time 50503413444 ps
CPU time 1334.97 seconds
Started Jul 27 05:18:50 PM PDT 24
Finished Jul 27 05:41:05 PM PDT 24
Peak memory 272776 kb
Host smart-33d20aba-8303-4368-a543-690b81e6301a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667825228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.667825228
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1662434599
Short name T15
Test name
Test status
Simulation time 187007112 ps
CPU time 10.99 seconds
Started Jul 27 05:18:47 PM PDT 24
Finished Jul 27 05:18:58 PM PDT 24
Peak memory 248780 kb
Host smart-11952706-55a0-47ae-a779-9fea6b34ae9d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1662434599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1662434599
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.1846097396
Short name T633
Test name
Test status
Simulation time 6857725516 ps
CPU time 138.19 seconds
Started Jul 27 05:18:48 PM PDT 24
Finished Jul 27 05:21:07 PM PDT 24
Peak memory 252124 kb
Host smart-80ef178f-c8db-468e-8443-e5e9f2cbc825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18460
97396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1846097396
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.3164464513
Short name T563
Test name
Test status
Simulation time 361834381 ps
CPU time 24.25 seconds
Started Jul 27 05:18:47 PM PDT 24
Finished Jul 27 05:19:12 PM PDT 24
Peak memory 256920 kb
Host smart-b8815d23-772a-43cc-bf1e-09322e8e6fd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31644
64513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3164464513
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.1990739259
Short name T326
Test name
Test status
Simulation time 19536848508 ps
CPU time 1579.8 seconds
Started Jul 27 05:18:48 PM PDT 24
Finished Jul 27 05:45:08 PM PDT 24
Peak memory 288924 kb
Host smart-cdabdc31-b356-4f34-9078-383f901b2e95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990739259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.1990739259
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2578561231
Short name T394
Test name
Test status
Simulation time 28642201613 ps
CPU time 1849.06 seconds
Started Jul 27 05:18:51 PM PDT 24
Finished Jul 27 05:49:40 PM PDT 24
Peak memory 282544 kb
Host smart-dea70457-6a77-4b4b-ae9a-eb3923a4e5d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578561231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2578561231
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.4080474328
Short name T313
Test name
Test status
Simulation time 6011066953 ps
CPU time 243.65 seconds
Started Jul 27 05:18:51 PM PDT 24
Finished Jul 27 05:22:54 PM PDT 24
Peak memory 248660 kb
Host smart-caacff81-18e3-4da5-a528-3400dfba75f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080474328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.4080474328
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2021318163
Short name T528
Test name
Test status
Simulation time 4799105286 ps
CPU time 69.35 seconds
Started Jul 27 05:18:48 PM PDT 24
Finished Jul 27 05:19:57 PM PDT 24
Peak memory 248840 kb
Host smart-406ab6c6-ad42-442b-9e4a-90cfed9f9aec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20213
18163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2021318163
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3092234738
Short name T477
Test name
Test status
Simulation time 2656941368 ps
CPU time 41.52 seconds
Started Jul 27 05:18:49 PM PDT 24
Finished Jul 27 05:19:30 PM PDT 24
Peak memory 248792 kb
Host smart-c871ad52-81d9-4d58-ae69-0d4e68a00699
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30922
34738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3092234738
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.827185023
Short name T43
Test name
Test status
Simulation time 561246372 ps
CPU time 20.09 seconds
Started Jul 27 05:18:48 PM PDT 24
Finished Jul 27 05:19:09 PM PDT 24
Peak memory 256456 kb
Host smart-048b0c0c-fd8c-47c4-9671-35cda0b84ae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82718
5023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.827185023
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.615567564
Short name T569
Test name
Test status
Simulation time 482573175 ps
CPU time 36.05 seconds
Started Jul 27 05:18:48 PM PDT 24
Finished Jul 27 05:19:24 PM PDT 24
Peak memory 256924 kb
Host smart-1456fa55-42b3-4e46-b8ce-5d4592c0ccd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61556
7564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.615567564
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.4270695993
Short name T524
Test name
Test status
Simulation time 3506791212 ps
CPU time 43.03 seconds
Started Jul 27 05:18:48 PM PDT 24
Finished Jul 27 05:19:31 PM PDT 24
Peak memory 257088 kb
Host smart-65e9e61c-86cf-48cb-b76b-4a959731f6b0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270695993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.4270695993
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.25408358
Short name T457
Test name
Test status
Simulation time 12114866666 ps
CPU time 1021.84 seconds
Started Jul 27 05:18:47 PM PDT 24
Finished Jul 27 05:35:49 PM PDT 24
Peak memory 273508 kb
Host smart-da1129cf-15ae-4cfd-8771-d1f0fbd9de72
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25408358 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.25408358
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.566483315
Short name T211
Test name
Test status
Simulation time 19644921 ps
CPU time 2.61 seconds
Started Jul 27 05:18:47 PM PDT 24
Finished Jul 27 05:18:49 PM PDT 24
Peak memory 249096 kb
Host smart-91462700-cf5e-4ca0-b51d-79180ad6a766
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=566483315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.566483315
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.622674192
Short name T54
Test name
Test status
Simulation time 131550006295 ps
CPU time 2020.34 seconds
Started Jul 27 05:18:47 PM PDT 24
Finished Jul 27 05:52:28 PM PDT 24
Peak memory 286332 kb
Host smart-48a2af4a-3c17-4c8d-b8e6-47b00283ffc5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622674192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.622674192
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1546781969
Short name T626
Test name
Test status
Simulation time 3674367571 ps
CPU time 35.76 seconds
Started Jul 27 05:18:46 PM PDT 24
Finished Jul 27 05:19:22 PM PDT 24
Peak memory 248684 kb
Host smart-ca5cf7c5-759f-41a1-ac01-68ba07a1c98e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1546781969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1546781969
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.2032939130
Short name T46
Test name
Test status
Simulation time 1459354546 ps
CPU time 88.81 seconds
Started Jul 27 05:18:48 PM PDT 24
Finished Jul 27 05:20:17 PM PDT 24
Peak memory 256420 kb
Host smart-51f1e8d5-de43-40d1-b649-b287078fae19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20329
39130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.2032939130
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.4241194845
Short name T532
Test name
Test status
Simulation time 216427037 ps
CPU time 17.38 seconds
Started Jul 27 05:18:49 PM PDT 24
Finished Jul 27 05:19:06 PM PDT 24
Peak memory 256668 kb
Host smart-53331069-6502-45f2-8d2e-9d00a142faa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42411
94845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.4241194845
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.246644866
Short name T332
Test name
Test status
Simulation time 33373996450 ps
CPU time 1390.85 seconds
Started Jul 27 05:18:49 PM PDT 24
Finished Jul 27 05:42:00 PM PDT 24
Peak memory 289632 kb
Host smart-a568687e-1725-4406-aa32-8b157d4e9f9e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246644866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.246644866
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.3008267173
Short name T37
Test name
Test status
Simulation time 26688548877 ps
CPU time 1682.95 seconds
Started Jul 27 05:18:51 PM PDT 24
Finished Jul 27 05:46:54 PM PDT 24
Peak memory 271280 kb
Host smart-b5285d3a-eb7b-4c52-a965-410b90f32028
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008267173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.3008267173
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.1604546501
Short name T566
Test name
Test status
Simulation time 193776636 ps
CPU time 9.83 seconds
Started Jul 27 05:18:50 PM PDT 24
Finished Jul 27 05:19:00 PM PDT 24
Peak memory 248800 kb
Host smart-f35e7164-4cdd-4181-980c-edc84c83cddc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16045
46501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.1604546501
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3568825767
Short name T700
Test name
Test status
Simulation time 410701094 ps
CPU time 26.68 seconds
Started Jul 27 05:18:46 PM PDT 24
Finished Jul 27 05:19:13 PM PDT 24
Peak memory 248812 kb
Host smart-fd08139d-9f97-4723-ac05-cfac72d96c84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35688
25767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3568825767
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.231108619
Short name T483
Test name
Test status
Simulation time 335552347 ps
CPU time 23.16 seconds
Started Jul 27 05:18:50 PM PDT 24
Finished Jul 27 05:19:14 PM PDT 24
Peak memory 256944 kb
Host smart-b33c52f1-7bb5-4a26-a465-546d6a6dcc8f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23110
8619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.231108619
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.510370514
Short name T446
Test name
Test status
Simulation time 159977107 ps
CPU time 11.54 seconds
Started Jul 27 05:18:47 PM PDT 24
Finished Jul 27 05:18:58 PM PDT 24
Peak memory 254808 kb
Host smart-a63fa59b-e0c4-4b96-81b0-719abd5fd3f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51037
0514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.510370514
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.2871534410
Short name T24
Test name
Test status
Simulation time 83683363342 ps
CPU time 1862.19 seconds
Started Jul 27 05:18:47 PM PDT 24
Finished Jul 27 05:49:49 PM PDT 24
Peak memory 289780 kb
Host smart-f0ab25a4-082c-4c99-a587-fca8bd30e11c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871534410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2871534410
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1965237303
Short name T199
Test name
Test status
Simulation time 30834561 ps
CPU time 2.95 seconds
Started Jul 27 05:18:53 PM PDT 24
Finished Jul 27 05:18:56 PM PDT 24
Peak memory 249092 kb
Host smart-40f07d51-770a-4651-b45e-51f366211edc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1965237303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1965237303
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.2706188846
Short name T543
Test name
Test status
Simulation time 31716988491 ps
CPU time 795.58 seconds
Started Jul 27 05:18:47 PM PDT 24
Finished Jul 27 05:32:02 PM PDT 24
Peak memory 266276 kb
Host smart-2c0c70c1-2e11-4eac-a26a-3b486876392f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706188846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.2706188846
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.4245940677
Short name T422
Test name
Test status
Simulation time 2002608928 ps
CPU time 22.62 seconds
Started Jul 27 05:18:50 PM PDT 24
Finished Jul 27 05:19:13 PM PDT 24
Peak memory 248792 kb
Host smart-9fa6feb4-d504-4099-a8a8-e9f118742767
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4245940677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.4245940677
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.426566968
Short name T373
Test name
Test status
Simulation time 1670522825 ps
CPU time 136.71 seconds
Started Jul 27 05:18:49 PM PDT 24
Finished Jul 27 05:21:06 PM PDT 24
Peak memory 256448 kb
Host smart-ca242eb6-625c-45e2-8498-9ce08408e393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42656
6968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.426566968
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.3108343230
Short name T12
Test name
Test status
Simulation time 12269137655 ps
CPU time 58.5 seconds
Started Jul 27 05:18:50 PM PDT 24
Finished Jul 27 05:19:48 PM PDT 24
Peak memory 257336 kb
Host smart-41a614e5-3501-4a53-a5d8-64d0d7ba54e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31083
43230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.3108343230
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.2959476751
Short name T217
Test name
Test status
Simulation time 59012004546 ps
CPU time 1672.43 seconds
Started Jul 27 05:18:51 PM PDT 24
Finished Jul 27 05:46:43 PM PDT 24
Peak memory 289832 kb
Host smart-8536f846-2828-4bf4-8fb8-ac9660e7e791
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959476751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.2959476751
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.1886578828
Short name T535
Test name
Test status
Simulation time 14842441036 ps
CPU time 311.76 seconds
Started Jul 27 05:18:49 PM PDT 24
Finished Jul 27 05:24:01 PM PDT 24
Peak memory 248792 kb
Host smart-bd2d2575-08af-45b2-9a2d-97cc28661360
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886578828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1886578828
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3339772980
Short name T82
Test name
Test status
Simulation time 623525446 ps
CPU time 19.71 seconds
Started Jul 27 05:18:51 PM PDT 24
Finished Jul 27 05:19:11 PM PDT 24
Peak memory 248684 kb
Host smart-d6a5e339-a299-4111-80d2-e2384ed6b87e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33397
72980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3339772980
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1086199229
Short name T271
Test name
Test status
Simulation time 4145075776 ps
CPU time 67.26 seconds
Started Jul 27 05:18:50 PM PDT 24
Finished Jul 27 05:19:57 PM PDT 24
Peak memory 248476 kb
Host smart-8a1bd05c-740c-432b-87c6-ffdd77a1c7e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10861
99229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1086199229
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.520366192
Short name T470
Test name
Test status
Simulation time 5628672569 ps
CPU time 37.44 seconds
Started Jul 27 05:18:48 PM PDT 24
Finished Jul 27 05:19:25 PM PDT 24
Peak memory 249216 kb
Host smart-85506d8a-e5a8-4a28-829d-1a4be93334c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52036
6192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.520366192
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.32672047
Short name T445
Test name
Test status
Simulation time 1138756084 ps
CPU time 61.3 seconds
Started Jul 27 05:18:47 PM PDT 24
Finished Jul 27 05:19:49 PM PDT 24
Peak memory 256428 kb
Host smart-c108dd45-cd69-48f1-9057-fb48f67b2abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32672
047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.32672047
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.2304950247
Short name T286
Test name
Test status
Simulation time 128814560020 ps
CPU time 2129.76 seconds
Started Jul 27 05:19:00 PM PDT 24
Finished Jul 27 05:54:30 PM PDT 24
Peak memory 289960 kb
Host smart-096ffde1-2711-4751-9173-af43d3f9ccb5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2304950247 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.2304950247
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1412385847
Short name T47
Test name
Test status
Simulation time 45945930 ps
CPU time 4.01 seconds
Started Jul 27 05:19:18 PM PDT 24
Finished Jul 27 05:19:22 PM PDT 24
Peak memory 249112 kb
Host smart-f2ccca45-c934-4a20-b1cb-f59604995b5e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1412385847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1412385847
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2754463292
Short name T251
Test name
Test status
Simulation time 36840419749 ps
CPU time 1595.85 seconds
Started Jul 27 05:18:59 PM PDT 24
Finished Jul 27 05:45:35 PM PDT 24
Peak memory 289252 kb
Host smart-80c9b4fe-d881-4123-bbb5-6fc742cc9388
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754463292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2754463292
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.1566055712
Short name T648
Test name
Test status
Simulation time 1022186419 ps
CPU time 8.34 seconds
Started Jul 27 05:18:59 PM PDT 24
Finished Jul 27 05:19:07 PM PDT 24
Peak memory 248736 kb
Host smart-91a682ae-817d-4525-86e6-589f41b98271
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1566055712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.1566055712
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1357451051
Short name T401
Test name
Test status
Simulation time 13399662181 ps
CPU time 181.87 seconds
Started Jul 27 05:18:58 PM PDT 24
Finished Jul 27 05:22:00 PM PDT 24
Peak memory 256972 kb
Host smart-d1892f51-ba02-47b9-a00c-84b5b66d142d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13574
51051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1357451051
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1622170519
Short name T234
Test name
Test status
Simulation time 312515721 ps
CPU time 19.68 seconds
Started Jul 27 05:18:58 PM PDT 24
Finished Jul 27 05:19:18 PM PDT 24
Peak memory 256952 kb
Host smart-58e14ae1-38b6-4b3c-9800-a1420260c1f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16221
70519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1622170519
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.4269217762
Short name T627
Test name
Test status
Simulation time 118789659535 ps
CPU time 1914.92 seconds
Started Jul 27 05:19:03 PM PDT 24
Finished Jul 27 05:50:59 PM PDT 24
Peak memory 282220 kb
Host smart-d80607a5-4273-4377-998a-0d8a7856abe9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269217762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.4269217762
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.3812456056
Short name T490
Test name
Test status
Simulation time 151846592454 ps
CPU time 2060.35 seconds
Started Jul 27 05:18:55 PM PDT 24
Finished Jul 27 05:53:16 PM PDT 24
Peak memory 282628 kb
Host smart-c7a71993-9353-436e-bdbf-ec0e8b7818ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812456056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3812456056
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3442040858
Short name T667
Test name
Test status
Simulation time 29577160714 ps
CPU time 608.15 seconds
Started Jul 27 05:18:59 PM PDT 24
Finished Jul 27 05:29:08 PM PDT 24
Peak memory 248768 kb
Host smart-1392617a-b744-45ca-8b70-0868d6761c1e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442040858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3442040858
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.1246521367
Short name T38
Test name
Test status
Simulation time 638003730 ps
CPU time 21.51 seconds
Started Jul 27 05:18:58 PM PDT 24
Finished Jul 27 05:19:20 PM PDT 24
Peak memory 248632 kb
Host smart-469e143c-d4fc-485c-99e9-873f395227fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12465
21367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1246521367
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.856142672
Short name T375
Test name
Test status
Simulation time 243500451 ps
CPU time 14.42 seconds
Started Jul 27 05:19:00 PM PDT 24
Finished Jul 27 05:19:14 PM PDT 24
Peak memory 248780 kb
Host smart-7c4ba04f-61dd-4cda-a06d-5ad0b1f02a73
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85614
2672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.856142672
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2355613253
Short name T289
Test name
Test status
Simulation time 192689635 ps
CPU time 16.13 seconds
Started Jul 27 05:19:03 PM PDT 24
Finished Jul 27 05:19:20 PM PDT 24
Peak memory 248264 kb
Host smart-0c131807-e204-4af6-a28c-07514b2a7c06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23556
13253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2355613253
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3992244670
Short name T183
Test name
Test status
Simulation time 131304567 ps
CPU time 12 seconds
Started Jul 27 05:19:00 PM PDT 24
Finished Jul 27 05:19:13 PM PDT 24
Peak memory 254748 kb
Host smart-f4ee24ce-3941-4ca6-b493-ebd33c6312ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39922
44670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3992244670
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.1992115038
Short name T203
Test name
Test status
Simulation time 193638045 ps
CPU time 3.58 seconds
Started Jul 27 05:18:16 PM PDT 24
Finished Jul 27 05:18:20 PM PDT 24
Peak memory 249132 kb
Host smart-3559c0aa-2c0d-4a2f-8f88-8bfe70d15187
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1992115038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.1992115038
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.966945080
Short name T672
Test name
Test status
Simulation time 48359556547 ps
CPU time 1522.39 seconds
Started Jul 27 05:18:18 PM PDT 24
Finished Jul 27 05:43:41 PM PDT 24
Peak memory 273128 kb
Host smart-1e9ffd28-b26c-463b-a637-be5745ff4709
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=966945080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.966945080
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1700232315
Short name T486
Test name
Test status
Simulation time 349481613 ps
CPU time 6.56 seconds
Started Jul 27 05:18:18 PM PDT 24
Finished Jul 27 05:18:25 PM PDT 24
Peak memory 248796 kb
Host smart-cb58e97a-8afe-44c0-97a3-c5fa2165a146
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1700232315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1700232315
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1297855169
Short name T695
Test name
Test status
Simulation time 7336448009 ps
CPU time 179.57 seconds
Started Jul 27 05:18:13 PM PDT 24
Finished Jul 27 05:21:12 PM PDT 24
Peak memory 257060 kb
Host smart-e20f72fb-a8fa-4b90-afab-7c4559dbb914
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12978
55169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1297855169
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.4204137310
Short name T525
Test name
Test status
Simulation time 341651997 ps
CPU time 20.87 seconds
Started Jul 27 05:18:18 PM PDT 24
Finished Jul 27 05:18:39 PM PDT 24
Peak memory 248736 kb
Host smart-e11baf57-507f-41e0-a32e-ab5d3ad1c185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42041
37310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.4204137310
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3365473930
Short name T260
Test name
Test status
Simulation time 10971726666 ps
CPU time 935.6 seconds
Started Jul 27 05:18:19 PM PDT 24
Finished Jul 27 05:33:55 PM PDT 24
Peak memory 272752 kb
Host smart-8531397a-fd09-4910-bf86-67e9f3283ad8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365473930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3365473930
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.979171797
Short name T551
Test name
Test status
Simulation time 42131117329 ps
CPU time 1983.82 seconds
Started Jul 27 05:18:13 PM PDT 24
Finished Jul 27 05:51:17 PM PDT 24
Peak memory 284216 kb
Host smart-d45ab931-e840-4c7d-9c30-505c7727c649
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979171797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.979171797
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.118521994
Short name T417
Test name
Test status
Simulation time 2125279394 ps
CPU time 67 seconds
Started Jul 27 05:18:20 PM PDT 24
Finished Jul 27 05:19:27 PM PDT 24
Peak memory 256004 kb
Host smart-5052d195-0704-40d6-9429-566cd2104aee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11852
1994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.118521994
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2225575846
Short name T187
Test name
Test status
Simulation time 1120916365 ps
CPU time 32.46 seconds
Started Jul 27 05:18:19 PM PDT 24
Finished Jul 27 05:18:52 PM PDT 24
Peak memory 256976 kb
Host smart-86386469-2f20-4485-83d1-7c9d62548fb3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22255
75846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2225575846
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.1789105312
Short name T33
Test name
Test status
Simulation time 714187656 ps
CPU time 20.8 seconds
Started Jul 27 05:18:20 PM PDT 24
Finished Jul 27 05:18:40 PM PDT 24
Peak memory 270512 kb
Host smart-65e4e487-ce7a-41bd-a870-7ea6c69da0c8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1789105312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.1789105312
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.3050624794
Short name T580
Test name
Test status
Simulation time 331505819 ps
CPU time 22.29 seconds
Started Jul 27 05:18:17 PM PDT 24
Finished Jul 27 05:18:40 PM PDT 24
Peak memory 248752 kb
Host smart-45d9b4b5-68de-459c-a3b5-e58a7963991b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30506
24794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.3050624794
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.2754510185
Short name T391
Test name
Test status
Simulation time 358908608 ps
CPU time 10.86 seconds
Started Jul 27 05:18:11 PM PDT 24
Finished Jul 27 05:18:23 PM PDT 24
Peak memory 248776 kb
Host smart-366592f0-af81-4fbb-b4f2-3f09175c7cac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27545
10185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2754510185
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.3224435762
Short name T646
Test name
Test status
Simulation time 87074909041 ps
CPU time 2583.48 seconds
Started Jul 27 05:18:13 PM PDT 24
Finished Jul 27 06:01:17 PM PDT 24
Peak memory 281528 kb
Host smart-904d737c-b71a-4fe2-ac25-3d5bf56e9fac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224435762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.3224435762
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.723337517
Short name T410
Test name
Test status
Simulation time 9119053642 ps
CPU time 778.03 seconds
Started Jul 27 05:19:08 PM PDT 24
Finished Jul 27 05:32:06 PM PDT 24
Peak memory 273372 kb
Host smart-58467167-d086-49cc-8699-4583781d0369
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723337517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.723337517
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.26002802
Short name T411
Test name
Test status
Simulation time 6976514109 ps
CPU time 233.43 seconds
Started Jul 27 05:19:17 PM PDT 24
Finished Jul 27 05:23:11 PM PDT 24
Peak memory 256584 kb
Host smart-d645bca2-9aaa-49ef-a8a6-dc237ef5d0dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26002
802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.26002802
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3162140768
Short name T277
Test name
Test status
Simulation time 4255586313 ps
CPU time 71.61 seconds
Started Jul 27 05:19:08 PM PDT 24
Finished Jul 27 05:20:20 PM PDT 24
Peak memory 248724 kb
Host smart-fc2b27eb-1ed6-41f7-addc-1a32fbfba569
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31621
40768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3162140768
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2978263068
Short name T474
Test name
Test status
Simulation time 8308294867 ps
CPU time 717.37 seconds
Started Jul 27 05:19:07 PM PDT 24
Finished Jul 27 05:31:04 PM PDT 24
Peak memory 273388 kb
Host smart-4583e37d-6667-4a96-a64e-dac2f97a9136
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978263068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2978263068
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3579486556
Short name T575
Test name
Test status
Simulation time 28816765587 ps
CPU time 1705.48 seconds
Started Jul 27 05:19:16 PM PDT 24
Finished Jul 27 05:47:42 PM PDT 24
Peak memory 273228 kb
Host smart-7f1ce91d-506c-4bd5-a197-bf4290e290f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579486556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3579486556
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2098376154
Short name T635
Test name
Test status
Simulation time 44733517501 ps
CPU time 401.88 seconds
Started Jul 27 05:19:08 PM PDT 24
Finished Jul 27 05:25:50 PM PDT 24
Peak memory 248712 kb
Host smart-64e86d5e-5bad-4f69-803f-20be9d9e3081
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098376154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2098376154
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1017808892
Short name T504
Test name
Test status
Simulation time 678862141 ps
CPU time 39.08 seconds
Started Jul 27 05:19:07 PM PDT 24
Finished Jul 27 05:19:46 PM PDT 24
Peak memory 248668 kb
Host smart-413dbfc8-94c9-449a-892b-00b1d25037da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10178
08892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1017808892
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.871528633
Short name T429
Test name
Test status
Simulation time 1258813501 ps
CPU time 21.67 seconds
Started Jul 27 05:19:08 PM PDT 24
Finished Jul 27 05:19:30 PM PDT 24
Peak memory 256916 kb
Host smart-9aa7ea8c-619a-4f57-9cfd-d3d0637fc913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87152
8633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.871528633
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1842248404
Short name T264
Test name
Test status
Simulation time 1748659808 ps
CPU time 26.17 seconds
Started Jul 27 05:19:09 PM PDT 24
Finished Jul 27 05:19:35 PM PDT 24
Peak memory 255864 kb
Host smart-bef2edb7-75c2-47fc-8bae-faec035261bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18422
48404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1842248404
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1860690904
Short name T463
Test name
Test status
Simulation time 783428458 ps
CPU time 10.56 seconds
Started Jul 27 05:19:09 PM PDT 24
Finished Jul 27 05:19:20 PM PDT 24
Peak memory 253776 kb
Host smart-167cb795-00fa-4cc2-88e5-506ea1705226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18606
90904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1860690904
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3405427263
Short name T584
Test name
Test status
Simulation time 47938618459 ps
CPU time 1081.49 seconds
Started Jul 27 05:19:17 PM PDT 24
Finished Jul 27 05:37:19 PM PDT 24
Peak memory 288840 kb
Host smart-c4922be7-4ed6-458a-a41d-fdfd86af79af
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405427263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3405427263
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3878415392
Short name T644
Test name
Test status
Simulation time 50627514372 ps
CPU time 3042.6 seconds
Started Jul 27 05:19:23 PM PDT 24
Finished Jul 27 06:10:06 PM PDT 24
Peak memory 289404 kb
Host smart-142dcc6a-e119-4da8-aa8a-2432419de5f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878415392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3878415392
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.1161341363
Short name T35
Test name
Test status
Simulation time 13622874253 ps
CPU time 197.62 seconds
Started Jul 27 05:19:08 PM PDT 24
Finished Jul 27 05:22:26 PM PDT 24
Peak memory 256272 kb
Host smart-691c4b0c-9435-4fac-a5c4-eccf35bb4549
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11613
41363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1161341363
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.77543949
Short name T583
Test name
Test status
Simulation time 925224052 ps
CPU time 55.25 seconds
Started Jul 27 05:19:17 PM PDT 24
Finished Jul 27 05:20:12 PM PDT 24
Peak memory 248736 kb
Host smart-a742befa-16fe-477c-9f64-69abbeb798c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77543
949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.77543949
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1208269915
Short name T293
Test name
Test status
Simulation time 67061580511 ps
CPU time 1127.11 seconds
Started Jul 27 05:19:19 PM PDT 24
Finished Jul 27 05:38:07 PM PDT 24
Peak memory 265192 kb
Host smart-3225a97f-ecfe-4e3d-89db-fc245c212303
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208269915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1208269915
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3277288696
Short name T7
Test name
Test status
Simulation time 7260278769 ps
CPU time 908.6 seconds
Started Jul 27 05:19:20 PM PDT 24
Finished Jul 27 05:34:29 PM PDT 24
Peak memory 283016 kb
Host smart-5c5ecf87-b5b6-495a-932b-45c5a4f4cf83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3277288696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3277288696
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.4160078226
Short name T87
Test name
Test status
Simulation time 50093319 ps
CPU time 4.46 seconds
Started Jul 27 05:19:06 PM PDT 24
Finished Jul 27 05:19:11 PM PDT 24
Peak memory 248808 kb
Host smart-ec91bbdf-ae68-4b95-8a77-cc349883a548
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41600
78226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.4160078226
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.4272978352
Short name T480
Test name
Test status
Simulation time 347178615 ps
CPU time 12.48 seconds
Started Jul 27 05:19:16 PM PDT 24
Finished Jul 27 05:19:28 PM PDT 24
Peak memory 255060 kb
Host smart-2694bde8-a334-46ab-ac43-a4abd61df9c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42729
78352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.4272978352
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.210718136
Short name T495
Test name
Test status
Simulation time 502694777 ps
CPU time 17.28 seconds
Started Jul 27 05:19:07 PM PDT 24
Finished Jul 27 05:19:24 PM PDT 24
Peak memory 248796 kb
Host smart-1adef607-bf50-48c1-a590-a7c11e6c806f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21071
8136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.210718136
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.624984309
Short name T652
Test name
Test status
Simulation time 9476646459 ps
CPU time 75.73 seconds
Started Jul 27 05:19:07 PM PDT 24
Finished Jul 27 05:20:22 PM PDT 24
Peak memory 256920 kb
Host smart-32343b99-916f-4b99-ba17-c9885dbd484b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62498
4309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.624984309
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3667841336
Short name T275
Test name
Test status
Simulation time 41336134927 ps
CPU time 1410.27 seconds
Started Jul 27 05:19:20 PM PDT 24
Finished Jul 27 05:42:51 PM PDT 24
Peak memory 273432 kb
Host smart-fb969e4c-f655-4156-9b85-6e84bd745cf6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667841336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3667841336
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.4015033846
Short name T259
Test name
Test status
Simulation time 37519821015 ps
CPU time 4277.33 seconds
Started Jul 27 05:19:17 PM PDT 24
Finished Jul 27 06:30:35 PM PDT 24
Peak memory 338768 kb
Host smart-2bbd980a-7efb-4998-86fc-92f0ad8858d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015033846 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.4015033846
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1515279155
Short name T363
Test name
Test status
Simulation time 42044626643 ps
CPU time 1036.6 seconds
Started Jul 27 05:19:21 PM PDT 24
Finished Jul 27 05:36:38 PM PDT 24
Peak memory 270308 kb
Host smart-38c5c34d-04d8-4d99-ab46-2c5d33ff3f8b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515279155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1515279155
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2007428538
Short name T455
Test name
Test status
Simulation time 2215584668 ps
CPU time 135.04 seconds
Started Jul 27 05:19:19 PM PDT 24
Finished Jul 27 05:21:34 PM PDT 24
Peak memory 256288 kb
Host smart-add063de-6fb6-4f28-ac63-06cb1c6f7f18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20074
28538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2007428538
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3149656237
Short name T645
Test name
Test status
Simulation time 1088347528 ps
CPU time 29.72 seconds
Started Jul 27 05:19:20 PM PDT 24
Finished Jul 27 05:19:50 PM PDT 24
Peak memory 256796 kb
Host smart-d5a42812-aef8-4aef-8954-04f8c2bf4cbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31496
56237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3149656237
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.468734995
Short name T295
Test name
Test status
Simulation time 15976228614 ps
CPU time 730.5 seconds
Started Jul 27 05:19:20 PM PDT 24
Finished Jul 27 05:31:31 PM PDT 24
Peak memory 265280 kb
Host smart-cd98db5b-84ec-480a-951f-362fdb513064
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468734995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.468734995
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.4175755185
Short name T507
Test name
Test status
Simulation time 70921023359 ps
CPU time 2167.94 seconds
Started Jul 27 05:19:18 PM PDT 24
Finished Jul 27 05:55:26 PM PDT 24
Peak memory 288904 kb
Host smart-4e40c69c-4a46-40c3-bdda-a08877faad49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175755185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.4175755185
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2847847239
Short name T300
Test name
Test status
Simulation time 12444255150 ps
CPU time 475.13 seconds
Started Jul 27 05:19:19 PM PDT 24
Finished Jul 27 05:27:15 PM PDT 24
Peak memory 248840 kb
Host smart-f16f1cff-11f9-4f10-a1fb-8a11ad13db84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847847239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2847847239
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.3321418701
Short name T433
Test name
Test status
Simulation time 628478383 ps
CPU time 32.56 seconds
Started Jul 27 05:19:23 PM PDT 24
Finished Jul 27 05:19:56 PM PDT 24
Peak memory 256296 kb
Host smart-21d66b99-4837-40bc-9024-72be771bf079
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33214
18701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.3321418701
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.19754559
Short name T20
Test name
Test status
Simulation time 5645240419 ps
CPU time 36.73 seconds
Started Jul 27 05:19:19 PM PDT 24
Finished Jul 27 05:19:56 PM PDT 24
Peak memory 256328 kb
Host smart-e2196706-cdd7-428d-bef0-5b397affac6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19754
559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.19754559
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3275608576
Short name T491
Test name
Test status
Simulation time 2150972882 ps
CPU time 70.77 seconds
Started Jul 27 05:19:19 PM PDT 24
Finished Jul 27 05:20:30 PM PDT 24
Peak memory 256564 kb
Host smart-e69d6c6e-56ac-40cf-8ffa-c7034f6fe987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32756
08576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3275608576
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.2159735471
Short name T413
Test name
Test status
Simulation time 37179922 ps
CPU time 5.76 seconds
Started Jul 27 05:19:23 PM PDT 24
Finished Jul 27 05:19:29 PM PDT 24
Peak memory 253780 kb
Host smart-94a3a564-76ec-45fc-91e4-12cfe411f33c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21597
35471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2159735471
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.586424874
Short name T45
Test name
Test status
Simulation time 3289110702 ps
CPU time 317.7 seconds
Started Jul 27 05:19:20 PM PDT 24
Finished Jul 27 05:24:38 PM PDT 24
Peak memory 256400 kb
Host smart-add19aee-ec1e-4066-8b9b-613a6ec1ea74
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586424874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.586424874
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.650593975
Short name T469
Test name
Test status
Simulation time 6597396334 ps
CPU time 123.65 seconds
Started Jul 27 05:19:23 PM PDT 24
Finished Jul 27 05:21:27 PM PDT 24
Peak memory 256492 kb
Host smart-37390d6d-e0af-4eeb-9a00-4118a8539907
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65059
3975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.650593975
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.12223544
Short name T380
Test name
Test status
Simulation time 1015151525 ps
CPU time 26.96 seconds
Started Jul 27 05:19:18 PM PDT 24
Finished Jul 27 05:19:45 PM PDT 24
Peak memory 248724 kb
Host smart-0e2d59d1-f30a-418a-b172-806ffbd833e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12223
544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.12223544
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3818480868
Short name T85
Test name
Test status
Simulation time 27075324406 ps
CPU time 1471.51 seconds
Started Jul 27 05:19:21 PM PDT 24
Finished Jul 27 05:43:53 PM PDT 24
Peak memory 273376 kb
Host smart-1a89000f-150e-4f96-9aa5-53c7c11e08ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818480868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3818480868
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.1944015784
Short name T263
Test name
Test status
Simulation time 15841398845 ps
CPU time 1231.65 seconds
Started Jul 27 05:19:23 PM PDT 24
Finished Jul 27 05:39:55 PM PDT 24
Peak memory 286296 kb
Host smart-b4013013-b9e7-49a3-9b3b-a2ff32d8ba89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944015784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.1944015784
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.198134863
Short name T238
Test name
Test status
Simulation time 21313143594 ps
CPU time 437.07 seconds
Started Jul 27 05:19:20 PM PDT 24
Finished Jul 27 05:26:37 PM PDT 24
Peak memory 248844 kb
Host smart-5e474089-e4a0-4c9b-9dd0-651456398426
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198134863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.198134863
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.1465928727
Short name T49
Test name
Test status
Simulation time 1603070313 ps
CPU time 41.49 seconds
Started Jul 27 05:19:21 PM PDT 24
Finished Jul 27 05:20:03 PM PDT 24
Peak memory 256032 kb
Host smart-a4999b73-c9a1-4e5c-ac6b-d9f4776847ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14659
28727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.1465928727
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.268356886
Short name T545
Test name
Test status
Simulation time 13147744541 ps
CPU time 58.89 seconds
Started Jul 27 05:19:20 PM PDT 24
Finished Jul 27 05:20:20 PM PDT 24
Peak memory 256416 kb
Host smart-99cfa4ce-1a4f-49bb-91c7-9fc08709cb21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26835
6886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.268356886
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.311040353
Short name T519
Test name
Test status
Simulation time 3263971459 ps
CPU time 32.8 seconds
Started Jul 27 05:19:20 PM PDT 24
Finished Jul 27 05:19:54 PM PDT 24
Peak memory 256924 kb
Host smart-cfe9ce7e-a021-4e86-be7d-f9c8e77cb975
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31104
0353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.311040353
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1741920653
Short name T658
Test name
Test status
Simulation time 281918848012 ps
CPU time 1664.55 seconds
Started Jul 27 05:19:19 PM PDT 24
Finished Jul 27 05:47:04 PM PDT 24
Peak memory 286552 kb
Host smart-1795eb7b-10b5-4d34-bbf0-eca714f72a6e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741920653 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1741920653
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.1851065694
Short name T704
Test name
Test status
Simulation time 77576443652 ps
CPU time 1596.04 seconds
Started Jul 27 05:19:20 PM PDT 24
Finished Jul 27 05:45:56 PM PDT 24
Peak memory 289888 kb
Host smart-eaf60249-901c-4fbf-b602-db6d6fbe3c27
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1851065694 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.1851065694
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.3649277581
Short name T68
Test name
Test status
Simulation time 59291576613 ps
CPU time 1867.06 seconds
Started Jul 27 05:19:29 PM PDT 24
Finished Jul 27 05:50:37 PM PDT 24
Peak memory 282276 kb
Host smart-749c38ab-b131-44c4-adf9-687356974143
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649277581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.3649277581
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.958721702
Short name T598
Test name
Test status
Simulation time 7067822438 ps
CPU time 110.83 seconds
Started Jul 27 05:19:19 PM PDT 24
Finished Jul 27 05:21:10 PM PDT 24
Peak memory 256512 kb
Host smart-d02eb2ae-222b-44fa-8b5a-190ac2f1886f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95872
1702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.958721702
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2479555783
Short name T279
Test name
Test status
Simulation time 206073170 ps
CPU time 6.52 seconds
Started Jul 27 05:19:17 PM PDT 24
Finished Jul 27 05:19:24 PM PDT 24
Peak memory 248132 kb
Host smart-ac5c300a-9517-4238-bd37-2846695796dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24795
55783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2479555783
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2648607901
Short name T618
Test name
Test status
Simulation time 57984967548 ps
CPU time 3369.57 seconds
Started Jul 27 05:19:31 PM PDT 24
Finished Jul 27 06:15:41 PM PDT 24
Peak memory 289440 kb
Host smart-15a7d923-85a6-4506-82d8-fb02261f7193
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648607901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2648607901
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.996967010
Short name T316
Test name
Test status
Simulation time 4967318944 ps
CPU time 196.84 seconds
Started Jul 27 05:19:31 PM PDT 24
Finished Jul 27 05:22:49 PM PDT 24
Peak memory 248876 kb
Host smart-044c0c0e-83e1-40b4-92ad-be6774eee053
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996967010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.996967010
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.2165361809
Short name T403
Test name
Test status
Simulation time 669602659 ps
CPU time 26.4 seconds
Started Jul 27 05:19:20 PM PDT 24
Finished Jul 27 05:19:47 PM PDT 24
Peak memory 248684 kb
Host smart-41c0a864-8ca0-49a2-8418-dbbdc745b45a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21653
61809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2165361809
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2564629428
Short name T605
Test name
Test status
Simulation time 475324213 ps
CPU time 25.27 seconds
Started Jul 27 05:19:19 PM PDT 24
Finished Jul 27 05:19:45 PM PDT 24
Peak memory 256504 kb
Host smart-8d15b580-12e0-4bba-ae9d-0be65744cd9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25646
29428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2564629428
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1171139170
Short name T296
Test name
Test status
Simulation time 184576093 ps
CPU time 21.35 seconds
Started Jul 27 05:19:19 PM PDT 24
Finished Jul 27 05:19:40 PM PDT 24
Peak memory 256208 kb
Host smart-68830232-b258-474c-8de7-8ed7f7874681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11711
39170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1171139170
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.836827894
Short name T509
Test name
Test status
Simulation time 1594766701 ps
CPU time 33.59 seconds
Started Jul 27 05:19:22 PM PDT 24
Finished Jul 27 05:19:56 PM PDT 24
Peak memory 256772 kb
Host smart-147f88ec-ef22-4f67-80e6-867ada3c364d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83682
7894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.836827894
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.2917515256
Short name T229
Test name
Test status
Simulation time 131584736438 ps
CPU time 1283.6 seconds
Started Jul 27 05:19:31 PM PDT 24
Finished Jul 27 05:40:55 PM PDT 24
Peak memory 288556 kb
Host smart-f4ad8907-cb6f-4a70-bed6-8e18a9428edf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917515256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.2917515256
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.3923295093
Short name T184
Test name
Test status
Simulation time 4861543395 ps
CPU time 105.08 seconds
Started Jul 27 05:19:32 PM PDT 24
Finished Jul 27 05:21:17 PM PDT 24
Peak memory 256936 kb
Host smart-3916f936-4f97-4cd4-816c-4fec70b6580e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39232
95093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.3923295093
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1515227146
Short name T674
Test name
Test status
Simulation time 3443402814 ps
CPU time 56.21 seconds
Started Jul 27 05:19:31 PM PDT 24
Finished Jul 27 05:20:28 PM PDT 24
Peak memory 248908 kb
Host smart-878076c4-b726-4161-9373-ab384bf5ecd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15152
27146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1515227146
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3927663316
Short name T330
Test name
Test status
Simulation time 435831808378 ps
CPU time 2201.16 seconds
Started Jul 27 05:19:31 PM PDT 24
Finished Jul 27 05:56:12 PM PDT 24
Peak memory 282124 kb
Host smart-49ce0ef6-4ab1-4ace-b96d-d558bc5ea090
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927663316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3927663316
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.898901373
Short name T256
Test name
Test status
Simulation time 151437468417 ps
CPU time 2019.54 seconds
Started Jul 27 05:19:32 PM PDT 24
Finished Jul 27 05:53:12 PM PDT 24
Peak memory 288928 kb
Host smart-4ecb67c4-0a06-4aaf-8d96-9e745eb9e054
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898901373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.898901373
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.740033139
Short name T661
Test name
Test status
Simulation time 20518625635 ps
CPU time 456.05 seconds
Started Jul 27 05:19:31 PM PDT 24
Finished Jul 27 05:27:08 PM PDT 24
Peak memory 248696 kb
Host smart-ec447ffc-6784-4d00-9a7d-2713d0f6db87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740033139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.740033139
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3934974362
Short name T443
Test name
Test status
Simulation time 17570397 ps
CPU time 2.78 seconds
Started Jul 27 05:19:31 PM PDT 24
Finished Jul 27 05:19:34 PM PDT 24
Peak memory 248808 kb
Host smart-c728cbb1-0f7e-4a53-9df4-910aba4f5c3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39349
74362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3934974362
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.526614096
Short name T568
Test name
Test status
Simulation time 3093918527 ps
CPU time 23.89 seconds
Started Jul 27 05:19:31 PM PDT 24
Finished Jul 27 05:19:55 PM PDT 24
Peak memory 248256 kb
Host smart-7b1e9fbd-5b27-463c-8a68-ab1856410091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52661
4096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.526614096
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.2223589879
Short name T283
Test name
Test status
Simulation time 1462243349 ps
CPU time 43.07 seconds
Started Jul 27 05:19:31 PM PDT 24
Finished Jul 27 05:20:14 PM PDT 24
Peak memory 248600 kb
Host smart-439f6b9c-6149-43e4-a81f-ad7049e7d710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22235
89879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2223589879
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.2472551058
Short name T460
Test name
Test status
Simulation time 377834194 ps
CPU time 33.77 seconds
Started Jul 27 05:19:30 PM PDT 24
Finished Jul 27 05:20:04 PM PDT 24
Peak memory 256972 kb
Host smart-7ad12f5d-b266-49af-9988-cb701dae3ce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24725
51058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.2472551058
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1445633347
Short name T237
Test name
Test status
Simulation time 1916459578 ps
CPU time 174.89 seconds
Started Jul 27 05:19:32 PM PDT 24
Finished Jul 27 05:22:27 PM PDT 24
Peak memory 256876 kb
Host smart-cd219c40-0861-4588-94d5-03ce30714e53
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445633347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1445633347
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.2136181852
Short name T115
Test name
Test status
Simulation time 298860571998 ps
CPU time 2085.17 seconds
Started Jul 27 05:19:31 PM PDT 24
Finished Jul 27 05:54:17 PM PDT 24
Peak memory 288036 kb
Host smart-1b695f41-4533-47e1-892a-c592a3f4870d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136181852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.2136181852
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.3999000716
Short name T679
Test name
Test status
Simulation time 15295058962 ps
CPU time 232.96 seconds
Started Jul 27 05:19:32 PM PDT 24
Finished Jul 27 05:23:25 PM PDT 24
Peak memory 257056 kb
Host smart-c2fa9990-e936-41ca-9dfd-dad15f97c2ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39990
00716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.3999000716
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.682184910
Short name T109
Test name
Test status
Simulation time 1241660090 ps
CPU time 60.12 seconds
Started Jul 27 05:19:30 PM PDT 24
Finished Jul 27 05:20:30 PM PDT 24
Peak memory 256144 kb
Host smart-45a026c5-00ac-48c9-8bac-b6efda7dc00e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68218
4910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.682184910
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1684537206
Short name T334
Test name
Test status
Simulation time 36269367847 ps
CPU time 1360.54 seconds
Started Jul 27 05:19:33 PM PDT 24
Finished Jul 27 05:42:13 PM PDT 24
Peak memory 289120 kb
Host smart-8eebf5aa-25da-4904-93f9-039ed6d3bf3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684537206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1684537206
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.531736699
Short name T687
Test name
Test status
Simulation time 89655994856 ps
CPU time 2661.88 seconds
Started Jul 27 05:19:31 PM PDT 24
Finished Jul 27 06:03:53 PM PDT 24
Peak memory 289120 kb
Host smart-9900e8fb-2979-403e-a0c7-d06c9b619d23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531736699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.531736699
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.1178685985
Short name T513
Test name
Test status
Simulation time 2893636179 ps
CPU time 111.52 seconds
Started Jul 27 05:19:30 PM PDT 24
Finished Jul 27 05:21:22 PM PDT 24
Peak memory 248620 kb
Host smart-784b0ca3-4647-42df-9a7e-ea0881e3007a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178685985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1178685985
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.245231021
Short name T350
Test name
Test status
Simulation time 3207837080 ps
CPU time 55.25 seconds
Started Jul 27 05:19:30 PM PDT 24
Finished Jul 27 05:20:26 PM PDT 24
Peak memory 257056 kb
Host smart-ab7ce939-8f76-4acc-a606-d214ba623126
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24523
1021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.245231021
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.1620197413
Short name T508
Test name
Test status
Simulation time 244595302 ps
CPU time 19.85 seconds
Started Jul 27 05:19:31 PM PDT 24
Finished Jul 27 05:19:51 PM PDT 24
Peak memory 248268 kb
Host smart-a63dbf96-8e6c-42ff-a718-b0e7c125b93c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16201
97413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.1620197413
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.129127153
Short name T590
Test name
Test status
Simulation time 192981674 ps
CPU time 6.47 seconds
Started Jul 27 05:19:29 PM PDT 24
Finished Jul 27 05:19:36 PM PDT 24
Peak memory 248836 kb
Host smart-5fb9a897-63ae-47de-b7d8-fee31306b4f8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12912
7153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.129127153
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.1593035347
Short name T362
Test name
Test status
Simulation time 1968883902 ps
CPU time 27.43 seconds
Started Jul 27 05:19:31 PM PDT 24
Finished Jul 27 05:19:59 PM PDT 24
Peak memory 256812 kb
Host smart-404fc4ec-6cd6-41c8-80a7-a0620d715405
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15930
35347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.1593035347
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2867764805
Short name T232
Test name
Test status
Simulation time 20048727282 ps
CPU time 913.47 seconds
Started Jul 27 05:19:44 PM PDT 24
Finished Jul 27 05:34:58 PM PDT 24
Peak memory 273120 kb
Host smart-85e14433-7d93-4130-8fac-ebbc6f59b263
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867764805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2867764805
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.225567387
Short name T547
Test name
Test status
Simulation time 3232999625 ps
CPU time 49.57 seconds
Started Jul 27 05:19:31 PM PDT 24
Finished Jul 27 05:20:21 PM PDT 24
Peak memory 256572 kb
Host smart-55a57b58-2c92-4352-b262-3ea9bb2cee15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22556
7387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.225567387
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.781684972
Short name T544
Test name
Test status
Simulation time 99354434 ps
CPU time 13.35 seconds
Started Jul 27 05:19:32 PM PDT 24
Finished Jul 27 05:19:46 PM PDT 24
Peak memory 256432 kb
Host smart-801bd445-be39-4e41-89a8-6e5e58bbfc99
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78168
4972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.781684972
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.2971298414
Short name T335
Test name
Test status
Simulation time 38862629558 ps
CPU time 845.72 seconds
Started Jul 27 05:19:47 PM PDT 24
Finished Jul 27 05:33:52 PM PDT 24
Peak memory 272668 kb
Host smart-89f532c9-e246-4b86-b566-83b7c9b31456
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971298414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2971298414
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3852121499
Short name T693
Test name
Test status
Simulation time 79617391203 ps
CPU time 2176.29 seconds
Started Jul 27 05:19:47 PM PDT 24
Finished Jul 27 05:56:04 PM PDT 24
Peak memory 283972 kb
Host smart-6c5ae016-65c0-4101-937d-507411dc9e5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852121499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3852121499
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1815794046
Short name T1
Test name
Test status
Simulation time 21632679891 ps
CPU time 407.23 seconds
Started Jul 27 05:19:42 PM PDT 24
Finished Jul 27 05:26:30 PM PDT 24
Peak memory 248772 kb
Host smart-20af1b05-29aa-4976-a346-c48943cd2a32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815794046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1815794046
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1624261581
Short name T44
Test name
Test status
Simulation time 271688040 ps
CPU time 24.54 seconds
Started Jul 27 05:19:30 PM PDT 24
Finished Jul 27 05:19:55 PM PDT 24
Peak memory 248836 kb
Host smart-3d333b48-4e4a-4ce9-8298-4f8161dd5c3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16242
61581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1624261581
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.1552229662
Short name T399
Test name
Test status
Simulation time 4480697012 ps
CPU time 62.95 seconds
Started Jul 27 05:19:32 PM PDT 24
Finished Jul 27 05:20:35 PM PDT 24
Peak memory 248876 kb
Host smart-44178aa3-97e0-4c12-b3cd-4912fac41e9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15522
29662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.1552229662
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3923040147
Short name T617
Test name
Test status
Simulation time 420505001 ps
CPU time 8.94 seconds
Started Jul 27 05:19:43 PM PDT 24
Finished Jul 27 05:19:52 PM PDT 24
Peak memory 253732 kb
Host smart-87cd2b30-347b-4abd-b0d2-dffad0bbd044
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39230
40147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3923040147
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3369772836
Short name T699
Test name
Test status
Simulation time 227147868 ps
CPU time 4.68 seconds
Started Jul 27 05:19:31 PM PDT 24
Finished Jul 27 05:19:36 PM PDT 24
Peak memory 250956 kb
Host smart-b69302e8-7910-4c76-ade8-d6f5b3081c64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33697
72836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3369772836
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3187521963
Short name T248
Test name
Test status
Simulation time 42050532692 ps
CPU time 2507.25 seconds
Started Jul 27 05:19:43 PM PDT 24
Finished Jul 27 06:01:31 PM PDT 24
Peak memory 301868 kb
Host smart-c21cb4be-c036-4101-958a-ba74e7832705
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187521963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3187521963
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.3398287576
Short name T613
Test name
Test status
Simulation time 31320832461 ps
CPU time 644.82 seconds
Started Jul 27 05:19:43 PM PDT 24
Finished Jul 27 05:30:28 PM PDT 24
Peak memory 273360 kb
Host smart-a9cdd6a7-5330-44ca-a7e6-aa72308c4eb3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398287576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.3398287576
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.4126836298
Short name T447
Test name
Test status
Simulation time 210043414 ps
CPU time 22.42 seconds
Started Jul 27 05:19:44 PM PDT 24
Finished Jul 27 05:20:07 PM PDT 24
Peak memory 256532 kb
Host smart-4e7040e9-5cf6-4ac1-97a8-e1521201051b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41268
36298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.4126836298
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2876303344
Short name T678
Test name
Test status
Simulation time 213624856 ps
CPU time 22.05 seconds
Started Jul 27 05:19:44 PM PDT 24
Finished Jul 27 05:20:06 PM PDT 24
Peak memory 248572 kb
Host smart-a28fcf61-1629-4b92-94ab-14e431158d4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28763
03344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2876303344
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2004041312
Short name T324
Test name
Test status
Simulation time 49781943949 ps
CPU time 2902.89 seconds
Started Jul 27 05:19:42 PM PDT 24
Finished Jul 27 06:08:05 PM PDT 24
Peak memory 289764 kb
Host smart-2c689c52-cb0f-4aa7-9f99-ad8eb9fb2073
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004041312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2004041312
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.2842589799
Short name T435
Test name
Test status
Simulation time 84028934977 ps
CPU time 2579.26 seconds
Started Jul 27 05:19:43 PM PDT 24
Finished Jul 27 06:02:43 PM PDT 24
Peak memory 288896 kb
Host smart-d4fef662-3355-4040-9f14-0258e1dfb12f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842589799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.2842589799
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.666509276
Short name T312
Test name
Test status
Simulation time 25842744739 ps
CPU time 554.73 seconds
Started Jul 27 05:19:43 PM PDT 24
Finished Jul 27 05:28:58 PM PDT 24
Peak memory 248912 kb
Host smart-f9c93924-5300-4292-838a-e21e228c1ee7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666509276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.666509276
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.3039979621
Short name T348
Test name
Test status
Simulation time 944037624 ps
CPU time 21.3 seconds
Started Jul 27 05:19:43 PM PDT 24
Finished Jul 27 05:20:04 PM PDT 24
Peak memory 256292 kb
Host smart-a37a1a2f-d7ff-4ce7-98ce-ba201c976310
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30399
79621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.3039979621
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.1274894099
Short name T557
Test name
Test status
Simulation time 762452420 ps
CPU time 14.95 seconds
Started Jul 27 05:19:48 PM PDT 24
Finished Jul 27 05:20:03 PM PDT 24
Peak memory 248156 kb
Host smart-94d5064c-d479-4227-bd1e-63c2eedbbe9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12748
94099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.1274894099
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.1436644253
Short name T620
Test name
Test status
Simulation time 768193725 ps
CPU time 29 seconds
Started Jul 27 05:19:44 PM PDT 24
Finished Jul 27 05:20:13 PM PDT 24
Peak memory 249284 kb
Host smart-01c2246a-a2e7-4703-b3a7-78df20cfd5ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14366
44253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1436644253
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2210893744
Short name T243
Test name
Test status
Simulation time 921497818 ps
CPU time 14.37 seconds
Started Jul 27 05:19:44 PM PDT 24
Finished Jul 27 05:19:59 PM PDT 24
Peak memory 255212 kb
Host smart-cca65425-875f-473d-b86e-ad0c9984ea5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22108
93744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2210893744
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.3031378832
Short name T98
Test name
Test status
Simulation time 28893808809 ps
CPU time 1355.1 seconds
Started Jul 27 05:19:45 PM PDT 24
Finished Jul 27 05:42:21 PM PDT 24
Peak memory 289404 kb
Host smart-1179ea33-55f1-4e92-aaf6-cf715b1398d8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031378832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.3031378832
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.990341948
Short name T372
Test name
Test status
Simulation time 8591265043 ps
CPU time 87.87 seconds
Started Jul 27 05:19:42 PM PDT 24
Finished Jul 27 05:21:10 PM PDT 24
Peak memory 256388 kb
Host smart-7de4ac59-9da4-47fd-b15d-6febf53a5cd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99034
1948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.990341948
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3697619175
Short name T430
Test name
Test status
Simulation time 768735808 ps
CPU time 42.72 seconds
Started Jul 27 05:19:43 PM PDT 24
Finished Jul 27 05:20:26 PM PDT 24
Peak memory 255444 kb
Host smart-2513d56a-8d5f-40fd-b529-f0a43c1ea238
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36976
19175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3697619175
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.759814361
Short name T536
Test name
Test status
Simulation time 13630133451 ps
CPU time 1376.25 seconds
Started Jul 27 05:19:43 PM PDT 24
Finished Jul 27 05:42:39 PM PDT 24
Peak memory 288272 kb
Host smart-3c9acd6c-67a5-4ade-81d9-7425ce3cba9b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759814361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.759814361
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.746326184
Short name T615
Test name
Test status
Simulation time 9162188870 ps
CPU time 688.19 seconds
Started Jul 27 05:19:44 PM PDT 24
Finished Jul 27 05:31:13 PM PDT 24
Peak memory 272916 kb
Host smart-a5dac042-0517-45ae-bcc2-4f88d63cb38a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746326184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.746326184
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.2309561492
Short name T257
Test name
Test status
Simulation time 15448956824 ps
CPU time 311.9 seconds
Started Jul 27 05:19:43 PM PDT 24
Finished Jul 27 05:24:55 PM PDT 24
Peak memory 249116 kb
Host smart-b1bb85ff-9525-484b-a274-5afe56c86089
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309561492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.2309561492
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.83192086
Short name T448
Test name
Test status
Simulation time 898913628 ps
CPU time 19.38 seconds
Started Jul 27 05:19:44 PM PDT 24
Finished Jul 27 05:20:03 PM PDT 24
Peak memory 248728 kb
Host smart-3618e6f9-332a-4f5a-9ad7-37209482d865
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83192
086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.83192086
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2872503603
Short name T86
Test name
Test status
Simulation time 332420501 ps
CPU time 21.11 seconds
Started Jul 27 05:19:43 PM PDT 24
Finished Jul 27 05:20:04 PM PDT 24
Peak memory 248136 kb
Host smart-1f9e98b3-74c6-4daf-979f-5994a19d9a2e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28725
03603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2872503603
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.219909627
Short name T671
Test name
Test status
Simulation time 670733983 ps
CPU time 14.36 seconds
Started Jul 27 05:19:43 PM PDT 24
Finished Jul 27 05:19:57 PM PDT 24
Peak memory 248676 kb
Host smart-90a5bcc4-969a-46d9-b740-5f4a5b2df0c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21990
9627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.219909627
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1957196729
Short name T488
Test name
Test status
Simulation time 160287833 ps
CPU time 12.73 seconds
Started Jul 27 05:19:44 PM PDT 24
Finished Jul 27 05:19:57 PM PDT 24
Peak memory 256916 kb
Host smart-dd516bd4-5621-4799-8ae3-a0af1009b693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19571
96729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1957196729
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1294099012
Short name T518
Test name
Test status
Simulation time 2202910708 ps
CPU time 24.5 seconds
Started Jul 27 05:19:42 PM PDT 24
Finished Jul 27 05:20:06 PM PDT 24
Peak memory 255252 kb
Host smart-fb3a0030-c7d4-486e-8e87-e6bfd2c09841
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294099012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1294099012
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.4077319439
Short name T240
Test name
Test status
Simulation time 28961725507 ps
CPU time 1817.11 seconds
Started Jul 27 05:19:44 PM PDT 24
Finished Jul 27 05:50:01 PM PDT 24
Peak memory 280656 kb
Host smart-059d1ea9-6d4e-4cc1-b357-6f0c8b157da8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077319439 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.4077319439
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.2600203068
Short name T200
Test name
Test status
Simulation time 151436273 ps
CPU time 2.75 seconds
Started Jul 27 05:18:17 PM PDT 24
Finished Jul 27 05:18:20 PM PDT 24
Peak memory 249016 kb
Host smart-b28335dc-0b93-4aa5-97a1-51014f62d047
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2600203068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2600203068
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.3356963475
Short name T104
Test name
Test status
Simulation time 19099444066 ps
CPU time 1427.54 seconds
Started Jul 27 05:18:17 PM PDT 24
Finished Jul 27 05:42:05 PM PDT 24
Peak memory 289828 kb
Host smart-fee97149-7109-400f-9921-893ecec7e03a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356963475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.3356963475
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.3288942256
Short name T408
Test name
Test status
Simulation time 336354254 ps
CPU time 10.05 seconds
Started Jul 27 05:18:16 PM PDT 24
Finished Jul 27 05:18:26 PM PDT 24
Peak memory 248716 kb
Host smart-1a43db9c-5ef0-4cb4-941b-b9d5a75c07ed
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3288942256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3288942256
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.429506277
Short name T233
Test name
Test status
Simulation time 1522553802 ps
CPU time 35.01 seconds
Started Jul 27 05:18:19 PM PDT 24
Finished Jul 27 05:18:54 PM PDT 24
Peak memory 256504 kb
Host smart-4716b0d3-b251-41b5-919f-305ae4702c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42950
6277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.429506277
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.1630042630
Short name T608
Test name
Test status
Simulation time 943128949 ps
CPU time 17.38 seconds
Started Jul 27 05:18:18 PM PDT 24
Finished Jul 27 05:18:36 PM PDT 24
Peak memory 248816 kb
Host smart-ea41f140-a77a-4242-a298-c38a2acff708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16300
42630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1630042630
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3650417572
Short name T244
Test name
Test status
Simulation time 39989724665 ps
CPU time 2323.49 seconds
Started Jul 27 05:18:16 PM PDT 24
Finished Jul 27 05:57:00 PM PDT 24
Peak memory 289124 kb
Host smart-bb74105e-3e5d-4ea1-91da-edd67cec1f7c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650417572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3650417572
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.515126535
Short name T487
Test name
Test status
Simulation time 9321319737 ps
CPU time 990.23 seconds
Started Jul 27 05:18:16 PM PDT 24
Finished Jul 27 05:34:46 PM PDT 24
Peak memory 273372 kb
Host smart-389fcabd-8d83-47ab-8be5-843a731eb366
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515126535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.515126535
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.2368775581
Short name T662
Test name
Test status
Simulation time 14151723380 ps
CPU time 314.5 seconds
Started Jul 27 05:18:17 PM PDT 24
Finished Jul 27 05:23:32 PM PDT 24
Peak memory 256056 kb
Host smart-b843fa64-1846-4540-8fe7-6017da7677d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368775581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.2368775581
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2102791994
Short name T346
Test name
Test status
Simulation time 2235322784 ps
CPU time 40.59 seconds
Started Jul 27 05:18:17 PM PDT 24
Finished Jul 27 05:18:58 PM PDT 24
Peak memory 248904 kb
Host smart-ecea36d0-681c-4c3c-a1a3-31b25af5a807
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21027
91994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2102791994
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.602654647
Short name T454
Test name
Test status
Simulation time 2371095493 ps
CPU time 34.84 seconds
Started Jul 27 05:18:15 PM PDT 24
Finished Jul 27 05:18:50 PM PDT 24
Peak memory 255392 kb
Host smart-962b2e77-edaa-4d2a-85ff-6dcaf480a573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60265
4647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.602654647
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1522545206
Short name T9
Test name
Test status
Simulation time 428064745 ps
CPU time 12.94 seconds
Started Jul 27 05:18:16 PM PDT 24
Finished Jul 27 05:18:29 PM PDT 24
Peak memory 269916 kb
Host smart-36f2660f-90b3-4306-bcdf-07d69b2f489e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1522545206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1522545206
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.216989098
Short name T83
Test name
Test status
Simulation time 1753388305 ps
CPU time 27.89 seconds
Started Jul 27 05:18:15 PM PDT 24
Finished Jul 27 05:18:43 PM PDT 24
Peak memory 256284 kb
Host smart-34a59d3b-0613-42c9-9d0e-30420f347c33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21698
9098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.216989098
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2593405709
Short name T530
Test name
Test status
Simulation time 93980178 ps
CPU time 5.08 seconds
Started Jul 27 05:18:15 PM PDT 24
Finished Jul 27 05:18:21 PM PDT 24
Peak memory 248728 kb
Host smart-e2dcedc8-e6e5-443c-b31f-880dd9d50ed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25934
05709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2593405709
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.1085735989
Short name T96
Test name
Test status
Simulation time 187843550989 ps
CPU time 971.35 seconds
Started Jul 27 05:18:16 PM PDT 24
Finished Jul 27 05:34:28 PM PDT 24
Peak memory 283864 kb
Host smart-3f79f7c7-706e-4f9d-80ad-a5651ba49d0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085735989 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.1085735989
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1246442176
Short name T105
Test name
Test status
Simulation time 9831799950 ps
CPU time 964.55 seconds
Started Jul 27 05:19:44 PM PDT 24
Finished Jul 27 05:35:49 PM PDT 24
Peak memory 281452 kb
Host smart-803b9b9f-31d2-4d40-bc8b-bc8ab6f4edc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246442176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1246442176
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1817241506
Short name T478
Test name
Test status
Simulation time 1702713088 ps
CPU time 36.78 seconds
Started Jul 27 05:19:44 PM PDT 24
Finished Jul 27 05:20:21 PM PDT 24
Peak memory 249756 kb
Host smart-3f689633-7fb0-444f-8a3f-3b1fc1fc3708
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18172
41506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1817241506
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.4274067289
Short name T423
Test name
Test status
Simulation time 673293886 ps
CPU time 38.27 seconds
Started Jul 27 05:19:44 PM PDT 24
Finished Jul 27 05:20:22 PM PDT 24
Peak memory 248836 kb
Host smart-8edd36bc-967b-4ccd-af23-64e8e39a6726
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42740
67289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.4274067289
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.816527974
Short name T338
Test name
Test status
Simulation time 150888450083 ps
CPU time 2350.23 seconds
Started Jul 27 05:19:42 PM PDT 24
Finished Jul 27 05:58:53 PM PDT 24
Peak memory 284928 kb
Host smart-dfbb44ca-91df-4672-aaf4-2ba292ed1acd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816527974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.816527974
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.1397238008
Short name T663
Test name
Test status
Simulation time 511986132051 ps
CPU time 1691.31 seconds
Started Jul 27 05:19:48 PM PDT 24
Finished Jul 27 05:47:59 PM PDT 24
Peak memory 268248 kb
Host smart-97167b53-c91a-4206-acdd-be2548eb0cd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397238008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.1397238008
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.4115673395
Short name T302
Test name
Test status
Simulation time 7692283889 ps
CPU time 323.46 seconds
Started Jul 27 05:19:43 PM PDT 24
Finished Jul 27 05:25:07 PM PDT 24
Peak memory 248868 kb
Host smart-65540db6-609c-4053-a7a7-5aa1513f4315
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115673395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.4115673395
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.1910353536
Short name T621
Test name
Test status
Simulation time 216344666 ps
CPU time 25.37 seconds
Started Jul 27 05:19:42 PM PDT 24
Finished Jul 27 05:20:07 PM PDT 24
Peak memory 248744 kb
Host smart-079c12be-6548-48eb-b126-399e38d484cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19103
53536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1910353536
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2995114400
Short name T3
Test name
Test status
Simulation time 386913229 ps
CPU time 30.18 seconds
Started Jul 27 05:19:45 PM PDT 24
Finished Jul 27 05:20:16 PM PDT 24
Peak memory 256864 kb
Host smart-a772bcb8-a6cd-4de4-a8fd-ad8a39c3d308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29951
14400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2995114400
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.3925296645
Short name T381
Test name
Test status
Simulation time 647407469 ps
CPU time 10.66 seconds
Started Jul 27 05:19:43 PM PDT 24
Finished Jul 27 05:19:54 PM PDT 24
Peak memory 248836 kb
Host smart-2439f82b-9849-457e-b0c5-5e8375e2c66f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39252
96645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.3925296645
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.606880689
Short name T675
Test name
Test status
Simulation time 406283772 ps
CPU time 7.86 seconds
Started Jul 27 05:19:43 PM PDT 24
Finished Jul 27 05:19:51 PM PDT 24
Peak memory 252136 kb
Host smart-60ccbdc3-37c0-488d-804e-24f01c0c56df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60688
0689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.606880689
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1592943596
Short name T656
Test name
Test status
Simulation time 1962996412 ps
CPU time 108.5 seconds
Started Jul 27 05:19:55 PM PDT 24
Finished Jul 27 05:21:43 PM PDT 24
Peak memory 256928 kb
Host smart-aea1704e-afc2-4142-aab3-174c0ab62b60
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592943596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1592943596
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.2475328162
Short name T371
Test name
Test status
Simulation time 20244191307 ps
CPU time 1315.8 seconds
Started Jul 27 05:19:52 PM PDT 24
Finished Jul 27 05:41:48 PM PDT 24
Peak memory 273416 kb
Host smart-e642e176-c3ce-4988-9abf-de094e5e0a69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475328162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.2475328162
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.2959719574
Short name T39
Test name
Test status
Simulation time 20812334653 ps
CPU time 261.56 seconds
Started Jul 27 05:19:52 PM PDT 24
Finished Jul 27 05:24:14 PM PDT 24
Peak memory 251976 kb
Host smart-a0837899-83ae-47da-9391-70aa61ab800f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29597
19574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.2959719574
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.4283918984
Short name T593
Test name
Test status
Simulation time 485355662 ps
CPU time 13.71 seconds
Started Jul 27 05:19:55 PM PDT 24
Finished Jul 27 05:20:09 PM PDT 24
Peak memory 248408 kb
Host smart-884cb375-ef7b-4f07-bb02-9ba22fd3c63c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42839
18984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.4283918984
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3942749854
Short name T245
Test name
Test status
Simulation time 16731550332 ps
CPU time 1213.81 seconds
Started Jul 27 05:19:54 PM PDT 24
Finished Jul 27 05:40:08 PM PDT 24
Peak memory 288980 kb
Host smart-61d51fbc-26a4-4201-97d4-0211a34f5246
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942749854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3942749854
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.989298708
Short name T523
Test name
Test status
Simulation time 51875434808 ps
CPU time 1753.73 seconds
Started Jul 27 05:19:53 PM PDT 24
Finished Jul 27 05:49:07 PM PDT 24
Peak memory 283592 kb
Host smart-97fa6bff-e1eb-4e4f-83d6-4928f3586b27
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989298708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.989298708
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.587366040
Short name T297
Test name
Test status
Simulation time 28880333985 ps
CPU time 565.5 seconds
Started Jul 27 05:19:53 PM PDT 24
Finished Jul 27 05:29:18 PM PDT 24
Peak memory 256864 kb
Host smart-212f3c1a-306b-47b9-bc07-e4b715b32cee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587366040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.587366040
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1019333007
Short name T406
Test name
Test status
Simulation time 113361346 ps
CPU time 5.63 seconds
Started Jul 27 05:19:57 PM PDT 24
Finished Jul 27 05:20:03 PM PDT 24
Peak memory 248800 kb
Host smart-b293eab4-45ed-4c64-8222-22462b47833c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10193
33007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1019333007
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3444972776
Short name T78
Test name
Test status
Simulation time 933911963 ps
CPU time 47.87 seconds
Started Jul 27 05:19:57 PM PDT 24
Finished Jul 27 05:20:45 PM PDT 24
Peak memory 256984 kb
Host smart-d639a1b8-3cec-4658-8727-ca4909608b19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34449
72776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3444972776
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.2812509022
Short name T450
Test name
Test status
Simulation time 1784795606 ps
CPU time 27.95 seconds
Started Jul 27 05:19:55 PM PDT 24
Finished Jul 27 05:20:23 PM PDT 24
Peak memory 256192 kb
Host smart-01b75bfd-80a5-4da2-9de9-20bff09047dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28125
09022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.2812509022
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1602697333
Short name T622
Test name
Test status
Simulation time 1096968123 ps
CPU time 17.44 seconds
Started Jul 27 05:19:57 PM PDT 24
Finished Jul 27 05:20:15 PM PDT 24
Peak memory 256464 kb
Host smart-aec9e0fd-7cbc-4310-b653-6689a095211d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16026
97333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1602697333
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.842683605
Short name T426
Test name
Test status
Simulation time 17608220084 ps
CPU time 1687.78 seconds
Started Jul 27 05:19:54 PM PDT 24
Finished Jul 27 05:48:02 PM PDT 24
Peak memory 289760 kb
Host smart-edc37fd9-5849-4545-b205-ba25de8e066a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842683605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_han
dler_stress_all.842683605
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.377071928
Short name T576
Test name
Test status
Simulation time 131947044133 ps
CPU time 2417.79 seconds
Started Jul 27 05:19:55 PM PDT 24
Finished Jul 27 06:00:13 PM PDT 24
Peak memory 287688 kb
Host smart-b75b2cb9-897f-48a3-848d-315587c2dd4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377071928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.377071928
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.3596648750
Short name T485
Test name
Test status
Simulation time 3734594147 ps
CPU time 186.12 seconds
Started Jul 27 05:19:55 PM PDT 24
Finished Jul 27 05:23:01 PM PDT 24
Peak memory 252084 kb
Host smart-400cc4f7-0a2f-44c9-9cdc-3adba93d3730
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35966
48750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3596648750
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.2481477378
Short name T94
Test name
Test status
Simulation time 62645117 ps
CPU time 5.2 seconds
Started Jul 27 05:19:55 PM PDT 24
Finished Jul 27 05:20:00 PM PDT 24
Peak memory 240640 kb
Host smart-9e014aa6-005b-442c-acf0-30598a22e384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24814
77378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2481477378
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.1350351204
Short name T329
Test name
Test status
Simulation time 18860259136 ps
CPU time 997.81 seconds
Started Jul 27 05:19:54 PM PDT 24
Finished Jul 27 05:36:32 PM PDT 24
Peak memory 289100 kb
Host smart-a52fee39-3734-43e3-aa77-d22834666f8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350351204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1350351204
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2867406682
Short name T253
Test name
Test status
Simulation time 44773334297 ps
CPU time 954.49 seconds
Started Jul 27 05:19:55 PM PDT 24
Finished Jul 27 05:35:49 PM PDT 24
Peak memory 269564 kb
Host smart-56ea859d-274c-48fd-ab7a-7e0d7c1fe19c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867406682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2867406682
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.904215102
Short name T533
Test name
Test status
Simulation time 39186811588 ps
CPU time 392.7 seconds
Started Jul 27 05:19:56 PM PDT 24
Finished Jul 27 05:26:28 PM PDT 24
Peak memory 248708 kb
Host smart-26ffd2d5-52b6-4268-bc78-df1e79ea0e33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904215102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.904215102
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2436642755
Short name T471
Test name
Test status
Simulation time 21250782 ps
CPU time 3.54 seconds
Started Jul 27 05:19:54 PM PDT 24
Finished Jul 27 05:19:57 PM PDT 24
Peak memory 248868 kb
Host smart-d4798c1c-d182-4f05-8d86-094805e6b9db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24366
42755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2436642755
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.2656870963
Short name T481
Test name
Test status
Simulation time 615533123 ps
CPU time 39.89 seconds
Started Jul 27 05:19:55 PM PDT 24
Finished Jul 27 05:20:35 PM PDT 24
Peak memory 248648 kb
Host smart-6c0527e9-8665-4329-8727-3ebc0fa7175f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26568
70963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.2656870963
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.855551946
Short name T416
Test name
Test status
Simulation time 492770515 ps
CPU time 30.67 seconds
Started Jul 27 05:19:58 PM PDT 24
Finished Jul 27 05:20:29 PM PDT 24
Peak memory 248724 kb
Host smart-daa3ebd1-6006-4ea1-bdca-94998f511621
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85555
1946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.855551946
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.2938184309
Short name T180
Test name
Test status
Simulation time 113926833 ps
CPU time 11.98 seconds
Started Jul 27 05:19:55 PM PDT 24
Finished Jul 27 05:20:07 PM PDT 24
Peak memory 256968 kb
Host smart-1c184924-e693-4603-9e5b-ee14a6ac81e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29381
84309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.2938184309
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2091487018
Short name T113
Test name
Test status
Simulation time 62564658440 ps
CPU time 3766.65 seconds
Started Jul 27 05:19:54 PM PDT 24
Finished Jul 27 06:22:41 PM PDT 24
Peak memory 289800 kb
Host smart-96ce8948-afd2-4642-a29b-85bdee9acc12
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091487018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2091487018
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2098765680
Short name T386
Test name
Test status
Simulation time 371806272707 ps
CPU time 2428.05 seconds
Started Jul 27 05:19:53 PM PDT 24
Finished Jul 27 06:00:21 PM PDT 24
Peak memory 288392 kb
Host smart-d1b4448a-d310-4074-b498-832682d66341
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098765680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2098765680
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.372326282
Short name T402
Test name
Test status
Simulation time 1002334395 ps
CPU time 19.2 seconds
Started Jul 27 05:19:54 PM PDT 24
Finished Jul 27 05:20:14 PM PDT 24
Peak memory 256424 kb
Host smart-8267807a-2f30-4d7e-8dbd-2d2f353ab587
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37232
6282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.372326282
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.4232428874
Short name T641
Test name
Test status
Simulation time 1227133755 ps
CPU time 43.6 seconds
Started Jul 27 05:19:57 PM PDT 24
Finished Jul 27 05:20:40 PM PDT 24
Peak memory 248796 kb
Host smart-f3f9eefc-1051-4856-b0bc-e8186b71cb8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42324
28874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.4232428874
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.3743060216
Short name T336
Test name
Test status
Simulation time 29748747426 ps
CPU time 1842.55 seconds
Started Jul 27 05:20:07 PM PDT 24
Finished Jul 27 05:50:50 PM PDT 24
Peak memory 273292 kb
Host smart-81a6bb8a-8126-4071-82f0-7dc36429245d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743060216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.3743060216
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3499860531
Short name T419
Test name
Test status
Simulation time 67531785549 ps
CPU time 2193.3 seconds
Started Jul 27 05:20:04 PM PDT 24
Finished Jul 27 05:56:38 PM PDT 24
Peak memory 288624 kb
Host smart-dbf62ca5-6500-457b-b162-871626dc32c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499860531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3499860531
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.832262271
Short name T315
Test name
Test status
Simulation time 78139846372 ps
CPU time 506.76 seconds
Started Jul 27 05:19:57 PM PDT 24
Finished Jul 27 05:28:24 PM PDT 24
Peak memory 248848 kb
Host smart-176f55c0-315d-4212-8559-fb94a2b63d6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832262271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.832262271
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.2621973168
Short name T347
Test name
Test status
Simulation time 4546471044 ps
CPU time 38.12 seconds
Started Jul 27 05:19:58 PM PDT 24
Finished Jul 27 05:20:36 PM PDT 24
Peak memory 248788 kb
Host smart-e2c09bf0-0d7d-464e-9420-2ca243ccc43e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26219
73168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2621973168
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.1369708230
Short name T572
Test name
Test status
Simulation time 339470206 ps
CPU time 28.86 seconds
Started Jul 27 05:19:54 PM PDT 24
Finished Jul 27 05:20:23 PM PDT 24
Peak memory 248276 kb
Host smart-d502057f-54b7-4936-9f9f-3a57837c4685
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13697
08230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1369708230
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2812242062
Short name T642
Test name
Test status
Simulation time 225595444 ps
CPU time 25.92 seconds
Started Jul 27 05:19:55 PM PDT 24
Finished Jul 27 05:20:21 PM PDT 24
Peak memory 248684 kb
Host smart-f05922dc-06ce-46bb-bff0-5b20377dc982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28122
42062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2812242062
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.766413266
Short name T439
Test name
Test status
Simulation time 2041583752 ps
CPU time 31.81 seconds
Started Jul 27 05:19:53 PM PDT 24
Finished Jul 27 05:20:25 PM PDT 24
Peak memory 256988 kb
Host smart-8ab99dac-104e-4ffc-ad19-b447671c4f60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76641
3266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.766413266
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2227520219
Short name T632
Test name
Test status
Simulation time 2954387700 ps
CPU time 23.11 seconds
Started Jul 27 05:20:06 PM PDT 24
Finished Jul 27 05:20:29 PM PDT 24
Peak memory 256740 kb
Host smart-cb994d5f-e02d-4e18-80bd-154b57dba5e8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227520219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2227520219
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1124517109
Short name T261
Test name
Test status
Simulation time 80378234025 ps
CPU time 1640.63 seconds
Started Jul 27 05:20:04 PM PDT 24
Finished Jul 27 05:47:25 PM PDT 24
Peak memory 289548 kb
Host smart-a45dbadc-bd1a-40f1-84ba-f51c37044b02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124517109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1124517109
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.3698708199
Short name T494
Test name
Test status
Simulation time 5702679851 ps
CPU time 149.17 seconds
Started Jul 27 05:20:04 PM PDT 24
Finished Jul 27 05:22:33 PM PDT 24
Peak memory 256560 kb
Host smart-4c0a2ea2-ab81-4485-ab64-8ec8765dd5ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36987
08199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3698708199
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.2473540370
Short name T67
Test name
Test status
Simulation time 509311039 ps
CPU time 29.27 seconds
Started Jul 27 05:20:03 PM PDT 24
Finished Jul 27 05:20:32 PM PDT 24
Peak memory 248612 kb
Host smart-ca2f04b1-dbe8-4c49-9a55-3f7a99a78a0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24735
40370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.2473540370
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3182065838
Short name T328
Test name
Test status
Simulation time 273866798748 ps
CPU time 3329.39 seconds
Started Jul 27 05:20:06 PM PDT 24
Finished Jul 27 06:15:36 PM PDT 24
Peak memory 289668 kb
Host smart-ef531772-f0fe-4814-b5ae-e114a9e41725
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182065838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3182065838
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.939868191
Short name T231
Test name
Test status
Simulation time 42267949679 ps
CPU time 1231.66 seconds
Started Jul 27 05:20:07 PM PDT 24
Finished Jul 27 05:40:38 PM PDT 24
Peak memory 286052 kb
Host smart-b3d8be2c-0bf0-41a2-9338-a73839e8c705
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939868191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.939868191
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2873597166
Short name T472
Test name
Test status
Simulation time 406706380 ps
CPU time 25.2 seconds
Started Jul 27 05:20:07 PM PDT 24
Finished Jul 27 05:20:32 PM PDT 24
Peak memory 256360 kb
Host smart-c475b7fb-3213-46ec-ba96-a98bed1ce9fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28735
97166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2873597166
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1316685412
Short name T63
Test name
Test status
Simulation time 243477785 ps
CPU time 22.69 seconds
Started Jul 27 05:20:05 PM PDT 24
Finished Jul 27 05:20:28 PM PDT 24
Peak memory 256856 kb
Host smart-ddfdba82-5a10-44d1-9482-b6c8cb1917ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13166
85412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1316685412
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2561095320
Short name T384
Test name
Test status
Simulation time 1380620558 ps
CPU time 28.85 seconds
Started Jul 27 05:20:05 PM PDT 24
Finished Jul 27 05:20:34 PM PDT 24
Peak memory 248332 kb
Host smart-e3b930bb-d4a3-4119-b9ed-792ce7acb027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25610
95320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2561095320
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3500855443
Short name T552
Test name
Test status
Simulation time 133164922 ps
CPU time 6.47 seconds
Started Jul 27 05:20:05 PM PDT 24
Finished Jul 27 05:20:12 PM PDT 24
Peak memory 251948 kb
Host smart-eb8edef1-1f79-4421-8f2f-6c04fd789d54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35008
55443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3500855443
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1862885873
Short name T606
Test name
Test status
Simulation time 58449281302 ps
CPU time 2978.23 seconds
Started Jul 27 05:20:06 PM PDT 24
Finished Jul 27 06:09:45 PM PDT 24
Peak memory 289756 kb
Host smart-438ced75-7b3c-49b1-9cb8-31a301f49dab
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862885873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1862885873
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.1491782499
Short name T382
Test name
Test status
Simulation time 71525421108 ps
CPU time 1396.65 seconds
Started Jul 27 05:20:21 PM PDT 24
Finished Jul 27 05:43:38 PM PDT 24
Peak memory 285744 kb
Host smart-9c3e9bb6-e80a-41e0-8db1-408b3905d57c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491782499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.1491782499
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.1181629852
Short name T222
Test name
Test status
Simulation time 988119675 ps
CPU time 112.78 seconds
Started Jul 27 05:20:07 PM PDT 24
Finished Jul 27 05:22:00 PM PDT 24
Peak memory 256900 kb
Host smart-25fdc346-de74-4acb-a9fe-1b49fac3c392
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11816
29852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.1181629852
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2856484056
Short name T427
Test name
Test status
Simulation time 946938950 ps
CPU time 27.6 seconds
Started Jul 27 05:20:05 PM PDT 24
Finished Jul 27 05:20:33 PM PDT 24
Peak memory 248852 kb
Host smart-1b42fd07-bdc5-4aca-8a3c-8d71936c38f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28564
84056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2856484056
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.1114257582
Short name T318
Test name
Test status
Simulation time 45772472827 ps
CPU time 2535.29 seconds
Started Jul 27 05:20:19 PM PDT 24
Finished Jul 27 06:02:35 PM PDT 24
Peak memory 283072 kb
Host smart-c4348544-7e65-4247-87e0-94be828ee0ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114257582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1114257582
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.2479083933
Short name T366
Test name
Test status
Simulation time 19864459856 ps
CPU time 1444.54 seconds
Started Jul 27 05:20:21 PM PDT 24
Finished Jul 27 05:44:25 PM PDT 24
Peak memory 273336 kb
Host smart-2ab35d0d-4095-4672-a84e-6bb0ccb77e81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479083933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2479083933
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.1784657203
Short name T629
Test name
Test status
Simulation time 12803908407 ps
CPU time 520.41 seconds
Started Jul 27 05:20:20 PM PDT 24
Finished Jul 27 05:29:01 PM PDT 24
Peak memory 248780 kb
Host smart-227aa0b0-ef55-4691-8579-b2f0736145cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784657203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.1784657203
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.2777534964
Short name T388
Test name
Test status
Simulation time 1048192933 ps
CPU time 26.09 seconds
Started Jul 27 05:20:06 PM PDT 24
Finished Jul 27 05:20:32 PM PDT 24
Peak memory 256204 kb
Host smart-a227575a-7e6e-47bb-8658-867443cc4a3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27775
34964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.2777534964
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1487663150
Short name T360
Test name
Test status
Simulation time 363095538 ps
CPU time 28.25 seconds
Started Jul 27 05:20:05 PM PDT 24
Finished Jul 27 05:20:33 PM PDT 24
Peak memory 248236 kb
Host smart-f45d5f91-e54b-455f-967f-0685cb3c24b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14876
63150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1487663150
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.393749690
Short name T290
Test name
Test status
Simulation time 672750445 ps
CPU time 28.95 seconds
Started Jul 27 05:20:14 PM PDT 24
Finished Jul 27 05:20:43 PM PDT 24
Peak memory 248792 kb
Host smart-e2f2563f-c470-425e-a4af-d3374be26384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39374
9690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.393749690
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.3944850444
Short name T390
Test name
Test status
Simulation time 1014286455 ps
CPU time 32.96 seconds
Started Jul 27 05:20:06 PM PDT 24
Finished Jul 27 05:20:40 PM PDT 24
Peak memory 256944 kb
Host smart-800d7a39-e616-47df-89ec-210beea545f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39448
50444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.3944850444
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.1747203090
Short name T660
Test name
Test status
Simulation time 75075462449 ps
CPU time 1378.16 seconds
Started Jul 27 05:20:21 PM PDT 24
Finished Jul 27 05:43:20 PM PDT 24
Peak memory 289780 kb
Host smart-00baaa70-47be-4f28-83a8-3b9651752115
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747203090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.1747203090
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.872956839
Short name T117
Test name
Test status
Simulation time 232832005626 ps
CPU time 2619.28 seconds
Started Jul 27 05:20:22 PM PDT 24
Finished Jul 27 06:04:01 PM PDT 24
Peak memory 286364 kb
Host smart-db78540d-eb08-4788-95ba-ec0363375889
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872956839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.872956839
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2330340952
Short name T36
Test name
Test status
Simulation time 16556417854 ps
CPU time 137.07 seconds
Started Jul 27 05:20:22 PM PDT 24
Finished Jul 27 05:22:39 PM PDT 24
Peak memory 250960 kb
Host smart-da4662fa-2795-4386-8c62-7f3286cdc4f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23303
40952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2330340952
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3957359176
Short name T630
Test name
Test status
Simulation time 343948492 ps
CPU time 36.54 seconds
Started Jul 27 05:20:18 PM PDT 24
Finished Jul 27 05:20:55 PM PDT 24
Peak memory 248588 kb
Host smart-0d909bcd-ce5f-49f1-b9a5-b49cd2758b81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39573
59176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3957359176
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.464920812
Short name T685
Test name
Test status
Simulation time 10299273887 ps
CPU time 730.5 seconds
Started Jul 27 05:20:20 PM PDT 24
Finished Jul 27 05:32:31 PM PDT 24
Peak memory 273364 kb
Host smart-1b6bb29b-549f-4a36-a4dd-2af37da03e91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464920812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.464920812
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.134228774
Short name T227
Test name
Test status
Simulation time 71679934530 ps
CPU time 2115.53 seconds
Started Jul 27 05:20:21 PM PDT 24
Finished Jul 27 05:55:36 PM PDT 24
Peak memory 281628 kb
Host smart-78afdc19-06d3-4f7f-af44-f39ab5f738a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134228774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.134228774
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3766260429
Short name T301
Test name
Test status
Simulation time 16760039629 ps
CPU time 473.62 seconds
Started Jul 27 05:20:23 PM PDT 24
Finished Jul 27 05:28:17 PM PDT 24
Peak memory 247712 kb
Host smart-b4f5b30c-9caa-4a08-bbd5-ebe29cc99916
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766260429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3766260429
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.2650080200
Short name T574
Test name
Test status
Simulation time 224916349 ps
CPU time 14.74 seconds
Started Jul 27 05:20:23 PM PDT 24
Finished Jul 27 05:20:38 PM PDT 24
Peak memory 255728 kb
Host smart-8649003c-1025-4e8b-8183-144f8b1b96f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26500
80200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.2650080200
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2707846192
Short name T431
Test name
Test status
Simulation time 251068000 ps
CPU time 25.14 seconds
Started Jul 27 05:20:26 PM PDT 24
Finished Jul 27 05:20:51 PM PDT 24
Peak memory 256976 kb
Host smart-12fb5f71-c08b-45b8-a975-43f78e557c3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27078
46192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2707846192
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.2604795264
Short name T436
Test name
Test status
Simulation time 391133481 ps
CPU time 12.57 seconds
Started Jul 27 05:20:21 PM PDT 24
Finished Jul 27 05:20:34 PM PDT 24
Peak memory 248340 kb
Host smart-24266dad-37ce-4c5f-98f9-94571ac69173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26047
95264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.2604795264
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.2748892818
Short name T624
Test name
Test status
Simulation time 374625625 ps
CPU time 26.24 seconds
Started Jul 27 05:20:23 PM PDT 24
Finished Jul 27 05:20:50 PM PDT 24
Peak memory 256984 kb
Host smart-7be2c024-18ca-496c-9811-9ce5de0e3d17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27488
92818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2748892818
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.2354002266
Short name T587
Test name
Test status
Simulation time 20616791099 ps
CPU time 2224.89 seconds
Started Jul 27 05:20:22 PM PDT 24
Finished Jul 27 05:57:27 PM PDT 24
Peak memory 306044 kb
Host smart-8585d50a-9e74-4c80-ba00-4f561465d170
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354002266 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.2354002266
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.4141134748
Short name T226
Test name
Test status
Simulation time 480329418523 ps
CPU time 1723.89 seconds
Started Jul 27 05:20:39 PM PDT 24
Finished Jul 27 05:49:23 PM PDT 24
Peak memory 273440 kb
Host smart-cb813b78-cb93-4ad3-9bf5-b9e265fe3aee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141134748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.4141134748
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1022680675
Short name T396
Test name
Test status
Simulation time 6066604637 ps
CPU time 192.46 seconds
Started Jul 27 05:20:21 PM PDT 24
Finished Jul 27 05:23:34 PM PDT 24
Peak memory 256496 kb
Host smart-94eedfdc-a05d-4e6c-80fa-49f19aa386f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10226
80675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1022680675
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.3742781559
Short name T442
Test name
Test status
Simulation time 1014951967 ps
CPU time 34.75 seconds
Started Jul 27 05:20:20 PM PDT 24
Finished Jul 27 05:20:55 PM PDT 24
Peak memory 248640 kb
Host smart-17d6aead-5c9e-43c8-b205-f6c0d88fd414
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37427
81559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.3742781559
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.645218890
Short name T604
Test name
Test status
Simulation time 179804827721 ps
CPU time 2276.78 seconds
Started Jul 27 05:20:35 PM PDT 24
Finished Jul 27 05:58:32 PM PDT 24
Peak memory 288860 kb
Host smart-08a4831e-7cf0-4dba-ae15-ec48f86a7acc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645218890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.645218890
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.3703285502
Short name T589
Test name
Test status
Simulation time 35158822403 ps
CPU time 2427.39 seconds
Started Jul 27 05:20:35 PM PDT 24
Finished Jul 27 06:01:03 PM PDT 24
Peak memory 289748 kb
Host smart-18d9ae58-1804-427a-a3f4-37239516d396
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703285502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.3703285502
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.1361787254
Short name T66
Test name
Test status
Simulation time 7411780447 ps
CPU time 307.42 seconds
Started Jul 27 05:20:39 PM PDT 24
Finished Jul 27 05:25:47 PM PDT 24
Peak memory 248860 kb
Host smart-1dc1f6b9-100c-4fc8-93b7-0b3e5a933dea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361787254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1361787254
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2088729345
Short name T553
Test name
Test status
Simulation time 7967683273 ps
CPU time 69.52 seconds
Started Jul 27 05:20:22 PM PDT 24
Finished Jul 27 05:21:31 PM PDT 24
Peak memory 257068 kb
Host smart-c297ac7c-cfca-4b6c-9d45-25365ab3110b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20887
29345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2088729345
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1490380747
Short name T2
Test name
Test status
Simulation time 2957160999 ps
CPU time 40.44 seconds
Started Jul 27 05:20:22 PM PDT 24
Finished Jul 27 05:21:03 PM PDT 24
Peak memory 248472 kb
Host smart-4efd6e53-8649-4c6a-ba43-dd22df02f2ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14903
80747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1490380747
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.636664615
Short name T676
Test name
Test status
Simulation time 152300506 ps
CPU time 10.54 seconds
Started Jul 27 05:20:20 PM PDT 24
Finished Jul 27 05:20:30 PM PDT 24
Peak memory 254932 kb
Host smart-bd495866-981e-4087-861b-d9b28cc3e885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63666
4615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.636664615
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.4076962710
Short name T434
Test name
Test status
Simulation time 48348029631 ps
CPU time 1222.99 seconds
Started Jul 27 05:20:34 PM PDT 24
Finished Jul 27 05:40:57 PM PDT 24
Peak memory 289232 kb
Host smart-5633250a-35a2-49ab-af47-d1aeb4628148
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4076962710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.4076962710
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.3478689458
Short name T65
Test name
Test status
Simulation time 66172965241 ps
CPU time 3324.69 seconds
Started Jul 27 05:20:34 PM PDT 24
Finished Jul 27 06:16:00 PM PDT 24
Peak memory 337844 kb
Host smart-b6ca5541-3fe0-45f6-aa91-2cc7c860cc7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478689458 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.3478689458
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2936640737
Short name T476
Test name
Test status
Simulation time 28659365116 ps
CPU time 2050.65 seconds
Started Jul 27 05:20:31 PM PDT 24
Finished Jul 27 05:54:42 PM PDT 24
Peak memory 281620 kb
Host smart-0dc56ac3-661a-46a1-91b9-468e2f1ee8ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936640737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2936640737
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.2013640287
Short name T357
Test name
Test status
Simulation time 33218282097 ps
CPU time 295.84 seconds
Started Jul 27 05:20:32 PM PDT 24
Finished Jul 27 05:25:28 PM PDT 24
Peak memory 256384 kb
Host smart-027805b0-4262-4228-bc48-24385d1ebe71
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20136
40287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.2013640287
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.585103396
Short name T594
Test name
Test status
Simulation time 807236120 ps
CPU time 47.45 seconds
Started Jul 27 05:20:33 PM PDT 24
Finished Jul 27 05:21:21 PM PDT 24
Peak memory 248356 kb
Host smart-cf96bdf7-e132-45ac-a346-24413d8031d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58510
3396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.585103396
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1392263655
Short name T692
Test name
Test status
Simulation time 29358807011 ps
CPU time 1774.41 seconds
Started Jul 27 05:20:34 PM PDT 24
Finished Jul 27 05:50:09 PM PDT 24
Peak memory 284536 kb
Host smart-4e99a571-c8d7-4a7b-8d07-7289d72dcc16
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392263655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1392263655
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1209623565
Short name T64
Test name
Test status
Simulation time 10644330280 ps
CPU time 1011.12 seconds
Started Jul 27 05:20:39 PM PDT 24
Finished Jul 27 05:37:30 PM PDT 24
Peak memory 285180 kb
Host smart-fc21cc5c-9544-4dbf-8706-4a363b3a2783
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209623565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1209623565
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1400295182
Short name T56
Test name
Test status
Simulation time 295936636 ps
CPU time 32.31 seconds
Started Jul 27 05:20:33 PM PDT 24
Finished Jul 27 05:21:06 PM PDT 24
Peak memory 248768 kb
Host smart-e7da7344-d1c8-447a-9fd6-999a08049021
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14002
95182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1400295182
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.357830462
Short name T99
Test name
Test status
Simulation time 334432808 ps
CPU time 23.52 seconds
Started Jul 27 05:20:33 PM PDT 24
Finished Jul 27 05:20:57 PM PDT 24
Peak memory 248316 kb
Host smart-8bf2a3f0-bfff-41f1-ac33-3a0ad26cce56
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35783
0462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.357830462
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.1977499578
Short name T498
Test name
Test status
Simulation time 2194309114 ps
CPU time 35.89 seconds
Started Jul 27 05:20:34 PM PDT 24
Finished Jul 27 05:21:10 PM PDT 24
Peak memory 257076 kb
Host smart-00b37538-79dd-4259-a855-a750b6d18dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19774
99578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.1977499578
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.2362433547
Short name T48
Test name
Test status
Simulation time 54326372490 ps
CPU time 1295.1 seconds
Started Jul 27 05:20:34 PM PDT 24
Finished Jul 27 05:42:09 PM PDT 24
Peak memory 289792 kb
Host smart-f1fb9c98-3256-4200-9291-21f0f1193a34
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362433547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.2362433547
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.1899808726
Short name T585
Test name
Test status
Simulation time 61086014396 ps
CPU time 1004.24 seconds
Started Jul 27 05:20:33 PM PDT 24
Finished Jul 27 05:37:17 PM PDT 24
Peak memory 281688 kb
Host smart-faca0f22-4a5c-4eb0-be9c-af9947ef569e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899808726 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.1899808726
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.418316782
Short name T112
Test name
Test status
Simulation time 13155702266 ps
CPU time 1068.08 seconds
Started Jul 27 05:20:33 PM PDT 24
Finished Jul 27 05:38:21 PM PDT 24
Peak memory 273176 kb
Host smart-453aba8e-6478-4917-98d0-705bcaee4200
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418316782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.418316782
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1295441641
Short name T565
Test name
Test status
Simulation time 4759737806 ps
CPU time 74.58 seconds
Started Jul 27 05:20:33 PM PDT 24
Finished Jul 27 05:21:48 PM PDT 24
Peak memory 256508 kb
Host smart-67f18170-8b25-4018-83d0-a7d292aa2a7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12954
41641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1295441641
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.4206624530
Short name T473
Test name
Test status
Simulation time 851145987 ps
CPU time 49.19 seconds
Started Jul 27 05:20:39 PM PDT 24
Finished Jul 27 05:21:29 PM PDT 24
Peak memory 248328 kb
Host smart-910b92b6-4340-45a0-80f6-0753762be871
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42066
24530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.4206624530
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.599933473
Short name T27
Test name
Test status
Simulation time 14822176285 ps
CPU time 1458.67 seconds
Started Jul 27 05:20:39 PM PDT 24
Finished Jul 27 05:44:58 PM PDT 24
Peak memory 289580 kb
Host smart-48886bd1-21b9-495c-a13c-af90ade963db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599933473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.599933473
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.3960237704
Short name T182
Test name
Test status
Simulation time 5445065219 ps
CPU time 124.47 seconds
Started Jul 27 05:20:36 PM PDT 24
Finished Jul 27 05:22:40 PM PDT 24
Peak memory 248720 kb
Host smart-ec130f90-20ca-4816-aec2-c9d16444fe2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960237704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.3960237704
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.2651587401
Short name T464
Test name
Test status
Simulation time 90493872 ps
CPU time 8.82 seconds
Started Jul 27 05:20:33 PM PDT 24
Finished Jul 27 05:20:42 PM PDT 24
Peak memory 249088 kb
Host smart-b378967d-a743-4806-b593-4836218f095c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26515
87401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.2651587401
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.4018411082
Short name T385
Test name
Test status
Simulation time 3735522115 ps
CPU time 62.56 seconds
Started Jul 27 05:20:34 PM PDT 24
Finished Jul 27 05:21:36 PM PDT 24
Peak memory 248604 kb
Host smart-a4c18d5f-15da-4492-a3ab-8d527f1425d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40184
11082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.4018411082
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2740446983
Short name T452
Test name
Test status
Simulation time 352046479 ps
CPU time 14.71 seconds
Started Jul 27 05:20:34 PM PDT 24
Finished Jul 27 05:20:48 PM PDT 24
Peak memory 248792 kb
Host smart-8d1c910d-87bf-4bfa-826c-19a48ef678c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27404
46983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2740446983
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.1582104592
Short name T560
Test name
Test status
Simulation time 668645736 ps
CPU time 37.4 seconds
Started Jul 27 05:20:35 PM PDT 24
Finished Jul 27 05:21:13 PM PDT 24
Peak memory 256496 kb
Host smart-b68adac4-f16b-412d-b105-9685278606f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15821
04592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.1582104592
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2282119772
Short name T268
Test name
Test status
Simulation time 68394843582 ps
CPU time 2252.97 seconds
Started Jul 27 05:20:34 PM PDT 24
Finished Jul 27 05:58:07 PM PDT 24
Peak memory 289584 kb
Host smart-d60c26a5-8890-4d25-bfcd-194e8b613f1c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282119772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2282119772
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1624662039
Short name T690
Test name
Test status
Simulation time 35851615360 ps
CPU time 2802.66 seconds
Started Jul 27 05:20:36 PM PDT 24
Finished Jul 27 06:07:19 PM PDT 24
Peak memory 314604 kb
Host smart-d47dcaaf-1112-4ebf-b1cd-7a01efd8e398
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624662039 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1624662039
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.3927244614
Short name T206
Test name
Test status
Simulation time 37633951 ps
CPU time 3.49 seconds
Started Jul 27 05:18:17 PM PDT 24
Finished Jul 27 05:18:21 PM PDT 24
Peak memory 249072 kb
Host smart-b707b54b-f8d2-4814-a03d-26f32eca004f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3927244614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3927244614
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.4060638281
Short name T546
Test name
Test status
Simulation time 1180846863 ps
CPU time 16.15 seconds
Started Jul 27 05:18:18 PM PDT 24
Finished Jul 27 05:18:35 PM PDT 24
Peak memory 248832 kb
Host smart-c89a06d7-8e47-4e87-988e-a43359a6590a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4060638281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.4060638281
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.2236517393
Short name T497
Test name
Test status
Simulation time 15674347668 ps
CPU time 84.11 seconds
Started Jul 27 05:18:19 PM PDT 24
Finished Jul 27 05:19:44 PM PDT 24
Peak memory 256976 kb
Host smart-bc8a16f0-293b-42db-a738-57359e7bda77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22365
17393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.2236517393
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3186010423
Short name T634
Test name
Test status
Simulation time 191771822 ps
CPU time 12.1 seconds
Started Jul 27 05:18:18 PM PDT 24
Finished Jul 27 05:18:30 PM PDT 24
Peak memory 248228 kb
Host smart-75f2bc08-13b8-4a14-9655-8e95ba62fa27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31860
10423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3186010423
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.3019428295
Short name T514
Test name
Test status
Simulation time 7156604167 ps
CPU time 672.81 seconds
Started Jul 27 05:18:19 PM PDT 24
Finished Jul 27 05:29:32 PM PDT 24
Peak memory 272768 kb
Host smart-5b43a9cf-422c-4a01-a01d-e0818079b986
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019428295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3019428295
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.2868404486
Short name T501
Test name
Test status
Simulation time 118146404033 ps
CPU time 3086.7 seconds
Started Jul 27 05:18:19 PM PDT 24
Finished Jul 27 06:09:46 PM PDT 24
Peak memory 289792 kb
Host smart-0b1e784e-a199-4e99-ac0b-75f04dc4875d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868404486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2868404486
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2923440210
Short name T698
Test name
Test status
Simulation time 39356832080 ps
CPU time 430.56 seconds
Started Jul 27 05:18:18 PM PDT 24
Finished Jul 27 05:25:29 PM PDT 24
Peak memory 248736 kb
Host smart-a672dab6-abec-499d-8e6d-496d3b124c55
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923440210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2923440210
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.3903948196
Short name T412
Test name
Test status
Simulation time 705490986 ps
CPU time 20.66 seconds
Started Jul 27 05:18:18 PM PDT 24
Finished Jul 27 05:18:39 PM PDT 24
Peak memory 248736 kb
Host smart-c82dbe5e-b456-4185-9aee-95bf5a673899
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39039
48196 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.3903948196
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.111733846
Short name T395
Test name
Test status
Simulation time 277831874 ps
CPU time 23.32 seconds
Started Jul 27 05:18:19 PM PDT 24
Finished Jul 27 05:18:43 PM PDT 24
Peak memory 248784 kb
Host smart-f70fb5b3-b06e-440a-b641-618c8b0dcff6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11173
3846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.111733846
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1212551996
Short name T34
Test name
Test status
Simulation time 886187073 ps
CPU time 24.63 seconds
Started Jul 27 05:18:19 PM PDT 24
Finished Jul 27 05:18:44 PM PDT 24
Peak memory 279412 kb
Host smart-25431f4d-f973-42bf-a4fd-682b5e585f3d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1212551996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1212551996
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.2185958343
Short name T664
Test name
Test status
Simulation time 761376512 ps
CPU time 15.95 seconds
Started Jul 27 05:18:19 PM PDT 24
Finished Jul 27 05:18:36 PM PDT 24
Peak memory 248736 kb
Host smart-4653d3e3-4447-4cc8-b9cb-479a3fd9dbd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21859
58343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.2185958343
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3693215027
Short name T14
Test name
Test status
Simulation time 56809795 ps
CPU time 3.04 seconds
Started Jul 27 05:18:16 PM PDT 24
Finished Jul 27 05:18:19 PM PDT 24
Peak memory 248760 kb
Host smart-6048dbba-e1ef-4118-a68a-6c1b234ced79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36932
15027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3693215027
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.4028424473
Short name T270
Test name
Test status
Simulation time 230025816162 ps
CPU time 3738.54 seconds
Started Jul 27 05:18:19 PM PDT 24
Finished Jul 27 06:20:38 PM PDT 24
Peak memory 305836 kb
Host smart-48011503-ab13-4fd3-a940-58ef81e68110
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028424473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.4028424473
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.1404340153
Short name T28
Test name
Test status
Simulation time 33263483961 ps
CPU time 1932.15 seconds
Started Jul 27 05:18:21 PM PDT 24
Finished Jul 27 05:50:33 PM PDT 24
Peak memory 306048 kb
Host smart-e8ea8961-9744-4cdb-9ed4-8ebd806e7904
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1404340153 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.1404340153
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.4218740167
Short name T637
Test name
Test status
Simulation time 11160068156 ps
CPU time 1143.58 seconds
Started Jul 27 05:20:46 PM PDT 24
Finished Jul 27 05:39:50 PM PDT 24
Peak memory 284964 kb
Host smart-5428d5f2-8f92-4d18-b623-d344e2991561
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218740167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.4218740167
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3011568152
Short name T358
Test name
Test status
Simulation time 897717034 ps
CPU time 74.9 seconds
Started Jul 27 05:20:45 PM PDT 24
Finished Jul 27 05:22:00 PM PDT 24
Peak memory 256280 kb
Host smart-2c6df18b-5280-4c93-be57-a6efd3d6f7cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30115
68152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3011568152
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.2941704853
Short name T352
Test name
Test status
Simulation time 3211782257 ps
CPU time 50.56 seconds
Started Jul 27 05:20:46 PM PDT 24
Finished Jul 27 05:21:37 PM PDT 24
Peak memory 248816 kb
Host smart-1be49837-5ecc-4d5b-828c-87680fcf3c16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29417
04853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2941704853
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1032528832
Short name T612
Test name
Test status
Simulation time 13328711969 ps
CPU time 1237.65 seconds
Started Jul 27 05:20:46 PM PDT 24
Finished Jul 27 05:41:24 PM PDT 24
Peak memory 281652 kb
Host smart-ce540380-af5e-4b58-a340-c5324a4aabfc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032528832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1032528832
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.140335599
Short name T102
Test name
Test status
Simulation time 142103888718 ps
CPU time 2148.91 seconds
Started Jul 27 05:20:47 PM PDT 24
Finished Jul 27 05:56:36 PM PDT 24
Peak memory 281588 kb
Host smart-eb417919-3381-4deb-b23a-8da2a5ce36f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140335599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.140335599
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.1995257652
Short name T571
Test name
Test status
Simulation time 22522184674 ps
CPU time 229.78 seconds
Started Jul 27 05:20:48 PM PDT 24
Finished Jul 27 05:24:38 PM PDT 24
Peak memory 248864 kb
Host smart-3ddc753c-d597-4de8-a769-d43a5cd99dee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995257652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1995257652
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.801066306
Short name T407
Test name
Test status
Simulation time 78085712 ps
CPU time 10.27 seconds
Started Jul 27 05:20:43 PM PDT 24
Finished Jul 27 05:20:54 PM PDT 24
Peak memory 255344 kb
Host smart-5164949f-d0f1-4575-94b9-78897ee81deb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80106
6306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.801066306
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1596557046
Short name T73
Test name
Test status
Simulation time 2302992031 ps
CPU time 43.1 seconds
Started Jul 27 05:20:46 PM PDT 24
Finished Jul 27 05:21:29 PM PDT 24
Peak memory 248848 kb
Host smart-2d093c3e-5616-4eab-8dc2-e1bcf43bdfe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15965
57046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1596557046
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.219189533
Short name T591
Test name
Test status
Simulation time 2869664318 ps
CPU time 41.87 seconds
Started Jul 27 05:20:46 PM PDT 24
Finished Jul 27 05:21:28 PM PDT 24
Peak memory 248824 kb
Host smart-bc6e6a45-fae9-447d-8666-d5214ffc0b5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21918
9533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.219189533
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2366609888
Short name T89
Test name
Test status
Simulation time 2757624290 ps
CPU time 45.79 seconds
Started Jul 27 05:20:47 PM PDT 24
Finished Jul 27 05:21:33 PM PDT 24
Peak memory 256912 kb
Host smart-772674e9-0526-4e20-b942-7c338d8992c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23666
09888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2366609888
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2343977918
Short name T114
Test name
Test status
Simulation time 32036725549 ps
CPU time 1692.74 seconds
Started Jul 27 05:20:46 PM PDT 24
Finished Jul 27 05:48:59 PM PDT 24
Peak memory 288728 kb
Host smart-2c4f5053-205b-4716-b1ac-ea9068bb2e46
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343977918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2343977918
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.1597392726
Short name T631
Test name
Test status
Simulation time 72058395614 ps
CPU time 6127.68 seconds
Started Jul 27 05:20:46 PM PDT 24
Finished Jul 27 07:02:54 PM PDT 24
Peak memory 355484 kb
Host smart-05ec0a70-b87f-4d97-8f66-fbe55d7a7cd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597392726 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.1597392726
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.452786379
Short name T378
Test name
Test status
Simulation time 8347440552 ps
CPU time 239.95 seconds
Started Jul 27 05:20:46 PM PDT 24
Finished Jul 27 05:24:47 PM PDT 24
Peak memory 256208 kb
Host smart-fa04d85e-da0d-4f30-93cf-65a57602ad0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45278
6379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.452786379
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2754401593
Short name T389
Test name
Test status
Simulation time 842933707 ps
CPU time 33.44 seconds
Started Jul 27 05:20:47 PM PDT 24
Finished Jul 27 05:21:20 PM PDT 24
Peak memory 248252 kb
Host smart-edb8cd1b-32e0-4bee-b3db-3f285dbd7481
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27544
01593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2754401593
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.465921891
Short name T322
Test name
Test status
Simulation time 15201198161 ps
CPU time 1323.7 seconds
Started Jul 27 05:20:47 PM PDT 24
Finished Jul 27 05:42:51 PM PDT 24
Peak memory 288604 kb
Host smart-cb46b3a3-fc1d-4589-a206-6e0fd7f507d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=465921891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.465921891
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3743317235
Short name T601
Test name
Test status
Simulation time 25951210013 ps
CPU time 1418.63 seconds
Started Jul 27 05:20:48 PM PDT 24
Finished Jul 27 05:44:26 PM PDT 24
Peak memory 289436 kb
Host smart-0f03d91b-fba0-4adf-b71b-4925b3403cf5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743317235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3743317235
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.956457764
Short name T101
Test name
Test status
Simulation time 74785209972 ps
CPU time 332.42 seconds
Started Jul 27 05:20:49 PM PDT 24
Finished Jul 27 05:26:21 PM PDT 24
Peak memory 248828 kb
Host smart-ae31e207-a722-48d2-b4d8-66a36f16c303
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956457764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.956457764
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.310983916
Short name T623
Test name
Test status
Simulation time 535784096 ps
CPU time 37.62 seconds
Started Jul 27 05:20:46 PM PDT 24
Finished Jul 27 05:21:24 PM PDT 24
Peak memory 248760 kb
Host smart-fc5801b0-2b8e-4306-bc63-3ad7081b6e9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31098
3916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.310983916
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.1508028935
Short name T510
Test name
Test status
Simulation time 391934404 ps
CPU time 16.19 seconds
Started Jul 27 05:20:46 PM PDT 24
Finished Jul 27 05:21:03 PM PDT 24
Peak memory 256872 kb
Host smart-a50072d1-753e-498b-9fac-f69fe28b4c86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15080
28935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1508028935
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.3913437132
Short name T298
Test name
Test status
Simulation time 87848541 ps
CPU time 9.94 seconds
Started Jul 27 05:20:46 PM PDT 24
Finished Jul 27 05:20:56 PM PDT 24
Peak memory 248000 kb
Host smart-ac87a530-37c4-41b9-92dc-a8cd9d1609a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39134
37132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.3913437132
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.349658231
Short name T686
Test name
Test status
Simulation time 91340291 ps
CPU time 4.18 seconds
Started Jul 27 05:20:48 PM PDT 24
Finished Jul 27 05:20:52 PM PDT 24
Peak memory 250672 kb
Host smart-54c5839c-9da5-459b-b3fd-4e9ea893d680
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34965
8231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.349658231
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2234772230
Short name T650
Test name
Test status
Simulation time 256394335223 ps
CPU time 2763.24 seconds
Started Jul 27 05:20:47 PM PDT 24
Finished Jul 27 06:06:50 PM PDT 24
Peak memory 288656 kb
Host smart-4464547e-d132-47fa-b278-3ac339e3bfb0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234772230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2234772230
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.3040350895
Short name T55
Test name
Test status
Simulation time 84090668950 ps
CPU time 9096.5 seconds
Started Jul 27 05:20:48 PM PDT 24
Finished Jul 27 07:52:26 PM PDT 24
Peak memory 387068 kb
Host smart-e5c734fe-3fb1-460d-80c4-ce5b50cd4f1e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040350895 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.3040350895
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.1449834585
Short name T437
Test name
Test status
Simulation time 76663776248 ps
CPU time 1546.29 seconds
Started Jul 27 05:20:48 PM PDT 24
Finished Jul 27 05:46:35 PM PDT 24
Peak memory 289048 kb
Host smart-d67b0c19-f271-4229-be96-8ce9f55f2b83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449834585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.1449834585
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1108856127
Short name T492
Test name
Test status
Simulation time 2432741283 ps
CPU time 48.47 seconds
Started Jul 27 05:20:50 PM PDT 24
Finished Jul 27 05:21:39 PM PDT 24
Peak memory 256584 kb
Host smart-a729b258-f032-4305-9575-5c49852a9046
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11088
56127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1108856127
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3583189833
Short name T392
Test name
Test status
Simulation time 1013602210 ps
CPU time 26.34 seconds
Started Jul 27 05:20:49 PM PDT 24
Finished Jul 27 05:21:15 PM PDT 24
Peak memory 248272 kb
Host smart-de6fdd01-cb1a-4ecd-ab6e-989ff79e4615
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35831
89833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3583189833
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.1084305027
Short name T367
Test name
Test status
Simulation time 210772598027 ps
CPU time 2660.84 seconds
Started Jul 27 05:20:59 PM PDT 24
Finished Jul 27 06:05:21 PM PDT 24
Peak memory 289768 kb
Host smart-823fe56e-4530-4bd0-934e-34ab647ca0ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084305027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.1084305027
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.2645885228
Short name T595
Test name
Test status
Simulation time 676275193 ps
CPU time 43.06 seconds
Started Jul 27 05:20:47 PM PDT 24
Finished Jul 27 05:21:31 PM PDT 24
Peak memory 256312 kb
Host smart-e9b16961-8817-4dae-ac2d-3b5ca29bfc91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26458
85228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2645885228
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.394839911
Short name T459
Test name
Test status
Simulation time 326050247 ps
CPU time 14.06 seconds
Started Jul 27 05:20:49 PM PDT 24
Finished Jul 27 05:21:03 PM PDT 24
Peak memory 253776 kb
Host smart-4a46b7ff-5821-4d1f-845c-c2bdc7853fcc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39483
9911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.394839911
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.776188697
Short name T640
Test name
Test status
Simulation time 661546925 ps
CPU time 56.92 seconds
Started Jul 27 05:20:50 PM PDT 24
Finished Jul 27 05:21:47 PM PDT 24
Peak memory 256488 kb
Host smart-e03e58da-a503-48fa-bf4c-5d0298006293
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77618
8697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.776188697
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.932096813
Short name T517
Test name
Test status
Simulation time 598331775 ps
CPU time 21.03 seconds
Started Jul 27 05:20:50 PM PDT 24
Finished Jul 27 05:21:11 PM PDT 24
Peak memory 256008 kb
Host smart-7d63b03f-96a6-456a-82fd-9f8991c146de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93209
6813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.932096813
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.3448957500
Short name T59
Test name
Test status
Simulation time 44656737432 ps
CPU time 4682.08 seconds
Started Jul 27 05:20:58 PM PDT 24
Finished Jul 27 06:39:00 PM PDT 24
Peak memory 322244 kb
Host smart-19435a04-c80f-44ba-be26-29f3d4c4ac44
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3448957500 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.3448957500
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1762773231
Short name T688
Test name
Test status
Simulation time 613705832778 ps
CPU time 2622.71 seconds
Started Jul 27 05:20:57 PM PDT 24
Finished Jul 27 06:04:40 PM PDT 24
Peak memory 289624 kb
Host smart-07885917-2ba7-4bf7-bf1b-541375d8baf9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762773231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1762773231
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.365716613
Short name T628
Test name
Test status
Simulation time 26305111035 ps
CPU time 195.54 seconds
Started Jul 27 05:20:57 PM PDT 24
Finished Jul 27 05:24:12 PM PDT 24
Peak memory 256232 kb
Host smart-1a92852e-3276-47fc-af8d-529b64f9ccff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36571
6613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.365716613
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.1868553909
Short name T643
Test name
Test status
Simulation time 2020838822 ps
CPU time 29.34 seconds
Started Jul 27 05:20:58 PM PDT 24
Finished Jul 27 05:21:28 PM PDT 24
Peak memory 248416 kb
Host smart-ff783fff-ebc1-4960-b7c9-b5993efce8b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18685
53909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1868553909
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1416484563
Short name T596
Test name
Test status
Simulation time 28193407909 ps
CPU time 1388.15 seconds
Started Jul 27 05:20:57 PM PDT 24
Finished Jul 27 05:44:06 PM PDT 24
Peak memory 289756 kb
Host smart-7ee827d4-aabb-4b94-9fef-d3c04b9bf33a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416484563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1416484563
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.772743086
Short name T314
Test name
Test status
Simulation time 8213333375 ps
CPU time 341.51 seconds
Started Jul 27 05:21:00 PM PDT 24
Finished Jul 27 05:26:42 PM PDT 24
Peak memory 248892 kb
Host smart-b4112806-1e6c-4e9b-9d27-795714d08596
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772743086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.772743086
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.240745755
Short name T252
Test name
Test status
Simulation time 730002420 ps
CPU time 37.77 seconds
Started Jul 27 05:20:55 PM PDT 24
Finished Jul 27 05:21:32 PM PDT 24
Peak memory 256968 kb
Host smart-ce2abb12-d48f-4905-9583-f417dcc293dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24074
5755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.240745755
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.3883950844
Short name T466
Test name
Test status
Simulation time 171852286 ps
CPU time 16.59 seconds
Started Jul 27 05:21:00 PM PDT 24
Finished Jul 27 05:21:17 PM PDT 24
Peak memory 256404 kb
Host smart-0a3c0ffd-9190-4b28-b0c2-4594cefc4d39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38839
50844 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.3883950844
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3083694833
Short name T53
Test name
Test status
Simulation time 3162504809 ps
CPU time 46.9 seconds
Started Jul 27 05:20:56 PM PDT 24
Finished Jul 27 05:21:43 PM PDT 24
Peak memory 248888 kb
Host smart-96d71598-b724-440a-a2f1-24393babfee5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30836
94833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3083694833
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.440178050
Short name T554
Test name
Test status
Simulation time 540329561 ps
CPU time 32.93 seconds
Started Jul 27 05:20:56 PM PDT 24
Finished Jul 27 05:21:29 PM PDT 24
Peak memory 256328 kb
Host smart-46be7927-d08f-49d3-8d82-9333d35d6a5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44017
8050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.440178050
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.963146829
Short name T29
Test name
Test status
Simulation time 31059510003 ps
CPU time 1812.14 seconds
Started Jul 27 05:20:59 PM PDT 24
Finished Jul 27 05:51:12 PM PDT 24
Peak memory 284160 kb
Host smart-596af281-d80f-45bf-a612-5d430bc601d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963146829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.963146829
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.2386544276
Short name T558
Test name
Test status
Simulation time 10221589702 ps
CPU time 199.15 seconds
Started Jul 27 05:20:56 PM PDT 24
Finished Jul 27 05:24:15 PM PDT 24
Peak memory 257052 kb
Host smart-8a3319a9-ceae-450c-89cb-c7c7b593f9c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23865
44276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2386544276
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2931596135
Short name T588
Test name
Test status
Simulation time 2982486847 ps
CPU time 40.14 seconds
Started Jul 27 05:20:57 PM PDT 24
Finished Jul 27 05:21:38 PM PDT 24
Peak memory 257084 kb
Host smart-1fb3555e-7f50-4794-8bc2-c02c679720b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29315
96135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2931596135
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.1622822978
Short name T361
Test name
Test status
Simulation time 42603221459 ps
CPU time 1273.9 seconds
Started Jul 27 05:21:09 PM PDT 24
Finished Jul 27 05:42:24 PM PDT 24
Peak memory 266260 kb
Host smart-95593185-af00-4b79-b48e-ec3d9d903e94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622822978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1622822978
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.3274737409
Short name T512
Test name
Test status
Simulation time 24343234946 ps
CPU time 406.37 seconds
Started Jul 27 05:20:59 PM PDT 24
Finished Jul 27 05:27:45 PM PDT 24
Peak memory 255332 kb
Host smart-bcae3677-1caf-4d56-91ec-42ad2b4f2f59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274737409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.3274737409
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3405559608
Short name T534
Test name
Test status
Simulation time 510869306 ps
CPU time 27.17 seconds
Started Jul 27 05:20:57 PM PDT 24
Finished Jul 27 05:21:24 PM PDT 24
Peak memory 256912 kb
Host smart-ee534bc4-2e16-404d-94b0-414a080b93b2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34055
59608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3405559608
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2114850418
Short name T100
Test name
Test status
Simulation time 132263614 ps
CPU time 9.24 seconds
Started Jul 27 05:20:58 PM PDT 24
Finished Jul 27 05:21:07 PM PDT 24
Peak memory 250912 kb
Host smart-c9275cda-53d4-4473-9835-82d62ff434c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21148
50418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2114850418
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.3805550076
Short name T287
Test name
Test status
Simulation time 678986935 ps
CPU time 30.45 seconds
Started Jul 27 05:20:56 PM PDT 24
Finished Jul 27 05:21:26 PM PDT 24
Peak memory 248444 kb
Host smart-39a671fd-643e-4097-8041-deedbd6be9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38055
50076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3805550076
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.256554756
Short name T370
Test name
Test status
Simulation time 1233250160 ps
CPU time 16.53 seconds
Started Jul 27 05:20:57 PM PDT 24
Finished Jul 27 05:21:14 PM PDT 24
Peak memory 256900 kb
Host smart-9e4fb5b4-c36e-41db-956d-987204157e7b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25655
4756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.256554756
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1101578703
Short name T377
Test name
Test status
Simulation time 23636808212 ps
CPU time 1252.98 seconds
Started Jul 27 05:21:09 PM PDT 24
Finished Jul 27 05:42:02 PM PDT 24
Peak memory 289688 kb
Host smart-db9f28b9-7394-4af8-b85a-ff00845c4df9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101578703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1101578703
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.2522454644
Short name T280
Test name
Test status
Simulation time 75546661261 ps
CPU time 1926.96 seconds
Started Jul 27 05:21:16 PM PDT 24
Finished Jul 27 05:53:23 PM PDT 24
Peak memory 299680 kb
Host smart-372a46e9-c7cd-49ab-9504-6fed7a3fd7ea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522454644 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.2522454644
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2017561696
Short name T453
Test name
Test status
Simulation time 62883804377 ps
CPU time 1961.99 seconds
Started Jul 27 05:21:08 PM PDT 24
Finished Jul 27 05:53:51 PM PDT 24
Peak memory 283168 kb
Host smart-722d0c52-10b5-44e1-b254-5f15808369ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017561696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2017561696
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1242708120
Short name T527
Test name
Test status
Simulation time 1654281191 ps
CPU time 12.31 seconds
Started Jul 27 05:21:17 PM PDT 24
Finished Jul 27 05:21:29 PM PDT 24
Peak memory 256348 kb
Host smart-438f7b41-388d-48e1-81d3-bc98795af858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12427
08120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1242708120
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.537683366
Short name T40
Test name
Test status
Simulation time 1219369641 ps
CPU time 22.94 seconds
Started Jul 27 05:21:08 PM PDT 24
Finished Jul 27 05:21:31 PM PDT 24
Peak memory 248340 kb
Host smart-daa58756-02f3-4d81-9acc-a419c15dc88c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53768
3366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.537683366
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.937661441
Short name T186
Test name
Test status
Simulation time 143316599313 ps
CPU time 2047.87 seconds
Started Jul 27 05:21:13 PM PDT 24
Finished Jul 27 05:55:21 PM PDT 24
Peak memory 289556 kb
Host smart-6a0eab2b-c3c4-4992-a610-0a1c58f7b0a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937661441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.937661441
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.3714547082
Short name T309
Test name
Test status
Simulation time 94730348348 ps
CPU time 381.95 seconds
Started Jul 27 05:21:09 PM PDT 24
Finished Jul 27 05:27:31 PM PDT 24
Peak memory 248768 kb
Host smart-0c407f83-86c6-4081-a008-4da00714db11
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714547082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3714547082
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.2909604205
Short name T500
Test name
Test status
Simulation time 676381265 ps
CPU time 37.96 seconds
Started Jul 27 05:21:10 PM PDT 24
Finished Jul 27 05:21:48 PM PDT 24
Peak memory 248804 kb
Host smart-4b0277c5-a62f-4a29-853a-83761a4bbe27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29096
04205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2909604205
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.3555673098
Short name T696
Test name
Test status
Simulation time 482886408 ps
CPU time 32.51 seconds
Started Jul 27 05:21:09 PM PDT 24
Finished Jul 27 05:21:41 PM PDT 24
Peak memory 256596 kb
Host smart-6dfefd45-6a9a-415a-93df-7fa2381ee248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35556
73098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.3555673098
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.430728763
Short name T281
Test name
Test status
Simulation time 2513518357 ps
CPU time 17.87 seconds
Started Jul 27 05:21:11 PM PDT 24
Finished Jul 27 05:21:29 PM PDT 24
Peak memory 248736 kb
Host smart-07ba4526-0448-49f9-bcc1-fb1e2b33dae6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43072
8763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.430728763
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2356960199
Short name T355
Test name
Test status
Simulation time 795743805 ps
CPU time 42.56 seconds
Started Jul 27 05:21:16 PM PDT 24
Finished Jul 27 05:21:59 PM PDT 24
Peak memory 256152 kb
Host smart-535af0e9-eccb-41df-8315-cadbf3e5a0a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23569
60199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2356960199
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.2430102526
Short name T611
Test name
Test status
Simulation time 104096459981 ps
CPU time 1665.56 seconds
Started Jul 27 05:21:08 PM PDT 24
Finished Jul 27 05:48:54 PM PDT 24
Peak memory 273304 kb
Host smart-078ef616-42d3-4282-8ec5-5e390808f959
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430102526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.2430102526
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1217560379
Short name T255
Test name
Test status
Simulation time 2633583080 ps
CPU time 178.98 seconds
Started Jul 27 05:21:08 PM PDT 24
Finished Jul 27 05:24:07 PM PDT 24
Peak memory 256596 kb
Host smart-baba4d8b-fa52-4618-a4ec-41889b9e5505
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12175
60379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1217560379
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.3297711068
Short name T691
Test name
Test status
Simulation time 778807396 ps
CPU time 20.75 seconds
Started Jul 27 05:21:09 PM PDT 24
Finished Jul 27 05:21:30 PM PDT 24
Peak memory 256520 kb
Host smart-f5e0cf36-f0e6-45b9-bc9b-4e0b1d280a86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32977
11068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3297711068
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1216139
Short name T484
Test name
Test status
Simulation time 21285885044 ps
CPU time 1621.03 seconds
Started Jul 27 05:21:10 PM PDT 24
Finished Jul 27 05:48:12 PM PDT 24
Peak memory 289132 kb
Host smart-619c3e26-6c46-46f9-9598-97f3d18e0689
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1216139
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.3006163993
Short name T506
Test name
Test status
Simulation time 84506353947 ps
CPU time 2479.81 seconds
Started Jul 27 05:21:08 PM PDT 24
Finished Jul 27 06:02:28 PM PDT 24
Peak memory 289712 kb
Host smart-cfd9a0e6-3af6-4b76-942b-3fd052ef0db5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006163993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3006163993
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.1684297115
Short name T223
Test name
Test status
Simulation time 27516094758 ps
CPU time 304.41 seconds
Started Jul 27 05:21:11 PM PDT 24
Finished Jul 27 05:26:16 PM PDT 24
Peak memory 255216 kb
Host smart-6d6280be-9804-4f69-bc9e-ed29bf880430
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684297115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.1684297115
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.141109674
Short name T185
Test name
Test status
Simulation time 1777611167 ps
CPU time 48.81 seconds
Started Jul 27 05:21:08 PM PDT 24
Finished Jul 27 05:21:57 PM PDT 24
Peak memory 248732 kb
Host smart-461c24c8-8736-4da3-ab53-7b67134101c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14110
9674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.141109674
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.4189855808
Short name T218
Test name
Test status
Simulation time 2684570034 ps
CPU time 29.51 seconds
Started Jul 27 05:21:16 PM PDT 24
Finished Jul 27 05:21:46 PM PDT 24
Peak memory 257080 kb
Host smart-277e8a39-4236-45dc-9a52-27c178af9f01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41898
55808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.4189855808
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.3543993194
Short name T379
Test name
Test status
Simulation time 323031164 ps
CPU time 11.37 seconds
Started Jul 27 05:21:09 PM PDT 24
Finished Jul 27 05:21:21 PM PDT 24
Peak memory 253404 kb
Host smart-5db783f4-ec37-48c3-84f7-82393ff255d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35439
93194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.3543993194
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.4290829785
Short name T461
Test name
Test status
Simulation time 1244946760 ps
CPU time 34.24 seconds
Started Jul 27 05:21:09 PM PDT 24
Finished Jul 27 05:21:43 PM PDT 24
Peak memory 256940 kb
Host smart-a50435aa-8631-40ea-8fd0-bd2d213e8eb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42908
29785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.4290829785
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1097056272
Short name T666
Test name
Test status
Simulation time 2299670250 ps
CPU time 146.27 seconds
Started Jul 27 05:21:08 PM PDT 24
Finished Jul 27 05:23:34 PM PDT 24
Peak memory 252020 kb
Host smart-dba345fa-2ece-4a6f-8919-88e5177070ea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097056272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1097056272
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.3695385144
Short name T425
Test name
Test status
Simulation time 379688814954 ps
CPU time 1993.03 seconds
Started Jul 27 05:21:17 PM PDT 24
Finished Jul 27 05:54:31 PM PDT 24
Peak memory 281552 kb
Host smart-95bb4c4e-40f2-4836-a6f2-4b777938ca24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695385144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3695385144
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.3215488951
Short name T682
Test name
Test status
Simulation time 7657368870 ps
CPU time 155.14 seconds
Started Jul 27 05:21:18 PM PDT 24
Finished Jul 27 05:23:53 PM PDT 24
Peak memory 252096 kb
Host smart-8a26fd68-998e-421f-a243-620035e7b64b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32154
88951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.3215488951
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.4167577427
Short name T285
Test name
Test status
Simulation time 1498772846 ps
CPU time 35.25 seconds
Started Jul 27 05:21:18 PM PDT 24
Finished Jul 27 05:21:53 PM PDT 24
Peak memory 249688 kb
Host smart-73bd5a6b-33e0-4f7f-b61e-1405dbc08581
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41675
77427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.4167577427
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.3661805866
Short name T321
Test name
Test status
Simulation time 21718228307 ps
CPU time 1104.95 seconds
Started Jul 27 05:21:18 PM PDT 24
Finished Jul 27 05:39:43 PM PDT 24
Peak memory 272560 kb
Host smart-ca8c10d8-6874-4074-8a62-96e9634a7b13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661805866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3661805866
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.1658359004
Short name T570
Test name
Test status
Simulation time 164466164994 ps
CPU time 1793.84 seconds
Started Jul 27 05:21:17 PM PDT 24
Finished Jul 27 05:51:12 PM PDT 24
Peak memory 289012 kb
Host smart-43955ec4-3ea5-45c1-9494-d7e44639ea5a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658359004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.1658359004
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.422323073
Short name T659
Test name
Test status
Simulation time 49475784832 ps
CPU time 594.35 seconds
Started Jul 27 05:21:19 PM PDT 24
Finished Jul 27 05:31:14 PM PDT 24
Peak memory 248848 kb
Host smart-e0c376a2-96ca-4861-a53b-3db02d331127
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422323073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.422323073
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1319066120
Short name T482
Test name
Test status
Simulation time 2524883948 ps
CPU time 46.36 seconds
Started Jul 27 05:21:08 PM PDT 24
Finished Jul 27 05:21:55 PM PDT 24
Peak memory 256976 kb
Host smart-e00a4ad7-43b8-4e9c-a650-d5740b66be45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13190
66120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1319066120
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2209938555
Short name T638
Test name
Test status
Simulation time 258099105 ps
CPU time 16.17 seconds
Started Jul 27 05:21:09 PM PDT 24
Finished Jul 27 05:21:26 PM PDT 24
Peak memory 248380 kb
Host smart-76e397ca-b7ff-4bc5-b510-3f191accc521
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22099
38555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2209938555
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3110301064
Short name T284
Test name
Test status
Simulation time 1559497470 ps
CPU time 47.2 seconds
Started Jul 27 05:21:20 PM PDT 24
Finished Jul 27 05:22:07 PM PDT 24
Peak memory 249092 kb
Host smart-ca1d3ec1-2741-45e9-88e8-e95d319c9b09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31103
01064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3110301064
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2466952693
Short name T441
Test name
Test status
Simulation time 759164333 ps
CPU time 22.66 seconds
Started Jul 27 05:21:09 PM PDT 24
Finished Jul 27 05:21:32 PM PDT 24
Peak memory 256916 kb
Host smart-cf27ab4f-2af3-4066-b8b5-306ac3789336
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24669
52693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2466952693
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2234880256
Short name T50
Test name
Test status
Simulation time 274198634858 ps
CPU time 3739.94 seconds
Started Jul 27 05:21:16 PM PDT 24
Finished Jul 27 06:23:37 PM PDT 24
Peak memory 298032 kb
Host smart-8adb29bf-1bdc-4ea3-8d74-854a6be32afe
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234880256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2234880256
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.3828190852
Short name T440
Test name
Test status
Simulation time 14642115095 ps
CPU time 1556.24 seconds
Started Jul 27 05:21:20 PM PDT 24
Finished Jul 27 05:47:16 PM PDT 24
Peak memory 289212 kb
Host smart-d25ed2d5-8b72-4b3e-a65f-703d5dc59c6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828190852 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.3828190852
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2792881354
Short name T515
Test name
Test status
Simulation time 5723125519 ps
CPU time 80.87 seconds
Started Jul 27 05:21:18 PM PDT 24
Finished Jul 27 05:22:39 PM PDT 24
Peak memory 256584 kb
Host smart-00450b3d-853b-4e51-8660-2f134a0b1466
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27928
81354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2792881354
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.105962533
Short name T573
Test name
Test status
Simulation time 1493133930 ps
CPU time 23.33 seconds
Started Jul 27 05:21:18 PM PDT 24
Finished Jul 27 05:21:41 PM PDT 24
Peak memory 256184 kb
Host smart-3a022248-4f03-417c-8b2e-68efc9c62f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10596
2533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.105962533
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.4213228618
Short name T602
Test name
Test status
Simulation time 133151781565 ps
CPU time 1875.79 seconds
Started Jul 27 05:21:21 PM PDT 24
Finished Jul 27 05:52:37 PM PDT 24
Peak memory 272484 kb
Host smart-b28e7f26-d20b-44fb-9645-5b86971122d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213228618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.4213228618
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.1945103104
Short name T254
Test name
Test status
Simulation time 48653850408 ps
CPU time 1434.9 seconds
Started Jul 27 05:21:20 PM PDT 24
Finished Jul 27 05:45:15 PM PDT 24
Peak memory 273348 kb
Host smart-67deef22-984a-40a8-a1a7-0892dd472172
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945103104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1945103104
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3156585953
Short name T308
Test name
Test status
Simulation time 20042455100 ps
CPU time 220.04 seconds
Started Jul 27 05:21:20 PM PDT 24
Finished Jul 27 05:25:00 PM PDT 24
Peak memory 248784 kb
Host smart-931d35cd-c19f-4b7d-a3ce-9df5d8dd7cba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156585953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3156585953
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1821927515
Short name T703
Test name
Test status
Simulation time 376732786 ps
CPU time 20.47 seconds
Started Jul 27 05:21:17 PM PDT 24
Finished Jul 27 05:21:38 PM PDT 24
Peak memory 256044 kb
Host smart-a1b01de8-a469-4a38-91ff-9bf1f8394986
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18219
27515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1821927515
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.2909292364
Short name T225
Test name
Test status
Simulation time 3176139542 ps
CPU time 40.94 seconds
Started Jul 27 05:21:21 PM PDT 24
Finished Jul 27 05:22:02 PM PDT 24
Peak memory 256132 kb
Host smart-1d4d8ab9-db2d-49c7-af57-3e1cd0812177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29092
92364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.2909292364
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.3397920500
Short name T614
Test name
Test status
Simulation time 504742761 ps
CPU time 11.2 seconds
Started Jul 27 05:21:19 PM PDT 24
Finished Jul 27 05:21:30 PM PDT 24
Peak memory 254952 kb
Host smart-761d776b-bce6-470a-9559-77678eca5da4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33979
20500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.3397920500
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.255625473
Short name T465
Test name
Test status
Simulation time 174261595 ps
CPU time 16.17 seconds
Started Jul 27 05:21:17 PM PDT 24
Finished Jul 27 05:21:33 PM PDT 24
Peak memory 256924 kb
Host smart-b3213d0f-d034-406f-a582-a670bdb5dc6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25562
5473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.255625473
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1162736553
Short name T697
Test name
Test status
Simulation time 106127380053 ps
CPU time 1813.01 seconds
Started Jul 27 05:21:21 PM PDT 24
Finished Jul 27 05:51:34 PM PDT 24
Peak memory 297636 kb
Host smart-f930b9f4-aedc-44f9-9947-beaab85ae321
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162736553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1162736553
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.2686418484
Short name T673
Test name
Test status
Simulation time 297268531250 ps
CPU time 7648.24 seconds
Started Jul 27 05:21:28 PM PDT 24
Finished Jul 27 07:28:57 PM PDT 24
Peak memory 371788 kb
Host smart-4882146b-28e0-499a-99ec-73eb7e59948b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686418484 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.2686418484
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.1007432696
Short name T103
Test name
Test status
Simulation time 27157826725 ps
CPU time 725.49 seconds
Started Jul 27 05:21:28 PM PDT 24
Finished Jul 27 05:33:34 PM PDT 24
Peak memory 273120 kb
Host smart-57973ee0-31e2-422b-aaca-4f19baf83528
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007432696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.1007432696
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.4052592386
Short name T353
Test name
Test status
Simulation time 5852517908 ps
CPU time 333.23 seconds
Started Jul 27 05:21:28 PM PDT 24
Finished Jul 27 05:27:02 PM PDT 24
Peak memory 257080 kb
Host smart-26dfe55f-821d-4fe4-a7a6-0fbc119f6b5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40525
92386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.4052592386
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.4228062407
Short name T397
Test name
Test status
Simulation time 39229507 ps
CPU time 5.33 seconds
Started Jul 27 05:21:25 PM PDT 24
Finished Jul 27 05:21:31 PM PDT 24
Peak memory 254540 kb
Host smart-6eddbcd3-7655-46a2-bcee-cc697ee28a36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42280
62407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.4228062407
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2040817703
Short name T319
Test name
Test status
Simulation time 49388871086 ps
CPU time 1141.96 seconds
Started Jul 27 05:21:28 PM PDT 24
Finished Jul 27 05:40:30 PM PDT 24
Peak memory 273476 kb
Host smart-ba491c72-a8a0-4ee7-bd59-2fbcabf560c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040817703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2040817703
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.977314192
Short name T365
Test name
Test status
Simulation time 75524166994 ps
CPU time 2303.18 seconds
Started Jul 27 05:21:28 PM PDT 24
Finished Jul 27 05:59:52 PM PDT 24
Peak memory 281628 kb
Host smart-5e509328-ec6c-4d80-a5af-8afc5cab906c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977314192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.977314192
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2756073493
Short name T304
Test name
Test status
Simulation time 17103731481 ps
CPU time 655.3 seconds
Started Jul 27 05:21:29 PM PDT 24
Finished Jul 27 05:32:25 PM PDT 24
Peak memory 248840 kb
Host smart-f44dce68-9650-4615-8e95-21515419b074
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756073493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2756073493
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.3543381362
Short name T438
Test name
Test status
Simulation time 68932305 ps
CPU time 8.53 seconds
Started Jul 27 05:21:28 PM PDT 24
Finished Jul 27 05:21:37 PM PDT 24
Peak memory 248816 kb
Host smart-52bb0e36-547b-4651-ac14-118c3adf6478
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35433
81362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.3543381362
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2257609265
Short name T77
Test name
Test status
Simulation time 830929512 ps
CPU time 47.7 seconds
Started Jul 27 05:21:29 PM PDT 24
Finished Jul 27 05:22:17 PM PDT 24
Peak memory 256708 kb
Host smart-03da4e97-9747-4410-ae72-59a054e38e6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22576
09265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2257609265
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3915432174
Short name T424
Test name
Test status
Simulation time 350513163 ps
CPU time 14.5 seconds
Started Jul 27 05:21:28 PM PDT 24
Finished Jul 27 05:21:43 PM PDT 24
Peak memory 248164 kb
Host smart-1421495b-a83d-4db9-bd78-b73d373a4ea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39154
32174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3915432174
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1707528955
Short name T72
Test name
Test status
Simulation time 1546964358 ps
CPU time 22.27 seconds
Started Jul 27 05:21:30 PM PDT 24
Finished Jul 27 05:21:52 PM PDT 24
Peak memory 256932 kb
Host smart-ae9e4735-ff60-427d-a79a-d760ebef3c5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17075
28955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1707528955
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.4196942041
Short name T57
Test name
Test status
Simulation time 19466677457 ps
CPU time 1535.34 seconds
Started Jul 27 05:21:39 PM PDT 24
Finished Jul 27 05:47:15 PM PDT 24
Peak memory 289820 kb
Host smart-125f0220-5a69-4af4-b293-3c69381802be
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196942041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.4196942041
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.1136263996
Short name T212
Test name
Test status
Simulation time 74927562 ps
CPU time 3.52 seconds
Started Jul 27 05:18:19 PM PDT 24
Finished Jul 27 05:18:22 PM PDT 24
Peak memory 249020 kb
Host smart-ab9759d5-cfc2-4727-ac51-83f8c8321cf9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1136263996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.1136263996
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2035536919
Short name T542
Test name
Test status
Simulation time 1764422352 ps
CPU time 21.24 seconds
Started Jul 27 05:18:17 PM PDT 24
Finished Jul 27 05:18:39 PM PDT 24
Peak memory 248780 kb
Host smart-16997bfb-5a2d-4127-9fa2-f07359036e5f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2035536919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2035536919
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.4067229302
Short name T13
Test name
Test status
Simulation time 4643205842 ps
CPU time 264.46 seconds
Started Jul 27 05:18:18 PM PDT 24
Finished Jul 27 05:22:42 PM PDT 24
Peak memory 256876 kb
Host smart-db186af2-95f3-47f3-aa76-0064821f4754
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40672
29302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.4067229302
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.1571122256
Short name T414
Test name
Test status
Simulation time 1363442536 ps
CPU time 48.99 seconds
Started Jul 27 05:18:18 PM PDT 24
Finished Jul 27 05:19:07 PM PDT 24
Peak memory 248756 kb
Host smart-e422581f-204a-40c1-876e-71a0059d3ee4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15711
22256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1571122256
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.340719948
Short name T578
Test name
Test status
Simulation time 87662450155 ps
CPU time 2441.31 seconds
Started Jul 27 05:18:19 PM PDT 24
Finished Jul 27 05:59:00 PM PDT 24
Peak memory 285424 kb
Host smart-cda7babf-d894-49a9-ab82-27434770dbb1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340719948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.340719948
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2090958317
Short name T250
Test name
Test status
Simulation time 239949725836 ps
CPU time 3406.23 seconds
Started Jul 27 05:18:16 PM PDT 24
Finished Jul 27 06:15:02 PM PDT 24
Peak memory 289460 kb
Host smart-4cd04bbc-8a28-4f7d-93f7-66d5c6700b2d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090958317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2090958317
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.646882094
Short name T503
Test name
Test status
Simulation time 6122745970 ps
CPU time 184.82 seconds
Started Jul 27 05:18:21 PM PDT 24
Finished Jul 27 05:21:26 PM PDT 24
Peak memory 248856 kb
Host smart-7d8533dd-41d4-481e-9133-dde06a66341d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=646882094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.646882094
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1791358419
Short name T582
Test name
Test status
Simulation time 1442093191 ps
CPU time 42.88 seconds
Started Jul 27 05:18:18 PM PDT 24
Finished Jul 27 05:19:01 PM PDT 24
Peak memory 248748 kb
Host smart-6aa603d2-bcc9-4a08-b7a8-d8e969d04894
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17913
58419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1791358419
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.4151820772
Short name T541
Test name
Test status
Simulation time 528291159 ps
CPU time 21.69 seconds
Started Jul 27 05:18:17 PM PDT 24
Finished Jul 27 05:18:39 PM PDT 24
Peak memory 248364 kb
Host smart-3e11c4fd-9f11-40f1-9cf8-fb52c1d9c5c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41518
20772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.4151820772
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.3900977385
Short name T683
Test name
Test status
Simulation time 1206680761 ps
CPU time 13.34 seconds
Started Jul 27 05:18:16 PM PDT 24
Finished Jul 27 05:18:30 PM PDT 24
Peak memory 249076 kb
Host smart-659ea4ea-efc2-4e73-a0d9-cfc00a18c5ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39009
77385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3900977385
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.836763767
Short name T548
Test name
Test status
Simulation time 6498108836 ps
CPU time 32.3 seconds
Started Jul 27 05:18:18 PM PDT 24
Finished Jul 27 05:18:50 PM PDT 24
Peak memory 256332 kb
Host smart-0906e0ed-0aed-438f-9fca-3b727393e996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83676
3767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.836763767
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.1335245675
Short name T398
Test name
Test status
Simulation time 314734677592 ps
CPU time 3228.36 seconds
Started Jul 27 05:18:20 PM PDT 24
Finished Jul 27 06:12:09 PM PDT 24
Peak memory 289844 kb
Host smart-102506b0-8784-4b2e-9afd-1a5661b2d556
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335245675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.1335245675
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.3926082069
Short name T207
Test name
Test status
Simulation time 51334369 ps
CPU time 3.69 seconds
Started Jul 27 05:18:35 PM PDT 24
Finished Jul 27 05:18:39 PM PDT 24
Peak memory 249120 kb
Host smart-0ec807b4-1e89-4b7b-a6a4-88c4e2e82fa3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3926082069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.3926082069
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2786494569
Short name T653
Test name
Test status
Simulation time 78968647181 ps
CPU time 2263.22 seconds
Started Jul 27 05:18:19 PM PDT 24
Finished Jul 27 05:56:03 PM PDT 24
Peak memory 281456 kb
Host smart-78d46619-84c4-4812-a9db-390538bc9c39
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786494569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2786494569
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.3805526792
Short name T376
Test name
Test status
Simulation time 2653482267 ps
CPU time 24.51 seconds
Started Jul 27 05:18:27 PM PDT 24
Finished Jul 27 05:18:51 PM PDT 24
Peak memory 248692 kb
Host smart-aabdd6dc-c9ee-4462-985e-db26ff45d34a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3805526792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.3805526792
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.3730725013
Short name T349
Test name
Test status
Simulation time 666723991 ps
CPU time 41.75 seconds
Started Jul 27 05:18:19 PM PDT 24
Finished Jul 27 05:19:01 PM PDT 24
Peak memory 256100 kb
Host smart-a5399607-58da-4e4f-87ee-791835c13c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37307
25013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.3730725013
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2865457140
Short name T564
Test name
Test status
Simulation time 1879600225 ps
CPU time 28.59 seconds
Started Jul 27 05:18:17 PM PDT 24
Finished Jul 27 05:18:45 PM PDT 24
Peak memory 248836 kb
Host smart-be5f2238-bc5a-4472-8ad7-849de36d0af6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28654
57140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2865457140
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.998898184
Short name T689
Test name
Test status
Simulation time 69906059060 ps
CPU time 1563.03 seconds
Started Jul 27 05:18:22 PM PDT 24
Finished Jul 27 05:44:26 PM PDT 24
Peak memory 289564 kb
Host smart-46631ed1-b030-4fa0-bf58-39a36fa54d5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998898184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.998898184
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.2477502365
Short name T236
Test name
Test status
Simulation time 108299568175 ps
CPU time 1142.22 seconds
Started Jul 27 05:18:27 PM PDT 24
Finished Jul 27 05:37:29 PM PDT 24
Peak memory 288920 kb
Host smart-2f7b8a40-5a28-4064-9f75-f6894989d1a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477502365 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2477502365
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3640427383
Short name T522
Test name
Test status
Simulation time 4398003820 ps
CPU time 75.76 seconds
Started Jul 27 05:18:19 PM PDT 24
Finished Jul 27 05:19:35 PM PDT 24
Peak memory 256724 kb
Host smart-6e1392ee-e383-4446-b39b-55ef2f6229aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36404
27383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3640427383
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.1159736764
Short name T607
Test name
Test status
Simulation time 259168814 ps
CPU time 18.22 seconds
Started Jul 27 05:18:20 PM PDT 24
Finished Jul 27 05:18:38 PM PDT 24
Peak memory 248112 kb
Host smart-5ea40f43-a165-48a3-80c2-3bf90bef6a4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11597
36764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.1159736764
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.4043680078
Short name T400
Test name
Test status
Simulation time 175609219 ps
CPU time 18.35 seconds
Started Jul 27 05:18:18 PM PDT 24
Finished Jul 27 05:18:36 PM PDT 24
Peak memory 256516 kb
Host smart-8b588c0f-75c6-4f3e-807b-612ddf22b7f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40436
80078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.4043680078
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.4267995694
Short name T526
Test name
Test status
Simulation time 910833551 ps
CPU time 46.66 seconds
Started Jul 27 05:18:17 PM PDT 24
Finished Jul 27 05:19:03 PM PDT 24
Peak memory 255960 kb
Host smart-301d0308-10ae-4f4b-90a2-d6d59ea4d5fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42679
95694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.4267995694
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.938256503
Short name T265
Test name
Test status
Simulation time 131168183188 ps
CPU time 1426.84 seconds
Started Jul 27 05:18:35 PM PDT 24
Finished Jul 27 05:42:23 PM PDT 24
Peak memory 297248 kb
Host smart-8a542cb5-31df-4786-8ecc-6153db7b8d40
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938256503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_hand
ler_stress_all.938256503
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.2835720402
Short name T213
Test name
Test status
Simulation time 80263803 ps
CPU time 3.74 seconds
Started Jul 27 05:18:29 PM PDT 24
Finished Jul 27 05:18:33 PM PDT 24
Peak memory 249040 kb
Host smart-dc5a5b7b-17f8-4b8c-a83f-f224e6f5578e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2835720402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2835720402
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.842066309
Short name T610
Test name
Test status
Simulation time 48879395772 ps
CPU time 2700.15 seconds
Started Jul 27 05:18:27 PM PDT 24
Finished Jul 27 06:03:28 PM PDT 24
Peak memory 287888 kb
Host smart-0b12089b-ab65-4998-b9de-bded616d2e4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=842066309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.842066309
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.215279043
Short name T444
Test name
Test status
Simulation time 423189020 ps
CPU time 20.47 seconds
Started Jul 27 05:18:31 PM PDT 24
Finished Jul 27 05:18:51 PM PDT 24
Peak memory 248808 kb
Host smart-8f3ee4a9-b184-48a9-929e-5ae1f2d65ab3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=215279043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.215279043
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.751578899
Short name T586
Test name
Test status
Simulation time 2995142146 ps
CPU time 43.04 seconds
Started Jul 27 05:18:29 PM PDT 24
Finished Jul 27 05:19:12 PM PDT 24
Peak memory 248380 kb
Host smart-0af0ce35-33c0-4826-b0ca-001bf7a391b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75157
8899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.751578899
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.4285069384
Short name T92
Test name
Test status
Simulation time 1097295305 ps
CPU time 13.42 seconds
Started Jul 27 05:18:27 PM PDT 24
Finished Jul 27 05:18:40 PM PDT 24
Peak memory 248468 kb
Host smart-fe97df9d-6787-4d71-b490-05efa0382ec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42850
69384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.4285069384
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.3945402319
Short name T325
Test name
Test status
Simulation time 74161095965 ps
CPU time 2167.55 seconds
Started Jul 27 05:18:29 PM PDT 24
Finished Jul 27 05:54:37 PM PDT 24
Peak memory 272800 kb
Host smart-3636b4b8-179b-468a-a01a-5f387b8997b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945402319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.3945402319
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.282287893
Short name T681
Test name
Test status
Simulation time 138692559628 ps
CPU time 1554.98 seconds
Started Jul 27 05:18:31 PM PDT 24
Finished Jul 27 05:44:26 PM PDT 24
Peak memory 273496 kb
Host smart-12b7adf1-4770-4ee3-bd64-d20e2767ebbe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282287893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.282287893
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.3493873263
Short name T538
Test name
Test status
Simulation time 13470332179 ps
CPU time 555.36 seconds
Started Jul 27 05:18:29 PM PDT 24
Finished Jul 27 05:27:45 PM PDT 24
Peak memory 248820 kb
Host smart-7a2513b6-5c86-4f32-8f48-56937c9f8cd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493873263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3493873263
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.760063727
Short name T368
Test name
Test status
Simulation time 1107098482 ps
CPU time 60.93 seconds
Started Jul 27 05:18:37 PM PDT 24
Finished Jul 27 05:19:38 PM PDT 24
Peak memory 256048 kb
Host smart-f7eef988-7872-4e12-90ca-d0570adde469
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76006
3727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.760063727
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.939005932
Short name T224
Test name
Test status
Simulation time 18114023084 ps
CPU time 61.64 seconds
Started Jul 27 05:18:29 PM PDT 24
Finished Jul 27 05:19:31 PM PDT 24
Peak memory 256980 kb
Host smart-06c8d16e-ab29-4950-8a77-dc3af1a62662
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93900
5932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.939005932
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.4287714717
Short name T272
Test name
Test status
Simulation time 380530502 ps
CPU time 24.6 seconds
Started Jul 27 05:18:28 PM PDT 24
Finished Jul 27 05:18:53 PM PDT 24
Peak memory 248348 kb
Host smart-4c081ca8-7148-4b7a-a883-07ec354d74ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42877
14717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.4287714717
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.1096515737
Short name T374
Test name
Test status
Simulation time 2236845963 ps
CPU time 68.05 seconds
Started Jul 27 05:18:32 PM PDT 24
Finished Jul 27 05:19:40 PM PDT 24
Peak memory 248788 kb
Host smart-db4cd370-e989-4ade-b9ef-99fc153bad1e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10965
15737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.1096515737
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.535009970
Short name T204
Test name
Test status
Simulation time 66543154 ps
CPU time 3.74 seconds
Started Jul 27 05:18:27 PM PDT 24
Finished Jul 27 05:18:31 PM PDT 24
Peak memory 249140 kb
Host smart-5eebb68d-ba1d-4445-aea4-f22b42302a30
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=535009970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.535009970
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.574865838
Short name T91
Test name
Test status
Simulation time 28358089658 ps
CPU time 1608.19 seconds
Started Jul 27 05:18:35 PM PDT 24
Finished Jul 27 05:45:24 PM PDT 24
Peak memory 273216 kb
Host smart-3e726f44-1079-4cf4-9f97-51174424cdd2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574865838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.574865838
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.3635844182
Short name T556
Test name
Test status
Simulation time 1219165758 ps
CPU time 53.35 seconds
Started Jul 27 05:18:28 PM PDT 24
Finished Jul 27 05:19:21 PM PDT 24
Peak memory 256460 kb
Host smart-8a2fb8ec-dd6a-460f-83c9-e9d316e765c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36358
44182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3635844182
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.523044786
Short name T409
Test name
Test status
Simulation time 1168013440 ps
CPU time 25.86 seconds
Started Jul 27 05:18:30 PM PDT 24
Finished Jul 27 05:18:56 PM PDT 24
Peak memory 248628 kb
Host smart-deeb8e1b-1548-4fcf-b44a-c133f4fdee61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52304
4786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.523044786
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.3572615270
Short name T505
Test name
Test status
Simulation time 173895072429 ps
CPU time 2529.33 seconds
Started Jul 27 05:18:35 PM PDT 24
Finished Jul 27 06:00:45 PM PDT 24
Peak memory 284516 kb
Host smart-b4a4fc36-dd20-4cc2-8acf-810d27215868
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572615270 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3572615270
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.183743547
Short name T303
Test name
Test status
Simulation time 10131793326 ps
CPU time 403.28 seconds
Started Jul 27 05:18:30 PM PDT 24
Finished Jul 27 05:25:13 PM PDT 24
Peak memory 248676 kb
Host smart-7be0ec11-db98-4513-9a3a-4f020bc99299
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183743547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.183743547
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.2811731370
Short name T41
Test name
Test status
Simulation time 243380282 ps
CPU time 15.1 seconds
Started Jul 27 05:18:30 PM PDT 24
Finished Jul 27 05:18:45 PM PDT 24
Peak memory 256824 kb
Host smart-42fdc707-43d5-42d5-878c-6ec6cac2eed1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28117
31370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2811731370
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2349434547
Short name T537
Test name
Test status
Simulation time 2724575038 ps
CPU time 36.03 seconds
Started Jul 27 05:18:25 PM PDT 24
Finished Jul 27 05:19:01 PM PDT 24
Peak memory 256460 kb
Host smart-1508258c-85b4-4750-95fd-0fa47552a883
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23494
34547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2349434547
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.373634155
Short name T609
Test name
Test status
Simulation time 1161091081 ps
CPU time 21.89 seconds
Started Jul 27 05:18:26 PM PDT 24
Finished Jul 27 05:18:48 PM PDT 24
Peak memory 248680 kb
Host smart-1c630664-5341-4119-96ff-2dd6b0242dd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37363
4155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.373634155
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.3163759895
Short name T511
Test name
Test status
Simulation time 635617503 ps
CPU time 31.74 seconds
Started Jul 27 05:18:27 PM PDT 24
Finished Jul 27 05:18:59 PM PDT 24
Peak memory 256916 kb
Host smart-35467470-f9e2-45cb-8243-5db3ac1d8069
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31637
59895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.3163759895
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.1592396436
Short name T52
Test name
Test status
Simulation time 200853030469 ps
CPU time 3026.46 seconds
Started Jul 27 05:18:30 PM PDT 24
Finished Jul 27 06:08:57 PM PDT 24
Peak memory 302176 kb
Host smart-484caf3d-fe5c-4e31-88c7-df34ddbc2367
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592396436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.1592396436
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2702426536
Short name T210
Test name
Test status
Simulation time 50250071 ps
CPU time 4.11 seconds
Started Jul 27 05:18:35 PM PDT 24
Finished Jul 27 05:18:39 PM PDT 24
Peak memory 248992 kb
Host smart-e9aef241-243b-4054-952d-f655861c6fb4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2702426536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2702426536
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.4095120729
Short name T428
Test name
Test status
Simulation time 104702068153 ps
CPU time 1474.03 seconds
Started Jul 27 05:18:26 PM PDT 24
Finished Jul 27 05:43:00 PM PDT 24
Peak memory 272796 kb
Host smart-2c053f0f-24f4-457d-8d2f-2f925731a41a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095120729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.4095120729
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.3775877660
Short name T520
Test name
Test status
Simulation time 978407382 ps
CPU time 11.63 seconds
Started Jul 27 05:18:27 PM PDT 24
Finished Jul 27 05:18:39 PM PDT 24
Peak memory 248704 kb
Host smart-6980c1de-06d4-46f1-acf8-35cd0648874a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3775877660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3775877660
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.705166695
Short name T421
Test name
Test status
Simulation time 968685761 ps
CPU time 33.53 seconds
Started Jul 27 05:18:29 PM PDT 24
Finished Jul 27 05:19:03 PM PDT 24
Peak memory 256436 kb
Host smart-4e654d41-080a-4ab7-b78f-b113a8c6d911
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70516
6695 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.705166695
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2393764257
Short name T581
Test name
Test status
Simulation time 74687683 ps
CPU time 5.85 seconds
Started Jul 27 05:18:28 PM PDT 24
Finished Jul 27 05:18:34 PM PDT 24
Peak memory 240040 kb
Host smart-41174816-b5c7-4031-8efd-858b497949fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23937
64257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2393764257
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.4234507080
Short name T291
Test name
Test status
Simulation time 65286336588 ps
CPU time 1371.44 seconds
Started Jul 27 05:18:31 PM PDT 24
Finished Jul 27 05:41:23 PM PDT 24
Peak memory 289108 kb
Host smart-01b763a0-f0fa-4065-86b1-28dcdfb14740
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234507080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.4234507080
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3807808296
Short name T71
Test name
Test status
Simulation time 85412991760 ps
CPU time 1364.11 seconds
Started Jul 27 05:18:33 PM PDT 24
Finished Jul 27 05:41:18 PM PDT 24
Peak memory 273340 kb
Host smart-31c4a594-4adb-447a-92a7-8180ad28d619
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807808296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3807808296
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.2008289505
Short name T16
Test name
Test status
Simulation time 7635065879 ps
CPU time 315.12 seconds
Started Jul 27 05:18:33 PM PDT 24
Finished Jul 27 05:23:48 PM PDT 24
Peak memory 248788 kb
Host smart-9874f225-9fda-4e36-b09a-d5bafe2981f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008289505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.2008289505
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2524105288
Short name T42
Test name
Test status
Simulation time 346294598 ps
CPU time 19.98 seconds
Started Jul 27 05:18:26 PM PDT 24
Finished Jul 27 05:18:46 PM PDT 24
Peak memory 248744 kb
Host smart-f9e92c15-edef-444d-8ddf-121097c719da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25241
05288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2524105288
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1400390721
Short name T489
Test name
Test status
Simulation time 415286972 ps
CPU time 26.94 seconds
Started Jul 27 05:18:29 PM PDT 24
Finished Jul 27 05:18:56 PM PDT 24
Peak memory 256504 kb
Host smart-159333fa-e050-4e17-880f-17928357d7af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14003
90721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1400390721
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1169148989
Short name T619
Test name
Test status
Simulation time 394920752 ps
CPU time 26.84 seconds
Started Jul 27 05:18:29 PM PDT 24
Finished Jul 27 05:18:56 PM PDT 24
Peak memory 248408 kb
Host smart-093928b5-7e79-4998-a939-a3a6c64c7bd6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11691
48989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1169148989
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.1679631397
Short name T356
Test name
Test status
Simulation time 43213734 ps
CPU time 5.84 seconds
Started Jul 27 05:18:29 PM PDT 24
Finished Jul 27 05:18:35 PM PDT 24
Peak memory 253768 kb
Host smart-bfb91a28-5b55-4611-b918-506aef209079
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16796
31397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.1679631397
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.4089303355
Short name T273
Test name
Test status
Simulation time 88519059637 ps
CPU time 2298.62 seconds
Started Jul 27 05:18:29 PM PDT 24
Finished Jul 27 05:56:48 PM PDT 24
Peak memory 287920 kb
Host smart-7b551690-bb34-4125-ab41-d50361f064b4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089303355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.4089303355
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.1304498606
Short name T274
Test name
Test status
Simulation time 387012020574 ps
CPU time 9886.92 seconds
Started Jul 27 05:18:27 PM PDT 24
Finished Jul 27 08:03:15 PM PDT 24
Peak memory 417616 kb
Host smart-24818995-8c31-4661-8cc7-03ed011aa4ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304498606 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.1304498606
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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