Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	66045893	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

32142073

1

T1

110033

T2

134078

T3

2363

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	14809378	1			T1	42744		T2	53051		T3	998
values[0x0]	40508057	1			T1	153095		T2	184895		T3	3275
values[0x1]	42870531	1			T1	152251		T2	184297		T3	3133

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	56224647	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

41963319

1

T1

138957

T2

169231

T3

3003

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	318480	1			T1	1355		T2	1748		T3	9
valid_sources[0x01]	310146	1			T1	1237		T2	1658		T3	10
valid_sources[0x02]	325743	1			T1	1334		T2	1623		T3	47
valid_sources[0x03]	313765	1			T1	1389		T2	1609		T3	39
valid_sources[0x04]	337447	1			T1	1361		T2	1582		T3	41
valid_sources[0x05]	673870	1			T1	1363		T2	1619		T3	21
valid_sources[0x06]	319037	1			T1	1375		T2	1687		T3	43
valid_sources[0x07]	311317	1			T1	1353		T2	1734		T3	25
valid_sources[0x08]	309737	1			T1	1296		T2	1700		T3	42
valid_sources[0x09]	724747	1			T1	1383		T2	1724		T3	40
valid_sources[0x0a]	324391	1			T1	1433		T2	1655		T3	39
valid_sources[0x0b]	629809	1			T1	1415		T2	1657		T3	22
valid_sources[0x0c]	673791	1			T1	1299		T2	1638		T3	27
valid_sources[0x0d]	316109	1			T1	1364		T2	1721		T3	26
valid_sources[0x0e]	311546	1			T1	1296		T2	1574		T3	25
valid_sources[0x0f]	314353	1			T1	1340		T2	1596		T3	30
valid_sources[0x10]	790400	1			T1	1319		T2	1624		T3	18
valid_sources[0x11]	303861	1			T1	1342		T2	1546		T3	46
valid_sources[0x12]	306270	1			T1	1252		T2	1591		T3	22
valid_sources[0x13]	670599	1			T1	1403		T2	1630		T3	21
valid_sources[0x14]	310597	1			T1	1292		T2	1661		T3	25
valid_sources[0x15]	308252	1			T1	1393		T2	1771		T3	19
valid_sources[0x16]	301811	1			T1	1384		T2	1593		T3	27
valid_sources[0x17]	892183	1			T1	1303		T2	1546		T3	38
valid_sources[0x18]	328135	1			T1	1338		T2	1691		T3	24
valid_sources[0x19]	311686	1			T1	1388		T2	1703		T3	17
valid_sources[0x1a]	317683	1			T1	1339		T2	1771		T3	28
valid_sources[0x1b]	315939	1			T1	1294		T2	1640		T3	25
valid_sources[0x1c]	318121	1			T1	1415		T2	1527		T3	31
valid_sources[0x1d]	315176	1			T1	1396		T2	1576		T3	26
valid_sources[0x1e]	311564	1			T1	1408		T2	1642		T3	30
valid_sources[0x1f]	313245	1			T1	1417		T2	1636		T3	35
valid_sources[0x20]	316779	1			T1	1295		T2	1679		T3	15
valid_sources[0x21]	795385	1			T1	1347		T2	1640		T3	34
valid_sources[0x22]	530737	1			T1	1404		T2	1767		T3	18
valid_sources[0x23]	315859	1			T1	1388		T2	1651		T3	20
valid_sources[0x24]	316623	1			T1	1440		T2	1612		T3	40
valid_sources[0x25]	310825	1			T1	1420		T2	1759		T3	22
valid_sources[0x26]	324979	1			T1	1323		T2	1648		T3	30
valid_sources[0x27]	628926	1			T1	1359		T2	1620		T3	22
valid_sources[0x28]	311916	1			T1	1421		T2	1699		T3	23
valid_sources[0x29]	307584	1			T1	1360		T2	1645		T3	29
valid_sources[0x2a]	315185	1			T1	1388		T2	1593		T3	39
valid_sources[0x2b]	301391	1			T1	1320		T2	1694		T3	37
valid_sources[0x2c]	315009	1			T1	1450		T2	1680		T3	33
valid_sources[0x2d]	300301	1			T1	1400		T2	1634		T3	27
valid_sources[0x2e]	325035	1			T1	1366		T2	1646		T3	38
valid_sources[0x2f]	313644	1			T1	1396		T2	1624		T3	14
valid_sources[0x30]	707657	1			T1	1265		T2	1689		T3	36
valid_sources[0x31]	555798	1			T1	1354		T2	1668		T3	30
valid_sources[0x32]	304664	1			T1	1399		T2	1682		T3	34
valid_sources[0x33]	316584	1			T1	1372		T2	1703		T3	16
valid_sources[0x34]	310790	1			T1	1314		T2	1673		T3	33
valid_sources[0x35]	305559	1			T1	1410		T2	1565		T3	5
valid_sources[0x36]	321595	1			T1	1337		T2	1678		T3	41
valid_sources[0x37]	320815	1			T1	1364		T2	1632		T3	23
valid_sources[0x38]	326682	1			T1	1366		T2	1666		T3	28
valid_sources[0x39]	752689	1			T1	1342		T2	1665		T3	27
valid_sources[0x3a]	312971	1			T1	1305		T2	1623		T3	54
valid_sources[0x3b]	308624	1			T1	1439		T2	1613		T3	55
valid_sources[0x3c]	309371	1			T1	1353		T2	1552		T3	18
valid_sources[0x3d]	324744	1			T1	1360		T2	1593		T3	39
valid_sources[0x3e]	301113	1			T1	1290		T2	1606		T3	15
valid_sources[0x3f]	321558	1			T1	1384		T2	1641		T3	33
valid_sources[0x40]	751623	1			T1	1359		T2	1574		T3	11
valid_sources[0x41]	746611	1			T1	1349		T2	1672		T3	17
valid_sources[0x42]	745462	1			T1	1350		T2	1713		T3	63
valid_sources[0x43]	311116	1			T1	1291		T2	1711		T3	35
valid_sources[0x44]	712315	1			T1	1321		T2	1674		T3	20
valid_sources[0x45]	304915	1			T1	1352		T2	1655		T3	34
valid_sources[0x46]	315896	1			T1	1338		T2	1654		T3	20
valid_sources[0x47]	310519	1			T1	1378		T2	1560		T3	33
valid_sources[0x48]	311899	1			T1	1337		T2	1697		T3	13
valid_sources[0x49]	313262	1			T1	1267		T2	1672		T3	6
valid_sources[0x4a]	334304	1			T1	1237		T2	1601		T3	31
valid_sources[0x4b]	515399	1			T1	1406		T2	1703		T3	32
valid_sources[0x4c]	321260	1			T1	1452		T2	1642		T3	21
valid_sources[0x4d]	329293	1			T1	1336		T2	1682		T3	23
valid_sources[0x4e]	320086	1			T1	1376		T2	1662		T3	21
valid_sources[0x4f]	313702	1			T1	1359		T2	1746		T3	15
valid_sources[0x50]	315349	1			T1	1371		T2	1735		T3	28
valid_sources[0x51]	317339	1			T1	1334		T2	1654		T3	25
valid_sources[0x52]	317812	1			T1	1419		T2	1581		T3	10
valid_sources[0x53]	321097	1			T1	1396		T2	1658		T3	24
valid_sources[0x54]	307863	1			T1	1306		T2	1719		T3	15
valid_sources[0x55]	752086	1			T1	1402		T2	1668		T3	46
valid_sources[0x56]	308027	1			T1	1352		T2	1569		T3	31
valid_sources[0x57]	304433	1			T1	1326		T2	1724		T3	6
valid_sources[0x58]	315323	1			T1	1277		T2	1540		T3	29
valid_sources[0x59]	590973	1			T1	1351		T2	1662		T3	23
valid_sources[0x5a]	317595	1			T1	1359		T2	1655		T3	33
valid_sources[0x5b]	304222	1			T1	1412		T2	1654		T3	27
valid_sources[0x5c]	310886	1			T1	1441		T2	1619		T3	21
valid_sources[0x5d]	313095	1			T1	1363		T2	1675		T3	42
valid_sources[0x5e]	312438	1			T1	1280		T2	1664		T3	29
valid_sources[0x5f]	302451	1			T1	1358		T2	1625		T3	23
valid_sources[0x60]	310586	1			T1	1369		T2	1646		T3	25
valid_sources[0x61]	1163564	1			T1	1337		T2	1692		T3	39
valid_sources[0x62]	311376	1			T1	1250		T2	1520		T3	33
valid_sources[0x63]	312507	1			T1	1343		T2	1566		T3	19
valid_sources[0x64]	314036	1			T1	1442		T2	1586		T3	22
valid_sources[0x65]	326245	1			T1	1429		T2	1646		T3	29
valid_sources[0x66]	310262	1			T1	1380		T2	1634		T3	37
valid_sources[0x67]	625383	1			T1	1319		T2	1540		T3	19
valid_sources[0x68]	323936	1			T1	1364		T2	1681		T3	24
valid_sources[0x69]	313002	1			T1	1310		T2	1631		T3	14
valid_sources[0x6a]	836017	1			T1	1358		T2	1700		T3	65
valid_sources[0x6b]	329816	1			T1	1344		T2	1616		T3	33
valid_sources[0x6c]	315510	1			T1	1394		T2	1674		T3	53
valid_sources[0x6d]	316196	1			T1	1374		T2	1670		T3	37
valid_sources[0x6e]	701071	1			T1	1467		T2	1624		T3	23
valid_sources[0x6f]	351292	1			T1	1351		T2	1606		T3	23
valid_sources[0x70]	303279	1			T1	1400		T2	1583		T3	31
valid_sources[0x71]	324408	1			T1	1362		T2	1641		T3	13
valid_sources[0x72]	307949	1			T1	1324		T2	1738		T3	27
valid_sources[0x73]	308852	1			T1	1357		T2	1675		T3	12
valid_sources[0x74]	315711	1			T1	1346		T2	1614		T3	21
valid_sources[0x75]	317496	1			T1	1350		T2	1679		T3	22
valid_sources[0x76]	613640	1			T1	1429		T2	1557		T3	40
valid_sources[0x77]	304976	1			T1	1398		T2	1669		T3	27
valid_sources[0x78]	309875	1			T1	1344		T2	1665		T3	40
valid_sources[0x79]	312732	1			T1	1304		T2	1696		T3	52
valid_sources[0x7a]	315643	1			T1	1349		T2	1604		T3	14
valid_sources[0x7b]	686457	1			T1	1473		T2	1578		T3	28
valid_sources[0x7c]	307831	1			T1	1358		T2	1649		T3	35
valid_sources[0x7d]	628614	1			T1	1446		T2	1696		T3	26
valid_sources[0x7e]	395878	1			T1	1369		T2	1688		T3	32
valid_sources[0x7f]	305830	1			T1	1387		T2	1604		T3	22
valid_sources[0x80]	314256	1			T1	1368		T2	1595		T3	16

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

7415525

1

T1

21351

T2

26515

T3

511

values[0x0]

all_enables

biggest_size

15580023

1

T1

56947

T2

69161

T3

1222

values[0x1]

all_enables

biggest_size

9146525

1

T1

31735

T2

38402

T3

630