SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | u_alert_handler_lpg_ctrl |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 70625 | 70625 | 0 | 0 |
OutputsKnown_A | 2147483647 | 2147483647 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 2147483647 | 2147483647 | 0 | 90000 |
gen_no_flops.OutputDelay_A | 2147483647 | 2147483647 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 70625 | 70625 | 0 | 0 |
T1 | 113 | 113 | 0 | 0 |
T2 | 113 | 113 | 0 | 0 |
T3 | 113 | 113 | 0 | 0 |
T4 | 113 | 113 | 0 | 0 |
T5 | 113 | 113 | 0 | 0 |
T7 | 113 | 113 | 0 | 0 |
T11 | 113 | 113 | 0 | 0 |
T12 | 113 | 113 | 0 | 0 |
T21 | 113 | 113 | 0 | 0 |
T22 | 113 | 113 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 48372701 | 48372136 | 0 | 0 |
T2 | 13329141 | 13328237 | 0 | 0 |
T3 | 7677785 | 7669762 | 0 | 0 |
T4 | 14392245 | 14392132 | 0 | 0 |
T5 | 38165524 | 38164168 | 0 | 0 |
T7 | 56625995 | 56616164 | 0 | 0 |
T11 | 7047810 | 7039787 | 0 | 0 |
T12 | 63495491 | 63494361 | 0 | 0 |
T21 | 1415438 | 1409675 | 0 | 0 |
T22 | 7099903 | 7092106 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 90000 |
T1 | 20547696 | 20547408 | 0 | 144 |
T2 | 5661936 | 5661552 | 0 | 144 |
T3 | 3261360 | 3257808 | 0 | 144 |
T4 | 6113520 | 6113472 | 0 | 144 |
T5 | 16211904 | 16211136 | 0 | 144 |
T7 | 24053520 | 24049200 | 0 | 144 |
T11 | 2993760 | 2990208 | 0 | 144 |
T12 | 26971536 | 26971056 | 0 | 144 |
T21 | 601248 | 598656 | 0 | 144 |
T22 | 3015888 | 3012432 | 0 | 144 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 2147483647 | 2147483647 | 0 | 0 |
T1 | 27825005 | 27824680 | 0 | 0 |
T2 | 7667205 | 7666685 | 0 | 0 |
T3 | 4416425 | 4411810 | 0 | 0 |
T4 | 8278725 | 8278660 | 0 | 0 |
T5 | 21953620 | 21952840 | 0 | 0 |
T7 | 32572475 | 32566820 | 0 | 0 |
T11 | 4054050 | 4049435 | 0 | 0 |
T12 | 36523955 | 36523305 | 0 | 0 |
T21 | 814190 | 810875 | 0 | 0 |
T22 | 4084015 | 4079530 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
CONT_ASSIGN | 124 | 1 | 1 | 100.00 |
ALWAYS | 128 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
124 | 1 | 1 | |
128 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_flops.gen_no_stable_chks.OutputDelay_A | 696897943 | 696730933 | 0 | 1875 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696730933 | 0 | 1875 |
T1 | 428077 | 428071 | 0 | 3 |
T2 | 117957 | 117949 | 0 | 3 |
T3 | 67945 | 67871 | 0 | 3 |
T4 | 127365 | 127364 | 0 | 3 |
T5 | 337748 | 337732 | 0 | 3 |
T7 | 501115 | 501025 | 0 | 3 |
T11 | 62370 | 62296 | 0 | 3 |
T12 | 561907 | 561897 | 0 | 3 |
T21 | 12526 | 12472 | 0 | 3 |
T22 | 62831 | 62759 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 625 | 625 | 0 | 0 |
OutputsKnown_A | 696897943 | 696737905 | 0 | 0 |
gen_no_flops.OutputDelay_A | 696897943 | 696737905 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 625 | 625 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T21 | 1 | 1 | 0 | 0 |
T22 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 696897943 | 696737905 | 0 | 0 |
T1 | 428077 | 428072 | 0 | 0 |
T2 | 117957 | 117949 | 0 | 0 |
T3 | 67945 | 67874 | 0 | 0 |
T4 | 127365 | 127364 | 0 | 0 |
T5 | 337748 | 337736 | 0 | 0 |
T7 | 501115 | 501028 | 0 | 0 |
T11 | 62370 | 62299 | 0 | 0 |
T12 | 561907 | 561897 | 0 | 0 |
T21 | 12526 | 12475 | 0 | 0 |
T22 | 62831 | 62762 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |