Module Definition
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Module : alert_handler_accu
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_classes[0].u_accu 100.00 100.00 100.00 100.00
tb.dut.gen_classes[1].u_accu 100.00 100.00 100.00 100.00
tb.dut.gen_classes[2].u_accu 100.00 100.00 100.00 100.00
tb.dut.gen_classes[3].u_accu 100.00 100.00 100.00 100.00


Module Instance : tb.dut.gen_classes[0].u_accu

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_count 100.00 100.00


Module Instance : tb.dut.gen_classes[1].u_accu

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_count 100.00 100.00


Module Instance : tb.dut.gen_classes[2].u_accu

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_count 100.00 100.00


Module Instance : tb.dut.gen_classes[3].u_accu

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_prim_count 100.00 100.00

Line Coverage for Module : alert_handler_accu
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN5611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
56 1 1

Cond Coverage for Module : alert_handler_accu
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT38,T41,T203
11CoveredT1,T2,T3 

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T7
Assert Coverage for Module : alert_handler_accu
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CountSaturateStable_A 2147483647 15278 0 0
DisabledNoTrigBkwd_A 2147483647 833086 0 0
DisabledNoTrigFwd_A 2147483647 1578149770 0 0


CountSaturateStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 15278 0 0
T14 251278 0 0 0
T38 3191 690 0 0
T41 5095 1490 0 0
T65 572648 0 0 0
T68 29474 0 0 0
T82 41105 0 0 0
T83 36029 0 0 0
T98 34350 0 0 0
T99 35244 0 0 0
T100 5975 0 0 0
T116 41293 0 0 0
T203 3089 677 0 0
T204 0 798 0 0
T205 0 230 0 0
T206 0 995 0 0
T207 0 957 0 0
T208 0 539 0 0
T209 0 498 0 0
T210 0 827 0 0
T211 0 600 0 0
T212 0 761 0 0
T213 0 548 0 0
T214 0 769 0 0
T215 0 665 0 0
T216 0 124 0 0
T217 0 916 0 0
T218 0 1484 0 0
T219 0 1128 0 0
T220 0 582 0 0
T221 260230 0 0 0
T222 363201 0 0 0
T223 367488 0 0 0
T224 72735 0 0 0
T225 14795 0 0 0
T226 120691 0 0 0
T227 25852 0 0 0
T228 117523 0 0 0
T229 28307 0 0 0

DisabledNoTrigBkwd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 833086 0 0
T1 856154 1519 0 0
T2 471828 3495 0 0
T3 271780 0 0 0
T4 509460 1123 0 0
T5 1350992 2146 0 0
T6 0 1291 0 0
T7 2004460 6635 0 0
T11 249480 380 0 0
T12 2247628 7672 0 0
T17 0 2555 0 0
T18 0 1159 0 0
T19 0 7564 0 0
T20 0 85 0 0
T21 50104 8 0 0
T22 251324 15 0 0
T38 6382 18 0 0
T39 0 1 0 0
T40 0 206 0 0

DisabledNoTrigFwd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 1578149770 0 0
T1 1712308 442534 0 0
T2 471828 244453 0 0
T3 271780 114322 0 0
T4 509460 469068 0 0
T5 1350992 716966 0 0
T7 2004460 1008458 0 0
T11 249480 55985 0 0
T12 2247628 745964 0 0
T21 50104 40505 0 0
T22 251324 194393 0 0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN5611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
56 1 1

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T7
11CoveredT1,T2,T3 

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT203,T209,T210
11CoveredT1,T2,T3 

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T7
Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CountSaturateStable_A 696897943 2667 0 0
DisabledNoTrigBkwd_A 696897943 247074 0 0
DisabledNoTrigFwd_A 696897943 374641626 0 0


CountSaturateStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 696897943 2667 0 0
T82 41105 0 0 0
T83 36029 0 0 0
T203 3089 677 0 0
T209 0 498 0 0
T210 0 827 0 0
T215 0 665 0 0
T223 367488 0 0 0
T224 72735 0 0 0
T225 14795 0 0 0
T226 120691 0 0 0
T227 25852 0 0 0
T228 117523 0 0 0
T229 28307 0 0 0

DisabledNoTrigBkwd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 696897943 247074 0 0
T1 428077 686 0 0
T2 117957 2 0 0
T3 67945 0 0 0
T4 127365 371 0 0
T5 337748 943 0 0
T7 501115 1097 0 0
T11 62370 66 0 0
T12 561907 3 0 0
T21 12526 8 0 0
T22 62831 4 0 0
T39 0 1 0 0

DisabledNoTrigFwd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 696897943 374641626 0 0
T1 428077 3026 0 0
T2 117957 117609 0 0
T3 67945 15531 0 0
T4 127365 117437 0 0
T5 337748 128197 0 0
T7 501115 2023 0 0
T11 62370 7493 0 0
T12 561907 561204 0 0
T21 12526 3080 0 0
T22 62831 50464 0 0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN5611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
56 1 1

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT41,T205,T211
11CoveredT1,T2,T3 

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT2,T11,T4
Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CountSaturateStable_A 696897943 6283 0 0
DisabledNoTrigBkwd_A 696897943 191073 0 0
DisabledNoTrigFwd_A 696897943 404411786 0 0


CountSaturateStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 696897943 6283 0 0
T14 251278 0 0 0
T41 5095 1490 0 0
T65 572648 0 0 0
T68 29474 0 0 0
T98 34350 0 0 0
T99 35244 0 0 0
T100 5975 0 0 0
T116 41293 0 0 0
T205 0 230 0 0
T211 0 600 0 0
T214 0 769 0 0
T218 0 1484 0 0
T219 0 1128 0 0
T220 0 582 0 0
T221 260230 0 0 0
T222 363201 0 0 0

DisabledNoTrigBkwd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 696897943 191073 0 0
T2 117957 2094 0 0
T3 67945 0 0 0
T4 127365 22 0 0
T5 337748 161 0 0
T6 0 975 0 0
T7 501115 0 0 0
T11 62370 67 0 0
T12 561907 3060 0 0
T17 0 1300 0 0
T20 0 85 0 0
T21 12526 0 0 0
T22 62831 6 0 0
T38 3191 0 0 0
T40 0 24 0 0

DisabledNoTrigFwd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 696897943 404411786 0 0
T1 428077 427522 0 0
T2 117957 5447 0 0
T3 67945 25434 0 0
T4 127365 126391 0 0
T5 337748 189128 0 0
T7 501115 501028 0 0
T11 62370 7355 0 0
T12 561907 26812 0 0
T21 12526 12475 0 0
T22 62831 37613 0 0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN5611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
56 1 1

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T7
11CoveredT1,T2,T3 

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT38,T204,T207
11CoveredT1,T2,T3 

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T7
Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CountSaturateStable_A 696897943 3206 0 0
DisabledNoTrigBkwd_A 696897943 212133 0 0
DisabledNoTrigFwd_A 696897943 386778460 0 0


CountSaturateStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 696897943 3206 0 0
T6 771263 0 0 0
T13 895122 0 0 0
T17 889738 0 0 0
T18 218686 0 0 0
T19 105335 0 0 0
T26 39720 0 0 0
T38 3191 690 0 0
T39 25212 0 0 0
T40 29133 0 0 0
T64 35755 0 0 0
T204 0 798 0 0
T207 0 957 0 0
T212 0 761 0 0

DisabledNoTrigBkwd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 696897943 212133 0 0
T1 428077 833 0 0
T2 117957 6 0 0
T3 67945 0 0 0
T4 127365 539 0 0
T5 337748 19 0 0
T7 501115 5538 0 0
T11 62370 81 0 0
T12 561907 1975 0 0
T17 0 1255 0 0
T21 12526 0 0 0
T22 62831 1 0 0
T38 0 18 0 0

DisabledNoTrigFwd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 696897943 386778460 0 0
T1 428077 8901 0 0
T2 117957 117376 0 0
T3 67945 64183 0 0
T4 127365 110005 0 0
T5 337748 239847 0 0
T7 501115 4379 0 0
T11 62370 33581 0 0
T12 561907 44052 0 0
T21 12526 12475 0 0
T22 62831 55878 0 0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN5611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
29 1 1
56 1 1

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T7
11CoveredT1,T2,T3 

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT206,T208,T213
11CoveredT1,T2,T3 

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT2,T11,T4
Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CountSaturateStable_A 696897943 3122 0 0
DisabledNoTrigBkwd_A 696897943 182806 0 0
DisabledNoTrigFwd_A 696897943 412317898 0 0


CountSaturateStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 696897943 3122 0 0
T206 4408 995 0 0
T208 0 539 0 0
T213 0 548 0 0
T216 0 124 0 0
T217 0 916 0 0
T230 9702 0 0 0
T231 78522 0 0 0
T232 252370 0 0 0
T233 356984 0 0 0
T234 901405 0 0 0
T235 92787 0 0 0
T236 156388 0 0 0
T237 268816 0 0 0
T238 80323 0 0 0

DisabledNoTrigBkwd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 696897943 182806 0 0
T2 117957 1393 0 0
T3 67945 0 0 0
T4 127365 191 0 0
T5 337748 1023 0 0
T6 0 316 0 0
T7 501115 0 0 0
T11 62370 166 0 0
T12 561907 2634 0 0
T18 0 1159 0 0
T19 0 7564 0 0
T21 12526 0 0 0
T22 62831 4 0 0
T38 3191 0 0 0
T40 0 182 0 0

DisabledNoTrigFwd_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 696897943 412317898 0 0
T1 428077 3085 0 0
T2 117957 4021 0 0
T3 67945 9174 0 0
T4 127365 115235 0 0
T5 337748 159794 0 0
T7 501115 501028 0 0
T11 62370 7556 0 0
T12 561907 113896 0 0
T21 12526 12475 0 0
T22 62831 50438 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%