Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[1].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T21
1	0	1	Covered	T1,T2,T21
1	1	0	Covered	T3,T7,T11
1	1	1	Covered	T3,T7,T11

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T11
0	1	Covered	T11,T4,T5
1	0	Covered	T7,T5,T6

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T11
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T7,T5,T6

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T11
1	0	Covered	T23,T24
1	1	Covered	T11,T4,T5

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T7

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T4,T12,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T2,T11

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T2,T7,T21

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T7

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T7
Phase1St	198	Covered	T1,T2,T7
Phase2St	215	Covered	T1,T2,T7
Phase3St	233	Covered	T1,T2,T7
TerminalSt	249	Covered	T1,T2,T7
TimeoutSt	159	Covered	T3,T7,T11

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T2,T7
IdleSt->TimeoutSt	159	Covered	T3,T7,T11
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T4,T5,T20
Phase0St->Phase1St	198	Covered	T1,T2,T7
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T7,T5,T25
Phase1St->Phase2St	215	Covered	T1,T2,T7
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T4,T5,T20
Phase2St->Phase3St	233	Covered	T1,T2,T7
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T4,T5,T26
Phase3St->TerminalSt	249	Covered	T1,T2,T7
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T1,T2,T21
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T3,T4,T5
TimeoutSt->Phase0St	172	Covered	T7,T11,T4

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T11
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T7,T11,T4
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T11
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T5,T20
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T7,T25,T27
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T4,T5,T20
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T5,T26
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T2,T21
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	914	0	0
CheckAccumTrig0_A	2147483647	2296	0	0
CheckAccumTrig1_A	2147483647	129	0	0
CheckClr_A	2147483647	1035	0	0
CheckEn_A	2147483647	1231954579	0	0
CheckPhase0_A	2147483647	2634	0	0
CheckPhase1_A	2147483647	2593	0	0
CheckPhase2_A	2147483647	2550	0	0
CheckPhase3_A	2147483647	2505	0	0
CheckTimeout0_A	2147483647	4484	0	0
CheckTimeoutSt1_A	2147483647	525751	0	0
CheckTimeoutSt2_A	2147483647	4109	0	0
CheckTimeoutStTrig_A	2147483647	245	0	0
ErrorStAllEscAsserted_A	2147483647	4511	0	0
ErrorStIsTerminal_A	2147483647	3671	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	914	0	0
T8	86008	114	0	0
T9	125100	286	0	0
T10	0	264	0	0
T28	0	134	0	0
T29	0	116	0	0
T30	107068	0	0	0
T31	746128	0	0	0
T32	46720	0	0	0
T33	946184	0	0	0
T34	362340	0	0	0
T35	3365692	0	0	0
T36	1723000	0	0	0
T37	513528	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2296	0	0
T1	856154	3	0	0
T2	471828	5	0	0
T3	271780	0	0	0
T4	509460	17	0	0
T5	1350992	20	0	0
T6	0	3	0	0
T7	2004460	2	0	0
T11	249480	5	0	0
T12	2247628	6	0	0
T17	0	2	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	2	0	0
T21	50104	1	0	0
T22	251324	5	0	0
T38	6382	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	129	0	0
T4	127365	0	0	0
T5	337748	2	0	0
T6	771263	1	0	0
T7	501115	1	0	0
T11	62370	0	0	0
T12	561907	0	0	0
T17	889738	0	0	0
T20	0	2	0	0
T21	12526	0	0	0
T22	62831	0	0	0
T23	99017	0	0	0
T27	0	1	0	0
T38	3191	0	0	0
T39	25212	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	6	0	0
T45	492306	1	0	0
T46	831619	1	0	0
T47	608159	1	0	0
T48	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	0	3	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	9141	0	0	0
T59	66812	0	0	0
T60	27432	0	0	0
T61	713790	0	0	0
T62	29702	0	0	0
T63	109078	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1035	0	0
T1	428077	1	0	0
T2	235914	1	0	0
T3	135890	0	0	0
T4	382095	8	0	0
T5	1350992	6	0	0
T6	0	2	0	0
T7	1503345	1	0	0
T11	187110	2	0	0
T12	2247628	0	0	0
T14	0	1	0	0
T15	0	1	0	0
T17	1779476	0	0	0
T18	218686	1	0	0
T19	105335	0	0	0
T20	0	8	0	0
T21	37578	1	0	0
T22	251324	2	0	0
T25	0	1	0	0
T26	39720	2	0	0
T27	0	2	0	0
T38	9573	0	0	0
T39	50424	1	0	0
T42	0	1	0	0
T64	35755	1	0	0
T65	0	13	0	0
T66	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1231954579	0	0
T1	1712308	442534	0	0
T2	471828	10933	0	0
T3	271780	114321	0	0
T4	509460	968204	0	0
T5	1350992	680919	0	0
T7	2004460	1006108	0	0
T11	249480	42093	0	0
T12	2247628	48028	0	0
T21	50104	40502	0	0
T22	251324	106130	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2634	0	0
T1	856154	3	0	0
T2	471828	5	0	0
T3	271780	0	0	0
T4	509460	19	0	0
T5	1350992	27	0	0
T6	0	4	0	0
T7	2004460	3	0	0
T11	249480	6	0	0
T12	2247628	6	0	0
T17	0	2	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	4	0	0
T21	50104	1	0	0
T22	251324	5	0	0
T38	6382	1	0	0
T39	0	1	0	0
T40	0	3	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2593	0	0
T1	856154	3	0	0
T2	471828	5	0	0
T3	271780	0	0	0
T4	509460	19	0	0
T5	1350992	26	0	0
T6	0	4	0	0
T7	2004460	2	0	0
T11	249480	6	0	0
T12	2247628	6	0	0
T17	0	2	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	4	0	0
T21	50104	1	0	0
T22	251324	5	0	0
T38	6382	1	0	0
T39	0	1	0	0
T40	0	3	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2550	0	0
T1	856154	3	0	0
T2	471828	5	0	0
T3	271780	0	0	0
T4	509460	18	0	0
T5	1350992	25	0	0
T6	0	4	0	0
T7	2004460	2	0	0
T11	249480	6	0	0
T12	2247628	5	0	0
T17	0	2	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	4	0	0
T21	50104	1	0	0
T22	251324	5	0	0
T38	6382	1	0	0
T39	0	1	0	0
T40	0	3	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2505	0	0
T1	856154	3	0	0
T2	471828	5	0	0
T3	271780	0	0	0
T4	509460	17	0	0
T5	1350992	23	0	0
T6	0	4	0	0
T7	2004460	2	0	0
T11	249480	6	0	0
T12	2247628	5	0	0
T17	0	2	0	0
T18	0	1	0	0
T19	0	1	0	0
T20	0	4	0	0
T21	50104	1	0	0
T22	251324	5	0	0
T38	6382	1	0	0
T39	0	1	0	0
T40	0	3	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4484	0	0
T3	203835	21	0	0
T4	509460	5	0	0
T5	1350992	50	0	0
T6	0	207	0	0
T7	1503345	1	0	0
T11	187110	1	0	0
T12	2247628	0	0	0
T17	889738	0	0	0
T18	218686	3	0	0
T19	0	1	0	0
T20	0	28	0	0
T21	37578	0	0	0
T22	251324	0	0	0
T25	0	1	0	0
T26	39720	0	0	0
T27	0	3	0	0
T38	12764	0	0	0
T39	100848	1	0	0
T40	0	1	0	0
T42	0	16	0	0
T64	35755	1	0	0
T65	0	189	0	0
T67	0	3	0	0
T68	0	4	0	0
T69	0	1	0	0
T70	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	525751	0	0
T3	203835	4460	0	0
T4	509460	991	0	0
T5	1350992	7187	0	0
T6	0	12444	0	0
T7	1503345	4	0	0
T11	187110	432	0	0
T12	2247628	0	0	0
T17	889738	0	0	0
T18	218686	189	0	0
T19	0	40	0	0
T20	0	5928	0	0
T21	37578	0	0	0
T22	251324	0	0	0
T25	0	25	0	0
T26	39720	0	0	0
T27	0	208	0	0
T38	12764	0	0	0
T39	100848	28	0	0
T40	0	156	0	0
T42	0	1467	0	0
T64	35755	100	0	0
T65	0	15856	0	0
T67	0	552	0	0
T68	0	1391	0	0
T69	0	123	0	0
T70	0	39	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4109	0	0
T3	203835	21	0	0
T4	382095	2	0	0
T5	1350992	42	0	0
T6	771263	205	0	0
T7	1503345	0	0	0
T11	187110	0	0	0
T12	1685721	0	0	0
T17	889738	0	0	0
T18	218686	3	0	0
T19	105335	1	0	0
T20	0	18	0	0
T21	37578	0	0	0
T22	251324	0	0	0
T25	0	1	0	0
T26	39720	0	0	0
T27	0	4	0	0
T38	12764	0	0	0
T39	100848	1	0	0
T42	0	21	0	0
T64	35755	1	0	0
T65	0	189	0	0
T67	0	3	0	0
T68	0	2	0	0
T69	0	53	0	0
T70	0	8	0	0
T71	0	4	0	0
T72	0	13	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	245	0	0
T4	254730	3	0	0
T5	1350992	5	0	0
T6	1542526	1	0	0
T11	62370	1	0	0
T12	1123814	0	0	0
T17	3558952	0	0	0
T18	874744	0	0	0
T19	210670	0	0	0
T20	0	8	0	0
T22	251324	0	0	0
T26	158880	0	0	0
T38	12764	0	0	0
T39	100848	0	0	0
T40	0	1	0	0
T42	0	2	0	0
T44	0	1	0	0
T63	0	1	0	0
T64	107265	0	0	0
T68	0	2	0	0
T69	0	3	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0
T77	0	1	0	0
T78	0	1	0	0
T79	0	4	0	0
T80	0	1	0	0
T81	0	1	0	0
T82	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4511	0	0
T8	86008	628	0	0
T9	125100	1335	0	0
T10	0	1308	0	0
T28	0	621	0	0
T29	0	619	0	0
T30	107068	0	0	0
T31	746128	0	0	0
T32	46720	0	0	0
T33	946184	0	0	0
T34	362340	0	0	0
T35	3365692	0	0	0
T36	1723000	0	0	0
T37	513528	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3671	0	0
T8	86008	508	0	0
T9	125100	1095	0	0
T10	0	1068	0	0
T28	0	501	0	0
T29	0	499	0	0
T30	107068	0	0	0
T31	746128	0	0	0
T32	46720	0	0	0
T33	946184	0	0	0
T34	362340	0	0	0
T35	3365692	0	0	0
T36	1723000	0	0	0
T37	513528	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1712308	1712288	0	0
T2	471828	471796	0	0
T3	271780	271496	0	0
T4	509460	509456	0	0
T5	1350992	1350944	0	0
T7	2004460	2004112	0	0
T11	249480	249196	0	0
T12	2247628	2247588	0	0
T21	50104	49900	0	0
T22	251324	251048	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1712308	1712288	0	0
T2	471828	471796	0	0
T3	271780	271496	0	0
T4	509460	509456	0	0
T5	1350992	1350944	0	0
T7	2004460	2004112	0	0
T11	249480	249196	0	0
T12	2247628	2247588	0	0
T21	50104	49900	0	0
T22	251324	251048	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T21
1	0	1	Covered	T1,T21,T4
1	1	0	Covered	T3,T4,T5
1	1	1	Covered	T3,T7,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T5
0	1	Covered	T5,T20,T68
1	0	Covered	T7,T5,T20

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T7,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T7,T5,T20

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T5
1	0	Not Covered
1	1	Covered	T5,T20,T68

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T7,T21
1	Covered	T2,T7,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T4,T5,T39

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T7,T21
1	Covered	T1,T11,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T7,T21,T4

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T4,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T4,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T7,T21

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T7,T21

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T7
Phase1St	198	Covered	T1,T2,T7
Phase2St	215	Covered	T1,T2,T7
Phase3St	233	Covered	T1,T2,T7
TerminalSt	249	Covered	T1,T2,T7
TimeoutSt	159	Covered	T3,T7,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T2,T7
IdleSt->TimeoutSt	159	Covered	T3,T7,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T4,T5,T20
Phase0St->Phase1St	198	Covered	T1,T2,T7
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T7,T43,T23
Phase1St->Phase2St	215	Covered	T1,T2,T7
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T4,T20,T81
Phase2St->Phase3St	233	Covered	T1,T2,T7
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T5,T79,T83
Phase3St->TerminalSt	249	Covered	T1,T2,T7
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T21,T4,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T5,T39
TimeoutSt->Phase0St	172	Covered	T7,T5,T20

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T7,T5,T20
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T7,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T39
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T5,T20
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T7,T43,T23
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T4,T20,T81
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T5,T79,T83
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T21,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	696897943	198	0	0
CheckAccumTrig0_A	696897943	828	0	0
CheckAccumTrig1_A	696897943	59	0	0
CheckClr_A	696897943	389	0	0
CheckEn_A	696701005	265403117	0	0
CheckPhase0_A	696897943	931	0	0
CheckPhase1_A	696897943	912	0	0
CheckPhase2_A	696897943	900	0	0
CheckPhase3_A	696897943	889	0	0
CheckTimeout0_A	696897943	1842	0	0
CheckTimeoutSt1_A	696897943	203362	0	0
CheckTimeoutSt2_A	696897943	1721	0	0
CheckTimeoutStTrig_A	696897943	62	0	0
ErrorStAllEscAsserted_A	696897943	1096	0	0
ErrorStIsTerminal_A	696897943	886	0	0
EscStateOut_A	696699571	696629336	0	0
u_state_regs_A	696897943	696737905	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	198	0	0
T8	21502	29	0	0
T9	31275	51	0	0
T10	0	57	0	0
T28	0	32	0	0
T29	0	29	0	0
T30	26767	0	0	0
T31	186532	0	0	0
T32	11680	0	0	0
T33	236546	0	0	0
T34	90585	0	0	0
T35	841423	0	0	0
T36	430750	0	0	0
T37	128382	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	828	0	0
T1	428077	1	0	0
T2	117957	1	0	0
T3	67945	0	0	0
T4	127365	8	0	0
T5	337748	8	0	0
T7	501115	1	0	0
T11	62370	1	0	0
T12	561907	1	0	0
T21	12526	1	0	0
T22	62831	1	0	0
T39	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	59	0	0
T4	127365	0	0	0
T5	337748	2	0	0
T7	501115	1	0	0
T11	62370	0	0	0
T12	561907	0	0	0
T17	889738	0	0	0
T20	0	2	0	0
T21	12526	0	0	0
T22	62831	0	0	0
T27	0	1	0	0
T38	3191	0	0	0
T39	25212	0	0	0
T42	0	1	0	0
T43	0	1	0	0
T44	0	6	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	389	0	0
T4	127365	5	0	0
T5	337748	5	0	0
T6	0	2	0	0
T7	501115	1	0	0
T11	62370	0	0	0
T12	561907	0	0	0
T14	0	1	0	0
T17	889738	0	0	0
T20	0	6	0	0
T21	12526	1	0	0
T22	62831	0	0	0
T38	3191	0	0	0
T39	25212	1	0	0
T64	0	1	0	0
T65	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696701005	265403117	0	0
T1	428077	3026	0	0
T2	117957	2061	0	0
T3	67945	15531	0	0
T4	127365	114446	0	0
T5	337748	110647	0	0
T7	501115	2023	0	0
T11	62370	7493	0	0
T12	561907	3243	0	0
T21	12526	3080	0	0
T22	62831	16978	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	931	0	0
T1	428077	1	0	0
T2	117957	1	0	0
T3	67945	0	0	0
T4	127365	7	0	0
T5	337748	11	0	0
T7	501115	2	0	0
T11	62370	1	0	0
T12	561907	1	0	0
T21	12526	1	0	0
T22	62831	1	0	0
T39	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	912	0	0
T1	428077	1	0	0
T2	117957	1	0	0
T3	67945	0	0	0
T4	127365	7	0	0
T5	337748	11	0	0
T7	501115	1	0	0
T11	62370	1	0	0
T12	561907	1	0	0
T21	12526	1	0	0
T22	62831	1	0	0
T39	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	900	0	0
T1	428077	1	0	0
T2	117957	1	0	0
T3	67945	0	0	0
T4	127365	6	0	0
T5	337748	11	0	0
T7	501115	1	0	0
T11	62370	1	0	0
T12	561907	1	0	0
T21	12526	1	0	0
T22	62831	1	0	0
T39	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	889	0	0
T1	428077	1	0	0
T2	117957	1	0	0
T3	67945	0	0	0
T4	127365	6	0	0
T5	337748	10	0	0
T7	501115	1	0	0
T11	62370	1	0	0
T12	561907	1	0	0
T21	12526	1	0	0
T22	62831	1	0	0
T39	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	1842	0	0
T3	67945	7	0	0
T4	127365	0	0	0
T5	337748	11	0	0
T6	0	204	0	0
T7	501115	1	0	0
T11	62370	0	0	0
T12	561907	0	0	0
T20	0	12	0	0
T21	12526	0	0	0
T22	62831	0	0	0
T38	3191	0	0	0
T39	25212	1	0	0
T64	0	1	0	0
T65	0	98	0	0
T67	0	1	0	0
T68	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	203362	0	0
T3	67945	1397	0	0
T4	127365	0	0	0
T5	337748	2772	0	0
T6	0	12295	0	0
T7	501115	4	0	0
T11	62370	0	0	0
T12	561907	0	0	0
T20	0	2599	0	0
T21	12526	0	0	0
T22	62831	0	0	0
T38	3191	0	0	0
T39	25212	28	0	0
T64	0	100	0	0
T65	0	8183	0	0
T67	0	178	0	0
T68	0	1138	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	1721	0	0
T3	67945	7	0	0
T4	127365	0	0	0
T5	337748	7	0	0
T6	0	204	0	0
T7	501115	0	0	0
T11	62370	0	0	0
T12	561907	0	0	0
T20	0	7	0	0
T21	12526	0	0	0
T22	62831	0	0	0
T38	3191	0	0	0
T39	25212	1	0	0
T42	0	7	0	0
T64	0	1	0	0
T65	0	98	0	0
T67	0	1	0	0
T68	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	62	0	0
T5	337748	2	0	0
T6	771263	0	0	0
T17	889738	0	0	0
T18	218686	0	0	0
T19	105335	0	0	0
T20	0	3	0	0
T22	62831	0	0	0
T26	39720	0	0	0
T38	3191	0	0	0
T39	25212	0	0	0
T63	0	1	0	0
T64	35755	0	0	0
T68	0	1	0	0
T69	0	2	0	0
T76	0	1	0	0
T78	0	1	0	0
T79	0	2	0	0
T80	0	1	0	0
T81	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	1096	0	0
T8	21502	177	0	0
T9	31275	321	0	0
T10	0	302	0	0
T28	0	156	0	0
T29	0	140	0	0
T30	26767	0	0	0
T31	186532	0	0	0
T32	11680	0	0	0
T33	236546	0	0	0
T34	90585	0	0	0
T35	841423	0	0	0
T36	430750	0	0	0
T37	128382	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	886	0	0
T8	21502	147	0	0
T9	31275	261	0	0
T10	0	242	0	0
T28	0	126	0	0
T29	0	110	0	0
T30	26767	0	0	0
T31	186532	0	0	0
T32	11680	0	0	0
T33	236546	0	0	0
T34	90585	0	0	0
T35	841423	0	0	0
T36	430750	0	0	0
T37	128382	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696699571	696629336	0	0
T1	428077	428072	0	0
T2	117957	117949	0	0
T3	67945	67874	0	0
T4	127365	127364	0	0
T5	337748	337736	0	0
T7	501115	501028	0	0
T11	62370	62299	0	0
T12	561907	561897	0	0
T21	12526	12475	0	0
T22	62831	62762	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	696737905	0	0
T1	428077	428072	0	0
T2	117957	117949	0	0
T3	67945	67874	0	0
T4	127365	127364	0	0
T5	337748	337736	0	0
T7	501115	501028	0	0
T11	62370	62299	0	0
T12	561907	561897	0	0
T21	12526	12475	0	0
T22	62831	62762	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T7
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T7
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T7

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T7

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T7,T11
1	0	1	Covered	T2,T4,T12
1	1	0	Covered	T3,T11,T4
1	1	1	Covered	T4,T5,T18

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T4,T5,T18
0	1	Covered	T4,T5,T20
1	0	Covered	T6,T69,T79

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T4,T5,T18
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T6,T69,T79

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T18
1	0	Not Covered
1	1	Covered	T4,T5,T20

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T4,T12

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T4,T5,T17

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T7
1	Covered	T1,T11,T18

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T11,T4
1	Covered	T2,T7,T4

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T12,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T2,T7

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T1,T7,T11

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T7
Phase1St	198	Covered	T1,T2,T7
Phase2St	215	Covered	T1,T2,T7
Phase3St	233	Covered	T1,T2,T7
TerminalSt	249	Covered	T1,T2,T7
TimeoutSt	159	Covered	T4,T5,T18

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T1,T2,T7
IdleSt->TimeoutSt	159	Covered	T4,T5,T18
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T84,T85,T86
Phase0St->Phase1St	198	Covered	T1,T2,T7
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T23,T87,T88
Phase1St->Phase2St	215	Covered	T1,T2,T7
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T23,T89,T90
Phase2St->Phase3St	233	Covered	T1,T2,T7
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T4,T26,T15
Phase3St->TerminalSt	249	Covered	T1,T2,T7
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T1,T11,T4
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T5,T18,T6
TimeoutSt->Phase0St	172	Covered	T4,T5,T6

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T7
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T18
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T6
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T4,T5,T18
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T5,T18,T6
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T86,T91,T92
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T7
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T7
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T23,T87,T88
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T7
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T7
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T23,T89,T90
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T7
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T4,T26,T15
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T7
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T7
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T11,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T7
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	696897943	239	0	0
CheckAccumTrig0_A	696897943	476	0	0
CheckAccumTrig1_A	696897943	30	0	0
CheckClr_A	696897943	220	0	0
CheckEn_A	696701005	324379039	0	0
CheckPhase0_A	696897943	569	0	0
CheckPhase1_A	696897943	564	0	0
CheckPhase2_A	696897943	557	0	0
CheckPhase3_A	696897943	546	0	0
CheckTimeout0_A	696897943	622	0	0
CheckTimeoutSt1_A	696897943	74605	0	0
CheckTimeoutSt2_A	696897943	522	0	0
CheckTimeoutStTrig_A	696897943	70	0	0
ErrorStAllEscAsserted_A	696897943	1110	0	0
ErrorStIsTerminal_A	696897943	900	0	0
EscStateOut_A	696699571	696629336	0	0
u_state_regs_A	696897943	696737905	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	239	0	0
T8	21502	26	0	0
T9	31275	82	0	0
T10	0	69	0	0
T28	0	32	0	0
T29	0	30	0	0
T30	26767	0	0	0
T31	186532	0	0	0
T32	11680	0	0	0
T33	236546	0	0	0
T34	90585	0	0	0
T35	841423	0	0	0
T36	430750	0	0	0
T37	128382	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	476	0	0
T1	428077	2	0	0
T2	117957	1	0	0
T3	67945	0	0	0
T4	127365	4	0	0
T5	337748	1	0	0
T7	501115	1	0	0
T11	62370	2	0	0
T12	561907	1	0	0
T17	0	1	0	0
T21	12526	0	0	0
T22	62831	1	0	0
T38	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	30	0	0
T6	771263	1	0	0
T13	895122	0	0	0
T14	251278	0	0	0
T20	722417	0	0	0
T24	0	1	0	0
T40	29133	0	0	0
T41	5095	0	0	0
T49	0	1	0	0
T67	17363	0	0	0
T69	0	1	0	0
T86	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T97	0	1	0	0
T98	34350	0	0	0
T99	35244	0	0	0
T100	5975	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	220	0	0
T1	428077	1	0	0
T2	117957	0	0	0
T3	67945	0	0	0
T4	127365	2	0	0
T5	337748	0	0	0
T7	501115	0	0	0
T11	62370	1	0	0
T12	561907	0	0	0
T15	0	1	0	0
T18	0	1	0	0
T20	0	1	0	0
T21	12526	0	0	0
T22	62831	1	0	0
T26	0	2	0	0
T42	0	1	0	0
T65	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696701005	324379039	0	0
T1	428077	8901	0	0
T2	117957	5679	0	0
T3	67945	64182	0	0
T4	127365	630467	0	0
T5	337748	239846	0	0
T7	501115	2031	0	0
T11	62370	19689	0	0
T12	561907	14537	0	0
T21	12526	12474	0	0
T22	62831	55877	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	569	0	0
T1	428077	2	0	0
T2	117957	1	0	0
T3	67945	0	0	0
T4	127365	6	0	0
T5	337748	2	0	0
T7	501115	1	0	0
T11	62370	2	0	0
T12	561907	1	0	0
T17	0	1	0	0
T21	12526	0	0	0
T22	62831	1	0	0
T38	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	564	0	0
T1	428077	2	0	0
T2	117957	1	0	0
T3	67945	0	0	0
T4	127365	6	0	0
T5	337748	2	0	0
T7	501115	1	0	0
T11	62370	2	0	0
T12	561907	1	0	0
T17	0	1	0	0
T21	12526	0	0	0
T22	62831	1	0	0
T38	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	557	0	0
T1	428077	2	0	0
T2	117957	1	0	0
T3	67945	0	0	0
T4	127365	6	0	0
T5	337748	2	0	0
T7	501115	1	0	0
T11	62370	2	0	0
T12	561907	1	0	0
T17	0	1	0	0
T21	12526	0	0	0
T22	62831	1	0	0
T38	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	546	0	0
T1	428077	2	0	0
T2	117957	1	0	0
T3	67945	0	0	0
T4	127365	5	0	0
T5	337748	2	0	0
T7	501115	1	0	0
T11	62370	2	0	0
T12	561907	1	0	0
T17	0	1	0	0
T21	12526	0	0	0
T22	62831	1	0	0
T38	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	622	0	0
T4	127365	2	0	0
T5	337748	7	0	0
T6	0	2	0	0
T12	561907	0	0	0
T17	889738	0	0	0
T18	218686	3	0	0
T20	0	4	0	0
T22	62831	0	0	0
T26	39720	0	0	0
T27	0	2	0	0
T38	3191	0	0	0
T39	25212	0	0	0
T42	0	6	0	0
T64	35755	0	0	0
T65	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	74605	0	0
T4	127365	477	0	0
T5	337748	920	0	0
T6	0	111	0	0
T12	561907	0	0	0
T17	889738	0	0	0
T18	218686	189	0	0
T20	0	579	0	0
T22	62831	0	0	0
T26	39720	0	0	0
T27	0	148	0	0
T38	3191	0	0	0
T39	25212	0	0	0
T42	0	315	0	0
T64	35755	0	0	0
T65	0	194	0	0
T67	0	178	0	0
T68	0	253	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	522	0	0
T5	337748	6	0	0
T6	771263	1	0	0
T17	889738	0	0	0
T18	218686	3	0	0
T19	105335	0	0	0
T20	0	3	0	0
T22	62831	0	0	0
T26	39720	0	0	0
T27	0	2	0	0
T38	3191	0	0	0
T39	25212	0	0	0
T42	0	6	0	0
T64	35755	0	0	0
T65	0	1	0	0
T67	0	1	0	0
T71	0	1	0	0
T72	0	13	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	70	0	0
T4	127365	2	0	0
T5	337748	1	0	0
T12	561907	0	0	0
T17	889738	0	0	0
T18	218686	0	0	0
T20	0	1	0	0
T22	62831	0	0	0
T26	39720	0	0	0
T38	3191	0	0	0
T39	25212	0	0	0
T44	0	1	0	0
T64	35755	0	0	0
T68	0	1	0	0
T69	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T79	0	1	0	0
T82	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	1110	0	0
T8	21502	143	0	0
T9	31275	334	0	0
T10	0	339	0	0
T28	0	143	0	0
T29	0	151	0	0
T30	26767	0	0	0
T31	186532	0	0	0
T32	11680	0	0	0
T33	236546	0	0	0
T34	90585	0	0	0
T35	841423	0	0	0
T36	430750	0	0	0
T37	128382	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	900	0	0
T8	21502	113	0	0
T9	31275	274	0	0
T10	0	279	0	0
T28	0	113	0	0
T29	0	121	0	0
T30	26767	0	0	0
T31	186532	0	0	0
T32	11680	0	0	0
T33	236546	0	0	0
T34	90585	0	0	0
T35	841423	0	0	0
T36	430750	0	0	0
T37	128382	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696699571	696629336	0	0
T1	428077	428072	0	0
T2	117957	117949	0	0
T3	67945	67874	0	0
T4	127365	127364	0	0
T5	337748	337736	0	0
T7	501115	501028	0	0
T11	62370	62299	0	0
T12	561907	561897	0	0
T21	12526	12475	0	0
T22	62831	62762	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	696737905	0	0
T1	428077	428072	0	0
T2	117957	117949	0	0
T3	67945	67874	0	0
T4	127365	127364	0	0
T5	337748	337736	0	0
T7	501115	501028	0	0
T11	62370	62299	0	0
T12	561907	561897	0	0
T21	12526	12475	0	0
T22	62831	62762	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T11
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T11

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T11,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T11,T4
1	0	1	Covered	T1,T2,T11
1	1	0	Covered	T3,T7,T4
1	1	1	Covered	T3,T11,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T4
0	1	Covered	T11,T4,T5
1	0	Covered	T45,T46,T49

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T11,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T45,T46,T49

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T11,T4
1	0	Covered	T24
1	1	Covered	T11,T4,T5

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T11,T4
1	Covered	T4,T5,T17

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T11,T4
1	Covered	T12,T22,T6

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T11,T4,T12
1	Covered	T2,T11,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T11,T4
1	Covered	T11,T4,T5

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T11,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T11,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T11,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T11,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T11,T4
Phase1St	198	Covered	T2,T11,T4
Phase2St	215	Covered	T2,T11,T4
Phase3St	233	Covered	T2,T11,T4
TerminalSt	249	Covered	T2,T11,T4
TimeoutSt	159	Covered	T3,T11,T4

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T2,T11,T4
IdleSt->TimeoutSt	159	Covered	T3,T11,T4
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T53,T101,T102
Phase0St->Phase1St	198	Covered	T2,T11,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T5,T25,T27
Phase1St->Phase2St	215	Covered	T2,T11,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T5,T85,T103
Phase2St->Phase3St	233	Covered	T2,T11,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T104,T24,T51
Phase3St->TerminalSt	249	Covered	T2,T11,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T11,T4
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T5,T67
TimeoutSt->Phase0St	172	Covered	T11,T4,T5

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T11,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T11,T4,T5
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T11,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T5,T67
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T53,T101,T102
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T11,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T11,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T25,T27,T66
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T11,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T11,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T5,T85,T103
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T11,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T11,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T104,T24,T51
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T11,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T11,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T11,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T11,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	696897943	221	0	0
CheckAccumTrig0_A	696897943	471	0	0
CheckAccumTrig1_A	696897943	23	0	0
CheckClr_A	696897943	197	0	0
CheckEn_A	696701005	326497903	0	0
CheckPhase0_A	696897943	550	0	0
CheckPhase1_A	696897943	539	0	0
CheckPhase2_A	696897943	526	0	0
CheckPhase3_A	696897943	518	0	0
CheckTimeout0_A	696897943	872	0	0
CheckTimeoutSt1_A	696897943	97640	0	0
CheckTimeoutSt2_A	696897943	789	0	0
CheckTimeoutStTrig_A	696897943	59	0	0
ErrorStAllEscAsserted_A	696897943	1207	0	0
ErrorStIsTerminal_A	696897943	997	0	0
EscStateOut_A	696699571	696629336	0	0
u_state_regs_A	696897943	696737905	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	221	0	0
T8	21502	35	0	0
T9	31275	62	0	0
T10	0	61	0	0
T28	0	28	0	0
T29	0	35	0	0
T30	26767	0	0	0
T31	186532	0	0	0
T32	11680	0	0	0
T33	236546	0	0	0
T34	90585	0	0	0
T35	841423	0	0	0
T36	430750	0	0	0
T37	128382	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	471	0	0
T2	117957	2	0	0
T3	67945	0	0	0
T4	127365	2	0	0
T5	337748	5	0	0
T6	0	1	0	0
T7	501115	0	0	0
T11	62370	1	0	0
T12	561907	1	0	0
T17	0	1	0	0
T20	0	2	0	0
T21	12526	0	0	0
T22	62831	2	0	0
T38	3191	0	0	0
T41	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	23	0	0
T23	99017	0	0	0
T45	492306	1	0	0
T46	831619	1	0	0
T47	608159	0	0	0
T49	0	1	0	0
T51	0	3	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	9141	0	0	0
T59	66812	0	0	0
T60	27432	0	0	0
T61	713790	0	0	0
T62	29702	0	0	0
T63	109078	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	197	0	0
T2	117957	1	0	0
T3	67945	0	0	0
T4	127365	1	0	0
T5	337748	1	0	0
T7	501115	0	0	0
T11	62370	1	0	0
T12	561907	0	0	0
T20	0	1	0	0
T21	12526	0	0	0
T22	62831	1	0	0
T25	0	1	0	0
T27	0	2	0	0
T38	3191	0	0	0
T65	0	11	0	0
T66	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696701005	326497903	0	0
T1	428077	427522	0	0
T2	117957	2599	0	0
T3	67945	25434	0	0
T4	127365	115630	0	0
T5	337748	189127	0	0
T7	501115	501027	0	0
T11	62370	7355	0	0
T12	561907	21443	0	0
T21	12526	12474	0	0
T22	62831	16254	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	550	0	0
T2	117957	2	0	0
T3	67945	0	0	0
T4	127365	3	0	0
T5	337748	6	0	0
T6	0	2	0	0
T7	501115	0	0	0
T11	62370	2	0	0
T12	561907	1	0	0
T17	0	1	0	0
T20	0	4	0	0
T21	12526	0	0	0
T22	62831	2	0	0
T38	3191	0	0	0
T40	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	539	0	0
T2	117957	2	0	0
T3	67945	0	0	0
T4	127365	3	0	0
T5	337748	5	0	0
T6	0	2	0	0
T7	501115	0	0	0
T11	62370	2	0	0
T12	561907	1	0	0
T17	0	1	0	0
T20	0	4	0	0
T21	12526	0	0	0
T22	62831	2	0	0
T38	3191	0	0	0
T40	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	526	0	0
T2	117957	2	0	0
T3	67945	0	0	0
T4	127365	3	0	0
T5	337748	4	0	0
T6	0	2	0	0
T7	501115	0	0	0
T11	62370	2	0	0
T12	561907	1	0	0
T17	0	1	0	0
T20	0	4	0	0
T21	12526	0	0	0
T22	62831	2	0	0
T38	3191	0	0	0
T40	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	518	0	0
T2	117957	2	0	0
T3	67945	0	0	0
T4	127365	3	0	0
T5	337748	4	0	0
T6	0	2	0	0
T7	501115	0	0	0
T11	62370	2	0	0
T12	561907	1	0	0
T17	0	1	0	0
T20	0	4	0	0
T21	12526	0	0	0
T22	62831	2	0	0
T38	3191	0	0	0
T40	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	872	0	0
T3	67945	4	0	0
T4	127365	1	0	0
T5	337748	3	0	0
T6	0	1	0	0
T7	501115	0	0	0
T11	62370	1	0	0
T12	561907	0	0	0
T20	0	6	0	0
T21	12526	0	0	0
T22	62831	0	0	0
T25	0	1	0	0
T38	3191	0	0	0
T39	25212	0	0	0
T40	0	1	0	0
T42	0	2	0	0
T67	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	97640	0	0
T3	67945	786	0	0
T4	127365	212	0	0
T5	337748	377	0	0
T6	0	38	0	0
T7	501115	0	0	0
T11	62370	432	0	0
T12	561907	0	0	0
T20	0	1808	0	0
T21	12526	0	0	0
T22	62831	0	0	0
T25	0	25	0	0
T38	3191	0	0	0
T39	25212	0	0	0
T40	0	156	0	0
T42	0	510	0	0
T67	0	196	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	789	0	0
T3	67945	4	0	0
T4	127365	0	0	0
T5	337748	2	0	0
T7	501115	0	0	0
T11	62370	0	0	0
T12	561907	0	0	0
T20	0	4	0	0
T21	12526	0	0	0
T22	62831	0	0	0
T25	0	1	0	0
T27	0	1	0	0
T38	3191	0	0	0
T39	25212	0	0	0
T42	0	2	0	0
T67	0	1	0	0
T69	0	52	0	0
T70	0	7	0	0
T71	0	3	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	59	0	0
T4	127365	1	0	0
T5	337748	1	0	0
T6	0	1	0	0
T11	62370	1	0	0
T12	561907	0	0	0
T17	889738	0	0	0
T18	218686	0	0	0
T20	0	2	0	0
T22	62831	0	0	0
T26	39720	0	0	0
T38	3191	0	0	0
T39	25212	0	0	0
T40	0	1	0	0
T73	0	1	0	0
T75	0	1	0	0
T77	0	1	0	0
T79	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	1207	0	0
T8	21502	149	0	0
T9	31275	359	0	0
T10	0	342	0	0
T28	0	179	0	0
T29	0	178	0	0
T30	26767	0	0	0
T31	186532	0	0	0
T32	11680	0	0	0
T33	236546	0	0	0
T34	90585	0	0	0
T35	841423	0	0	0
T36	430750	0	0	0
T37	128382	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	997	0	0
T8	21502	119	0	0
T9	31275	299	0	0
T10	0	282	0	0
T28	0	149	0	0
T29	0	148	0	0
T30	26767	0	0	0
T31	186532	0	0	0
T32	11680	0	0	0
T33	236546	0	0	0
T34	90585	0	0	0
T35	841423	0	0	0
T36	430750	0	0	0
T37	128382	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696699571	696629336	0	0
T1	428077	428072	0	0
T2	117957	117949	0	0
T3	67945	67874	0	0
T4	127365	127364	0	0
T5	337748	337736	0	0
T7	501115	501028	0	0
T11	62370	62299	0	0
T12	561907	561897	0	0
T21	12526	12475	0	0
T22	62831	62762	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	696737905	0	0
T1	428077	428072	0	0
T2	117957	117949	0	0
T3	67945	67874	0	0
T4	127365	127364	0	0
T5	337748	337736	0	0
T7	501115	501028	0	0
T11	62370	62299	0	0
T12	561907	561897	0	0
T21	12526	12475	0	0
T22	62831	62762	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T3,T11
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T11

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T11,T4

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T3,T11,T4
1	0	1	Covered	T1,T11,T12
1	1	0	Covered	T7,T4,T5
1	1	1	Covered	T3,T4,T5

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T3,T4,T5
0	1	Covered	T5,T20,T42
1	0	Covered	T5,T70,T93

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T3,T4,T5
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T70,T93

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T23
1	1	Covered	T5,T20,T42

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T4,T12,T5
1	Covered	T2,T11,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T11,T4
1	Covered	T12,T5,T6

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T11,T4
1	Covered	T4,T40,T65

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T11,T4
1	Covered	T5,T18,T13

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T8,T9,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T11,T5,T22

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T11,T4,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T2,T4,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T9,T10
1	0	Covered	T4,T12,T5

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T8,T9,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T11,T4
Phase1St	198	Covered	T2,T11,T4
Phase2St	215	Covered	T2,T11,T4
Phase3St	233	Covered	T2,T11,T4
TerminalSt	249	Covered	T2,T11,T4
TimeoutSt	159	Covered	T3,T4,T5

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T8,T9,T10
IdleSt->Phase0St	152	Covered	T2,T11,T4
IdleSt->TimeoutSt	159	Covered	T3,T4,T5
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T42,T105,T101
Phase0St->Phase1St	198	Covered	T2,T11,T4
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T106,T107,T89
Phase1St->Phase2St	215	Covered	T2,T11,T4
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T12,T70,T108
Phase2St->Phase3St	233	Covered	T2,T11,T4
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T5,T108,T109
Phase3St->TerminalSt	249	Covered	T2,T11,T4
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T4,T12,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T3,T4,T5
TimeoutSt->Phase0St	172	Covered	T5,T20,T42

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T4
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T20,T42
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T3,T4,T5
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T42,T105,T101
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T11,T4
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T11,T4
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T106,T107,T89
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T11,T4
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T11,T4
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T12,T70,T108
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T11,T4
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T11,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T5,T108,T109
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T11,T4
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T11,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T12,T5,T40
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T11,T4
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T10

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	696897943	256	0	0
CheckAccumTrig0_A	696897943	521	0	0
CheckAccumTrig1_A	696897943	17	0	0
CheckClr_A	696897943	229	0	0
CheckEn_A	696701005	315674520	0	0
CheckPhase0_A	696897943	584	0	0
CheckPhase1_A	696897943	578	0	0
CheckPhase2_A	696897943	567	0	0
CheckPhase3_A	696897943	552	0	0
CheckTimeout0_A	696897943	1148	0	0
CheckTimeoutSt1_A	696897943	150144	0	0
CheckTimeoutSt2_A	696897943	1077	0	0
CheckTimeoutStTrig_A	696897943	54	0	0
ErrorStAllEscAsserted_A	696897943	1098	0	0
ErrorStIsTerminal_A	696897943	888	0	0
EscStateOut_A	696699571	696629336	0	0
u_state_regs_A	696897943	696737905	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	256	0	0
T8	21502	24	0	0
T9	31275	91	0	0
T10	0	77	0	0
T28	0	42	0	0
T29	0	22	0	0
T30	26767	0	0	0
T31	186532	0	0	0
T32	11680	0	0	0
T33	236546	0	0	0
T34	90585	0	0	0
T35	841423	0	0	0
T36	430750	0	0	0
T37	128382	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	521	0	0
T2	117957	1	0	0
T3	67945	0	0	0
T4	127365	3	0	0
T5	337748	6	0	0
T6	0	2	0	0
T7	501115	0	0	0
T11	62370	1	0	0
T12	561907	3	0	0
T18	0	1	0	0
T19	0	1	0	0
T21	12526	0	0	0
T22	62831	1	0	0
T38	3191	0	0	0
T40	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	17	0	0
T5	337748	1	0	0
T6	771263	0	0	0
T17	889738	0	0	0
T18	218686	0	0	0
T19	105335	0	0	0
T22	62831	0	0	0
T26	39720	0	0	0
T38	3191	0	0	0
T39	25212	0	0	0
T51	0	1	0	0
T64	35755	0	0	0
T70	0	1	0	0
T93	0	2	0	0
T110	0	1	0	0
T111	0	1	0	0
T112	0	1	0	0
T113	0	1	0	0
T114	0	2	0	0
T115	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	229	0	0
T5	337748	4	0	0
T12	561907	2	0	0
T13	0	1	0	0
T17	889738	0	0	0
T18	218686	0	0	0
T19	105335	0	0	0
T20	0	1	0	0
T22	62831	0	0	0
T26	39720	0	0	0
T27	0	1	0	0
T38	3191	0	0	0
T39	25212	0	0	0
T40	0	1	0	0
T42	0	4	0	0
T64	35755	0	0	0
T65	0	3	0	0
T66	0	1	0	0
T116	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696701005	315674520	0	0
T1	428077	3085	0	0
T2	117957	594	0	0
T3	67945	9174	0	0
T4	127365	107661	0	0
T5	337748	141299	0	0
T7	501115	501027	0	0
T11	62370	7556	0	0
T12	561907	8805	0	0
T21	12526	12474	0	0
T22	62831	17021	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	584	0	0
T2	117957	1	0	0
T3	67945	0	0	0
T4	127365	3	0	0
T5	337748	8	0	0
T6	0	2	0	0
T7	501115	0	0	0
T11	62370	1	0	0
T12	561907	3	0	0
T18	0	1	0	0
T19	0	1	0	0
T21	12526	0	0	0
T22	62831	1	0	0
T38	3191	0	0	0
T40	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	578	0	0
T2	117957	1	0	0
T3	67945	0	0	0
T4	127365	3	0	0
T5	337748	8	0	0
T6	0	2	0	0
T7	501115	0	0	0
T11	62370	1	0	0
T12	561907	3	0	0
T18	0	1	0	0
T19	0	1	0	0
T21	12526	0	0	0
T22	62831	1	0	0
T38	3191	0	0	0
T40	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	567	0	0
T2	117957	1	0	0
T3	67945	0	0	0
T4	127365	3	0	0
T5	337748	8	0	0
T6	0	2	0	0
T7	501115	0	0	0
T11	62370	1	0	0
T12	561907	2	0	0
T18	0	1	0	0
T19	0	1	0	0
T21	12526	0	0	0
T22	62831	1	0	0
T38	3191	0	0	0
T40	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	552	0	0
T2	117957	1	0	0
T3	67945	0	0	0
T4	127365	3	0	0
T5	337748	7	0	0
T6	0	2	0	0
T7	501115	0	0	0
T11	62370	1	0	0
T12	561907	2	0	0
T18	0	1	0	0
T19	0	1	0	0
T21	12526	0	0	0
T22	62831	1	0	0
T38	3191	0	0	0
T40	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	1148	0	0
T3	67945	10	0	0
T4	127365	2	0	0
T5	337748	29	0	0
T7	501115	0	0	0
T11	62370	0	0	0
T12	561907	0	0	0
T19	0	1	0	0
T20	0	6	0	0
T21	12526	0	0	0
T22	62831	0	0	0
T27	0	1	0	0
T38	3191	0	0	0
T39	25212	0	0	0
T42	0	8	0	0
T65	0	90	0	0
T69	0	1	0	0
T70	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	150144	0	0
T3	67945	2277	0	0
T4	127365	302	0	0
T5	337748	3118	0	0
T7	501115	0	0	0
T11	62370	0	0	0
T12	561907	0	0	0
T19	0	40	0	0
T20	0	942	0	0
T21	12526	0	0	0
T22	62831	0	0	0
T27	0	60	0	0
T38	3191	0	0	0
T39	25212	0	0	0
T42	0	642	0	0
T65	0	7479	0	0
T69	0	123	0	0
T70	0	39	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	1077	0	0
T3	67945	10	0	0
T4	127365	2	0	0
T5	337748	27	0	0
T7	501115	0	0	0
T11	62370	0	0	0
T12	561907	0	0	0
T19	0	1	0	0
T20	0	4	0	0
T21	12526	0	0	0
T22	62831	0	0	0
T27	0	1	0	0
T38	3191	0	0	0
T39	25212	0	0	0
T42	0	6	0	0
T65	0	90	0	0
T69	0	1	0	0
T70	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	54	0	0
T5	337748	1	0	0
T6	771263	0	0	0
T17	889738	0	0	0
T18	218686	0	0	0
T19	105335	0	0	0
T20	0	2	0	0
T22	62831	0	0	0
T26	39720	0	0	0
T38	3191	0	0	0
T39	25212	0	0	0
T42	0	2	0	0
T45	0	2	0	0
T47	0	2	0	0
T64	35755	0	0	0
T117	0	1	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	1	0	0
T121	0	3	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	1098	0	0
T8	21502	159	0	0
T9	31275	321	0	0
T10	0	325	0	0
T28	0	143	0	0
T29	0	150	0	0
T30	26767	0	0	0
T31	186532	0	0	0
T32	11680	0	0	0
T33	236546	0	0	0
T34	90585	0	0	0
T35	841423	0	0	0
T36	430750	0	0	0
T37	128382	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	888	0	0
T8	21502	129	0	0
T9	31275	261	0	0
T10	0	265	0	0
T28	0	113	0	0
T29	0	120	0	0
T30	26767	0	0	0
T31	186532	0	0	0
T32	11680	0	0	0
T33	236546	0	0	0
T34	90585	0	0	0
T35	841423	0	0	0
T36	430750	0	0	0
T37	128382	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696699571	696629336	0	0
T1	428077	428072	0	0
T2	117957	117949	0	0
T3	67945	67874	0	0
T4	127365	127364	0	0
T5	337748	337736	0	0
T7	501115	501028	0	0
T11	62370	62299	0	0
T12	561907	561897	0	0
T21	12526	12475	0	0
T22	62831	62762	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	696897943	696737905	0	0
T1	428077	428072	0	0
T2	117957	117949	0	0
T3	67945	67874	0	0
T4	127365	127364	0	0
T5	337748	337736	0	0
T7	501115	501028	0	0
T11	62370	62299	0	0
T12	561907	561897	0	0
T21	12526	12475	0	0
T22	62831	62762	0	0