Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	40960	1			T15	4		T22	38		T4	29
class_i[0x1]	67087	1			T8	3315		T22	4		T4	9
class_i[0x2]	91881	1			T1	3		T15	558		T22	271
class_i[0x3]	41179	1			T15	63		T4	21		T24	10

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	59610	1			T1	2		T8	868		T15	13
alert[0x1]	58043	1			T1	1		T8	824		T15	23
alert[0x2]	62459	1			T8	849		T15	558		T22	257
alert[0x3]	60995	1			T8	774		T15	31		T22	9

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

240801

1

T8

3315

T15

625

T22

313

esc_ping_fail

306

1

T1

3

T17

2

T18

7

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	59524	1			T8	868		T15	13		T22	22
esc_integrity_fail	alert[0x1]	57971	1			T8	824		T15	23		T22	25
esc_integrity_fail	alert[0x2]	62378	1			T8	849		T15	558		T22	257
esc_integrity_fail	alert[0x3]	60928	1			T8	774		T15	31		T22	9
esc_ping_fail	alert[0x0]	86	1			T1	2		T18	2		T90	3
esc_ping_fail	alert[0x1]	72	1			T1	1		T17	1		T18	3
esc_ping_fail	alert[0x2]	81	1			T18	2		T90	3		T242	3
esc_ping_fail	alert[0x3]	67	1			T17	1		T90	3		T242	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	40886	1			T15	4		T22	38		T4	29
esc_integrity_fail	class_i[0x1]	66990	1			T8	3315		T22	4		T4	9
esc_integrity_fail	class_i[0x2]	91823	1			T15	558		T22	271		T5	12
esc_integrity_fail	class_i[0x3]	41102	1			T15	63		T4	21		T24	10
esc_ping_fail	class_i[0x0]	74	1			T18	2		T90	10		T310	1
esc_ping_fail	class_i[0x1]	97	1			T17	1		T18	3		T310	1
esc_ping_fail	class_i[0x2]	58	1			T1	3		T17	1		T18	1
esc_ping_fail	class_i[0x3]	77	1			T18	1		T242	9		T316	2