Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	695263121	0	0	624
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	695263121	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	695263121	695089685	0	0
tb.dut.CheckAccuCntDw	0	0	624	624	0	0
tb.dut.CheckEscCntDw	0	0	624	624	0	0
tb.dut.CheckNAlerts	0	0	624	624	0	0
tb.dut.CheckNClasses	0	0	624	624	0	0
tb.dut.CheckNEscSev	0	0	624	624	0	0
tb.dut.CrashdumpKnownO_A	0	0	695263121	695089685	0	0
tb.dut.EdnKnownO_A	0	0	695263121	695089685	0	0
tb.dut.EscPKnownO_A	0	0	695263121	695089685	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	695263121	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	695263121	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	695263121	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	695263121	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	695263121	80	0	0
tb.dut.IrqAKnownO_A	0	0	695263121	695089685	0	0
tb.dut.IrqBKnownO_A	0	0	695263121	695089685	0	0
tb.dut.IrqCKnownO_A	0	0	695263121	695089685	0	0
tb.dut.IrqDKnownO_A	0	0	695263121	695089685	0	0
tb.dut.TlAReadyKnownO_A	0	0	695263121	695089685	0	0
tb.dut.TlDValidKnownO_A	0	0	695263121	695089685	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	721421236	2761657	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	721421236	14370	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	721421236	14237	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	721421236	14377	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	721421236	14077	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	721421236	14091	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	721421236	14213	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	721421236	14144	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	721421236	14168	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	721421236	13845	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	721421236	15362	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	721421236	13800	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	721421236	14231	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	721421236	14227	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	721421236	14270	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	721421236	15369	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	721421236	14210	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	721421236	15212	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	721421236	15123	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	721421236	14161	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	721421236	14778	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	721421236	14210	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	721421236	15554	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	721421236	15351	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	721421236	13989	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	721421236	14026	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	721421236	14215	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	721421236	14306	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	721421236	15495	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	721421236	15218	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	721421236	14702	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	721421236	14055	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	721421236	14245	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	721421236	14325	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	721421236	15122	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	721421236	15383	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	721421236	14858	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	721421236	15172	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	721421236	13864	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	721421236	14153	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	721421236	14427	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	721421236	14086	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	721421236	14798	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	721421236	14538	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	721421236	14457	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	721421236	14276	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	721421236	14229	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	721421236	14565	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	721421236	15319	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	721421236	14407	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	721421236	15269	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	721421236	14340	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	721421236	14055	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	721421236	14063	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	721421236	15276	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	721421236	13818	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	721421236	15254	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	721421236	14620	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	721421236	14195	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	721421236	14130	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	721421236	14023	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	721421236	14240	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	721421236	15238	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	721421236	15290	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	721421236	15933	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	721421236	14082	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	721421236	15278	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	721421236	14031	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	721421236	14414	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	721421236	14220	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	721421236	27338	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	721421236	15021	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	721421236	15168	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	721421236	14373	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	721421236	14332	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	721421236	13909	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	721421236	13969	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	721421236	14078	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	721421236	15353	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	695263121	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	695263121	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	695263121	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	695263121	5885	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	695263121	213197	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	695263121	356909686	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	695263121	238	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	695263121	837	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	695263121	37	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	695263121	390	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	695102115	256063556	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	695263121	943	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	695263121	926	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	695263121	899	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	695263121	887	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	695263121	1239	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	695263121	142715	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	695263121	1117	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	695263121	84	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	695263121	1275	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	695263121	1035	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	695100578	695028611	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	695263121	695089685	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	695263121	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	695263121	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	695263121	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	695263121	3042	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	695263121	177840	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	695263121	423685676	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	695263121	247	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	695263121	509	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	695263121	30	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	695263121	262	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	695102115	326983737	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	695263121	618	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	695263121	605	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	695263121	599	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	695263121	586	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	695263121	1959	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	695263121	192486	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	695263121	1838	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	695263121	88	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	695263121	1290	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	695263121	1050	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	695100578	695028611	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	695263121	695089685	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	695263121	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	695263121	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	695263121	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	695263121	3747	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	695263121	201137	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	695263121	382365075	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	695263121	268	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	695263121	497	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	695263121	24	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	695263121	216	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	695102115	303389235	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	695263121	584	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	695263121	577	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	695263121	567	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	695263121	558	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	695263121	1460	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	695263121	157252	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	695263121	1367	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	695263121	68	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	695263121	1285	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	695263121	1045	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	695100578	695028611	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	695263121	695089685	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	695263121	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	695263121	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	695263121	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	695263121	2659	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	695263121	173518	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	695263121	445585541	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	695263121	198	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	695263121	478	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	695263121	29	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	695263121	220	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	695102115	351089115	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	695263121	562	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	695263121	553	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	695263121	539	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	695263121	529	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	695263121	1645	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	695263121	159318	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	695263121	1549	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	695263121	62	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	695263121	1189	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	695263121	949	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	695100578	695028611	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	695263121	695089685	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	721421236	133205443	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	721421236	720709451	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	721421236	720709451	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	721421236	195364821	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	721421236	720709451	0	0
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