Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.59	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	4	36	90.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	4	36	90.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	84	1			T8	1		T13	3		T25	1
class_index[0x1]	88	1			T25	1		T77	1		T80	1
class_index[0x2]	68	1			T19	1		T24	1		T79	1
class_index[0x3]	62	1			T4	1		T52	1		T78	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	129	1			T8	1		T13	3		T19	1
intr_timeout_cnt[1]	73	1			T4	1		T77	1		T80	1
intr_timeout_cnt[2]	26	1			T100	2		T136	1		T106	3
intr_timeout_cnt[3]	19	1			T135	1		T118	1		T136	2
intr_timeout_cnt[4]	10	1			T24	1		T81	1		T265	2
intr_timeout_cnt[5]	16	1			T81	1		T36	1		T29	2
intr_timeout_cnt[6]	10	1			T100	2		T266	1		T267	1
intr_timeout_cnt[7]	10	1			T86	1		T116	1		T124	1
intr_timeout_cnt[8]	2	1			T204	1		T268	1		-	-
intr_timeout_cnt[9]	7	1			T267	1		T269	1		T244	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	4	36	90.00	4

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[8] , intr_timeout_cnt[9]]	--	--	2
[class_index[0x3]]	[intr_timeout_cnt[8]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	40	1			T8	1		T13	3		T25	1
class_index[0x0]	intr_timeout_cnt[1]	15	1			T80	1		T94	1		T270	1
class_index[0x0]	intr_timeout_cnt[2]	9	1			T100	1		T136	1		T106	3
class_index[0x0]	intr_timeout_cnt[3]	7	1			T118	1		T136	1		T106	1
class_index[0x0]	intr_timeout_cnt[4]	3	1			T81	1		T271	1		T215	1
class_index[0x0]	intr_timeout_cnt[5]	3	1			T36	1		T29	1		T100	1
class_index[0x0]	intr_timeout_cnt[6]	2	1			T266	1		T267	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	2	1			T86	1		T206	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	3	1			T272	1		T273	2		-	-
class_index[0x1]	intr_timeout_cnt[0]	36	1			T25	1		T80	1		T81	5
class_index[0x1]	intr_timeout_cnt[1]	24	1			T77	1		T86	1		T58	1
class_index[0x1]	intr_timeout_cnt[2]	9	1			T100	1		T214	1		T269	1
class_index[0x1]	intr_timeout_cnt[3]	4	1			T136	1		T274	1		T99	1
class_index[0x1]	intr_timeout_cnt[4]	4	1			T265	2		T275	2		-	-
class_index[0x1]	intr_timeout_cnt[5]	6	1			T81	1		T29	1		T261	1
class_index[0x1]	intr_timeout_cnt[6]	3	1			T100	1		T276	1		T272	1
class_index[0x1]	intr_timeout_cnt[7]	2	1			T124	1		T277	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	25	1			T19	1		T79	1		T83	1
class_index[0x2]	intr_timeout_cnt[1]	21	1			T82	1		T44	2		T29	1
class_index[0x2]	intr_timeout_cnt[2]	4	1			T214	1		T278	3		-	-
class_index[0x2]	intr_timeout_cnt[3]	6	1			T279	1		T280	1		T281	1
class_index[0x2]	intr_timeout_cnt[4]	1	1			T24	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[5]	4	1			T267	1		T282	1		T283	1
class_index[0x2]	intr_timeout_cnt[6]	1	1			T271	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	2	1			T116	1		T269	1		-	-
class_index[0x2]	intr_timeout_cnt[8]	2	1			T204	1		T268	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	2	1			T244	1		T284	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	28	1			T52	1		T78	1		T134	1
class_index[0x3]	intr_timeout_cnt[1]	13	1			T4	1		T29	1		T100	1
class_index[0x3]	intr_timeout_cnt[2]	4	1			T281	1		T272	1		T278	1
class_index[0x3]	intr_timeout_cnt[3]	2	1			T135	1		T285	1		-	-
class_index[0x3]	intr_timeout_cnt[4]	2	1			T214	1		T99	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	3	1			T279	1		T286	1		T215	1
class_index[0x3]	intr_timeout_cnt[6]	4	1			T100	1		T268	1		T261	1
class_index[0x3]	intr_timeout_cnt[7]	4	1			T204	1		T268	2		T287	1
class_index[0x3]	intr_timeout_cnt[9]	2	1			T267	1		T269	1		-	-